JP3092223B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, the present invention relates to a semiconductor memory device having a redundant circuit.

[0002]

2. Description of the Related Art A conventional semiconductor memory device having a redundant circuit has a circuit configuration as shown in FIG.

In FIG. 9, a main cell section 110, a redundant cell section 117, a row decoder 109, an address buffer 107, a column decoder 108, a sense amplifier write circuit 112, and a redundant sense amplifier write circuit are provided. Circuit 112 '
, A column selection transistor group 111, an address input terminal (A0 to Am) 104, an I / O terminal 114, an input / output buffer 113, and a fuse determination circuit (1) 001 to
(N) 00n, fuse determination circuit (s) 00s, 2
1, an exclusive OR (EOR) circuit 100, a NAND circuit 101, an inverter circuit 102, and two n-type transistors 103 are shown.

When there is a defect in the main cell portion 110, the defective portion is replaced with a redundant cell portion 117 so that all the memory cells appear to be non-defective. The replacement with the redundant cell unit 117 is generally performed by storing replacement data by cutting a fuse or writing in an EPROM completely shielded from ultraviolet rays.

Address data is stored in the fuse determination circuits (1) 001 to (n) 00n, and whether or not a redundant circuit is used is stored in the fuse determination circuit (s) 00s. The fuse determination circuits (1) to (n)
And the output of the address buffer 113 coincide with each other and the output of the fuse determination circuit (s) 00s indicates the redundant use, the redundant cell unit 117 is accessed.

[0006]

In such a conventional redundant circuit, it is difficult to collect individual data of the fuse determination circuit, such as a power supply voltage margin of the fuse determination circuit, and ON / OFF information of the fuse. .

Therefore, in the case of the fuse cutting method, it is determined whether the fuse is completely cut or not.
When an M cell is used, it is very complicated to check whether or not the change in the threshold voltage of the cell is sufficient.

An object of the present invention is to provide a semiconductor memory device which solves the above-mentioned drawbacks and enables a simple and reliable check of a redundant circuit.

[0009]

According to the structure of the present invention, in a semiconductor memory device provided with a redundant circuit, one or more sets of redundant memory cell sections provided in a row direction or a column direction are provided.
A fuse element group for storing information for switching the redundant memory cell unit a plurality of sets of corresponding to the redundant memory cell section, selects and outputs the fuse data of a desired fuse element group among the plurality of fuse element groups a fuse data selection transistors, and a test mode setting circuit for setting the test mode by an input signal from a certain external terminal, double
Address signal lines connected to the number of address input terminals
Connected in series between the power supply terminal and the resistor.
Transformer connected to the output of the
A plurality of fuse data output circuits comprising
In the test mode, the plurality of fuse data outputs
Leakage of the plurality of address input terminals connected to the circuit;
The presence or absence corresponds to the fuse data .

[0010]

FIG. 1 is a block diagram showing a first division of a three-part drawing of a semiconductor memory device according to a first embodiment of the present invention.
FIG. 2 is a block diagram showing a second division, and FIG. 3 is a block diagram showing a third division.

In FIG. 1, FIG. 2 and FIG. 3, the same reference numerals are connected to the alphabetic wirings A to P, respectively.

In this embodiment, the redundant cell section access circuits (1) to (m), the selector 118, the fuse data selecting transistor group 130, the NOR circuit 115,
I / O buffer 113 and sense amplifier writing circuit 112
, Test mode setting circuit 105, address buffer 107, I / O terminal 114, I / O buffer 113
, Sense amplifier writing circuit 112, column selecting transistor group 111, main cell unit 110, fuse data output circuit 131, column decoder 108, row decoder 109, redundant cell unit 116, fuse data And an output circuit 200.

In this embodiment, an example is shown in which m sets of redundant cell portions for n row addresses are provided.

During normal operation, test mode setting circuit 1
05 becomes inactive, and its output signal TES (negative value) becomes H level. At this time, the n-type transistor M
_{1 to} M _n and M _S become conductive, and the selector 11
8 (see FIG. 8) are all at L level, so that all the fuse data selecting transistor groups 130 are in a non-conductive state.

Therefore, fuse data signal lines F ₁ to F ₁
F _n, F _s are all set to L level. At this time, n-type transistor 103 in fuse data output circuit 200 (FIG. 7) is turned off. From the above, in the normal operation, all the circuits related to the fuse data output are inactive, and the normal operation is performed.

On the other hand, when a specific mode is applied to a certain address terminal to set the test mode, the output signal TES (negative value) of the test mode setting circuit 105 goes low. Then, the selector circuit 118 becomes active, only the output signal Y _s2 corresponding to the address signal input to the address terminals Ai to Ay becomes H level, one set of the fuse data selection transistor group 130 is selected, and data sets of the fuse determination circuit is output fuse data signal lines F ₁ to F _s, the F _n. By the way, at this time, since the n-type transistors M _{1 to} M _n and M _S in the drawing are in a non-conductive state, the data of the fuse judgment circuit is supplied to the fuse data output circuit 200 through the fuse data signal lines F _{1 to} F _s and F _n. Is transmitted to Further, the above-described fuse data output circuit 200 is connected to the address input terminal 104.

Next, the fuse data output circuit 200 of FIG. 3 will be described with reference to FIG. The fuse data output circuit includes an address input signal line, a resistor 120 and an n-type transistor 103 inserted in series with a reference potential, and a fuse data signal line _Fi is connected to a gate terminal of the n-type transistor 103. . Now, when the data of the fuse determination circuit (FIG. 1) is at "H" level, the fuse data signal line is also at H level, and the n-type transistor 103 is turned on. Therefore, if an H level is applied to the address input terminal 104 at this time, a current flows from the address input terminal 104 to the reference potential.

Next, the data of the fuse judgment circuit is set to "L".
At the time of the level, the above-mentioned fuse data signal line becomes the L level, the above-mentioned n-type transistor 103 becomes non-conductive, and even if the H level is applied to the address input terminal 104, a path through which a current flows does not occur in a circuit.

Therefore, the address input terminal 104
By applying a level and measuring the input terminal leak at the address terminal, data of the fuse determination circuit can be detected by the presence or absence of a leak current.

In FIG. 8, the selector 118 shown in FIG.
Test mode setting circuit 1 _receiving address input _Ak
35, an address buffer 136 to which (A _i ,..., A _{i + n−1} ) is input, a NAND gate 101, and an inverter 102, and outputs selector output signals Y _{s1 ,.} It is.

FIGS. 4, 5, and 6 show the first, second, and third divisions of the semiconductor memory device according to the second embodiment of the present invention. FIG.

4, 5, and 6, wirings 1 to 22 having the same arithmetic numerals are connected to form an entire circuit.

The block diagram of the second embodiment of the present invention is a case in which m sets of redundant cell portions for n row addresses are provided.

Fuse data selection transistor group 13
The configuration of the 0 and fuse data output circuit 200 is basically the same as that of the first embodiment. The difference is in the method of selecting the fuse data selection transistor group 130. In the present embodiment, the fuse data selection transistor group 130 is selected by the output of the row decoder. When the test mode signal TES (negative value) becomes L level, the CMOS transmission gate 106 becomes active and the row is turned off. The output of the decoder is connected to the fuse data selection transistor group 130.

Therefore, by inputting an address signal to the address input terminal 104, one set of an arbitrary fuse data selection transistor group can be selected.

[0026]

As described above, according to the present invention, by setting a test mode in which the data of each redundant fuse decision circuit is output to an external terminal, each characteristic of the fuse decision circuit is evaluated and selected. In addition to this, there is an effect that it is possible to easily detect which address is input and which redundant cell portion is used.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first division in a three-part drawing of a semiconductor memory device according to a first embodiment of the present invention;

FIG. 2 is a block diagram showing a second division of FIG. 1;

FIG. 3 is a block diagram showing a third division of FIG. 1;

FIG. 4 is a block diagram showing a first division in a three-part drawing of a semiconductor memory device according to a second embodiment of the present invention;

FIG. 5 is a block diagram showing a second division of FIG. 4;

FIG. 6 is a block diagram showing a third division of FIG. 4;

FIG. 7 is a block diagram showing a fuse data output circuit of FIG. 1;

FIG. 8 is a block diagram illustrating the selector of FIG. 1;

FIG. 9 is a block diagram showing a conventional semiconductor memory device.

[Explanation of symbols]

001, 00n, 00s Fuse judgment circuit 100 EOR circuit 101 NAND circuit 102 Inverter circuit 103 N-type transistor 104 Address input terminal 105 Test mode setting circuit 106 CMOS translate gate 107 Address buffer 108 Column decoder 109 Row decoder 110 Main cell section 111 Column Selection transistor 112 Sense amplifier / write circuit 113 I / O buffer 114 I / O terminal 115 NOR circuit 116 Redundant cell section (row) 117 Redundant cell section (column) 118 Selector circuit 200 Fuse cell margin circuit 119 Input protection 120 Resistance M ₁ , M _n , M _s n-type transistors F _{1 to} F _n , F _s fuse data signal line TES (negative value) Test mode setting signal

Claims (1)

(57) [Claims] In a semiconductor memory device provided with a redundant circuit, one or more sets of redundant memory cell units provided in a row direction or a column direction and a plurality of sets of the redundant memory cells corresponding to the redundant memory cell units. a fuse element group for storing information for switching the memory cell portion, the plurality of fuse element group select fuse data of a desired fuse element group output
A fuse data selection transistor group, a test mode setting circuit for setting a test mode by an input signal from an external terminal, and a plurality of address data input terminals.
Resistors connected in series between the number of address signal lines and the power supply end
The gate of the fuse data selection transistor group
Multiple fuse data consisting of transistors connected to the force
A data output circuit, and in the test mode, the plurality of
The plurality of addresses connected to a fuse data output circuit
The presence or absence of a leak at the input terminal corresponds to the fuse data.
The semiconductor memory device characterized in that is.