JPH0541099A - Semiconductor storing device - Google Patents

Abstract

PURPOSE:To investigate respective characteristics of a fuse deciding circuit and to easily detect that any redundant cell part is used to any address input. CONSTITUTION:This device is provided with a test mode setting circuit 105 having the input signal of a certain address terminal as an input and having a test mode setting signal as an output and a fuse data selecting transistor group 130 activated by the above-mentioned test mode setting signal and outputting the data content of the fuse deciding circuit storing an address data, etc., for the redundant to the outside of a semiconductor storing device and a fuse data output circuit 200.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, it relates to a semiconductor memory device having a redundant circuit.

[0002]

2. Description of the Related Art A conventional semiconductor memory device having a redundant circuit has a circuit configuration as shown in FIG.

In FIG. 9, a main cell section 110, a redundant cell section 117, a row decoder 109, an address buffer 107, a column decoder 108, a sense amplifier write circuit 112, and a redundant sense amplifier write. Circuit 112 '
A column selection transistor group 111, an address input terminal (A0 to Am) 104, an I / O terminal 114, an input / output buffer 113, and a fuse determination circuit (1) 001 to 001.
(N) 00n, fuse determination circuit (s) 00s, 2
An exclusive OR (EOR) circuit 100, a NAND circuit 101, an inverter circuit 102, and two n-type transistors 103 are shown.

When a defect exists in the main cell section 110, the defective section is replaced with a redundant cell section 117 so that all the memory cells are regarded as non-defective. The replacement with the redundant cell unit 117 is generally performed by storing replacement data by cutting a fuse or writing in an EPROM completely shielded from ultraviolet rays.

Fuse determination circuit (1) 001 to fuse determination circuit (n) 00n store address data, and fuse determination circuit (s) 00s stores whether or not a redundant circuit is used. The fuse determination circuits (1) to (n)
2 and the output of the address buffer 113 match, and the output of the fuse determination circuit (s) 00s indicates redundant use, the redundant cell section 117 is accessed.

[0006]

In such a conventional redundancy circuit, it is difficult to collect individual data of the fuse determination circuit, such as the power supply voltage margin of the fuse determination circuit, fuse ON / OFF information, and the like. ..

Therefore, in the case of the fuse cutting method, whether or not the fuse is completely cut, or PRO
When the M cell is used, it is very complicated to check whether or not the change in the threshold voltage of the cell is sufficient.

It is an object of the present invention to provide a semiconductor memory device which solves the above-mentioned drawbacks and allows the redundant circuit to be checked easily and surely.

[0009]

According to the structure of the present invention, in a semiconductor memory device having a redundant circuit, one set or a plurality of sets of redundant memory cell portions provided in the row direction or the column direction,
A fuse element group for storing information for switching the redundant memory cell section, one set or a plurality of sets corresponding to the redundant memory cell section, a fuse configuring the fuse element group, and each of the fuse element groups. A fuse data output circuit for directly outputting the stored individual data to an external terminal, and a fuse data selection transistor group for connecting data of a desired fuse element among a plurality of fuse element groups to the fuse data output circuit. And a test mode setting circuit that outputs an internal signal from an external terminal according to an input signal and sets a test mode.

[0010]

1 is a block diagram showing a first divided portion of a three-divided drawing of a semiconductor memory device according to a first embodiment of the present invention,
2 is a block diagram showing a second division, and FIG. 3 is a block diagram showing a third division.

In FIGS. 1, 2 and 3, the wirings A to P of the alphabet are connected with the same symbols.

In this embodiment, redundant cell access circuits (1) to (m), a selector 118, a fuse data selection transistor group 130, a NOR circuit 115, and
I / O buffer 113 and sense amplifier write circuit 112
A test mode setting circuit 105, an address buffer 107, an I / O terminal 114, and an I / O buffer 113.
A sense amplifier write circuit 112, a column selection transistor group 111, a main cell section 110, a fuse data output circuit 131, a column decoder 108, a row decoder 109, a redundant cell section 116, and fuse data. And an output circuit 200.

In this embodiment, the case where there are m sets of redundant cell parts for n row addresses is taken as an example.

During normal operation, the test mode setting circuit 1
05 becomes inactive, and its output signal TES (negative value) becomes H level. At this time, the n-type transistor M
_{1 to} M _n and M _S become conductive, and further the selector 11
Since all the output signals of 8 (see FIG. 8) are at the L level, the fuse data selection transistor groups 130 are all non-conductive.

Therefore, the fuse data signal lines F ₁ ...
F _n and F _s are all set to L level. At this time, the n-type transistor 103 in the fuse data output circuit 200 (FIG. 7) is turned off. From the above, during normal operation, all the circuit groups related to fuse data output are inactive, and normal operation is performed.

On the other hand, when a specific signal is applied to a certain address terminal to set the test mode, the output signal TES (negative value) of the test mode setting circuit 105 becomes L level. Then, the selector circuit 118 becomes active, only the output signal Y _s2 corresponding to the address signal input to the address terminals Ai to Ay becomes H level, and one set of the fuse data selection transistor group 130 is selected. The data of the pair of fuse determination circuits is output to the fuse data signal lines F _{1 to} F _s and F _n . At this time, since the n-type transistors M _{1 to} M _n and M _S in the figure are in a non-conducting state, the data of the fuse determination circuit is the fuse data output circuit 200 through the fuse data signal lines F _{1 to} F _s and F _n. Be transmitted to. Further, the fuse data output circuit 200 described above is connected to the address input terminal 104.

Next, the fuse data output circuit 200 of FIG. 3 will be described with reference to FIG. The fuse data output circuit is composed of an address input signal line and a resistor 120 and an n-type transistor 103 which are inserted in series with a reference potential, and the fuse data signal line F _i is connected to the gate terminal of the n-type transistor 103. .. Now, assuming that the data of the fuse determination circuit (FIG. 1) is at "H" level, the fuse data signal line is also at H level, and the n-type transistor 103 becomes conductive. Therefore, if the H level is applied to the address input terminal 104 at this time, a current flows from the address input terminal 104 to the reference potential.

Next, the data of the fuse determination circuit is "L".
At the time of the level, the above-mentioned fuse data signal line becomes the L level, the n-type transistor 103 becomes non-conductive, and even if the H level is applied to the address input terminal 104, the path through which the current flows does not occur in the circuit.

Therefore, H is applied to the address input terminal 104.
By applying the level and measuring the input terminal leak of the address terminal, the data of the fuse determination circuit can be detected by the presence or absence of the leak current.

In FIG. 8, the selector 118 of FIG.
Test mode setting circuit 1 having address input A _k as input
35, an address buffer 136 having (A _i , ..., A _{i + n-1} ) as inputs, a NAND gate 101, and an inverter 102, and a circuit for outputting selector output signals Y _s1 , ..., Y _sm. Is.

FIG. 4, FIG. 5, and FIG. 6 show the first divided portion, the second divided portion, and the third divided portion of the three-part drawing of the semiconductor memory device according to the second embodiment of the present invention, respectively. It is a block diagram shown.

Of the wirings 1 to 22 in FIGS. 4, 5 and 6, those having the same numerals are connected to form the entire circuit.

The block diagram of the second embodiment of the present invention is a case where m sets of redundant cell parts for n row addresses are provided.

Fuse data selection transistor group 13
The configurations of 0 and the fuse data output circuit 200 are basically the same as those of the first embodiment. The different point is the selection method of the fuse data selection transistor group 130. In this embodiment, the fuse data selection transistor group 130 is selected by the output of the row decoder, and when the test mode signal TES (negative value) becomes L level, the CMOS transmission gate 106 becomes active and the row The output of the decoder is connected to the fuse data selection transistor group 130.

Therefore, by inputting an address signal to the address input terminal 104, one set of arbitrary fuse data selection transistor groups can be selected.

[0026]

As described above, according to the present invention, the characteristics of each fuse judgment circuit are evaluated / selected by setting the test mode in which the data of each redundancy fuse judgment circuit is output to the external terminal. In addition to that, it is possible to easily detect which redundant cell portion is used at which address input.

[Brief description of drawings]

FIG. 1 is a block diagram showing a portion of a first division of a three-division view of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a portion of a second division of FIG.

FIG. 3 is a block diagram showing a portion of a third division of FIG.

FIG. 4 is a block diagram showing a portion of a first division of a three-division view of a semiconductor memory device according to a second embodiment of the present invention.

5 is a block diagram showing a portion of the second division of FIG. 4. FIG.

6 is a block diagram showing a portion of a third division of FIG. 4. FIG.

7 is a block diagram showing a fuse data output circuit of FIG. 1. FIG.

8 is a block diagram showing the selector of FIG. 1. FIG.

FIG. 9 is a block diagram showing a conventional semiconductor memory device.

[Explanation of symbols]

001, 00n, 00s Fuse determination circuit 100 EOR circuit 101 NAND circuit 102 Inverter circuit 103 N-type transistor 104 Address input terminal 105 Test mode setting circuit 106 CMOS translate gate 107 Address buffer 108 Column decoder 109 Row decoder 110 Main cell section 111 Column Selection transistor 112 Sense amplifier / write circuit 113 I / O buffer 114 I / O terminal 115 NOR circuit 116 Redundant cell part (row) 117 Redundant cell part (column) 118 Selector circuit 200 Fuse cell margin circuit 119 Input protection 120 Resistance M ₁ , M _n , M _s n type transistor F _{1 to} F _n , F _s fuse data signal line TES (negative value) test mode setting signal

Claims (2)

[Claims] 1. A semiconductor memory device having a redundant circuit, wherein one or a plurality of sets of redundant memory cell sections are provided in a row direction or a column direction, and one or a plurality of sets corresponding to the redundant memory cell sections. Of the fuse element group for storing information for switching the redundant memory cell section, fuses forming the fuse element group, and individual data stored in each of the fuse element groups are directly output to external terminals. Fuse data output circuit, a fuse data selection transistor group for connecting data of a desired fuse element of the plurality of fuse element groups to the fuse data output circuit, and outputting an internal signal by an input signal from a certain external terminal. A semiconductor memory device comprising a test mode setting circuit for setting a test mode. 2. The semiconductor memory device according to claim 1, wherein the fuse data output circuit is a circuit for outputting data depending on the presence or absence of an input terminal leak of the address input terminal.