JPH0481839B2 - - Google Patents

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to semiconductor memory integrated circuits.

[Conventional technology]

The degree of integration of semiconductor memory integrated circuits (hereinafter referred to as memory ICs) is increasing, and their reliability is also required to be higher and higher.

Generally, when testing a memory IC, it is checked to see if it operates normally between one bit and all other bits, and this is done for all bits, so the number of tests for an N-bit memory is proportional to ^N2 . . Therefore,
As the scale of memory ICs increases, the time required for testing increases rapidly, making the use of expensive measuring instruments less efficient. For this reason, there is a need to shorten the inspection time.

On the other hand, since testing of memory ICs is generally performed from external terminals, there is a possibility that there may be some deterioration such as leakage in the elements that make up the storage unit, especially in memory ICs whose basic storage unit is a flip-flop circuit made of bipolar transistors. is often seen as normal operation. ``Some deterioration'' becomes ``major deterioration'' over time, and there is a risk that it may cause malfunction. Therefore, in order to obtain high reliability, memory ICs with such "slightly degraded" elements must be detected and eliminated.

[Problem that the invention seeks to solve]

However, until now, a memory IC that satisfies the above requirements has not been realized. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a semiconductor memory integrated circuit which can shorten the testing time of the semiconductor memory integrated circuit and provide high reliability.

[Means for solving problems]

The semiconductor memory integrated circuit of the present invention includes first and second bipolar transistors whose bases and collectors are cross-connected to each other and whose emitters are commonly connected, and whose one ends correspond to the collectors of the first and second bipolar transistors, respectively. A plurality of flip-flop circuit type storage units each having first and second load elements connected to each other and having the other ends commonly connected and arranged in a matrix in multiple rows and columns; first and second power supply terminals that respectively receive power supply potentials;
provided corresponding to each row of the plurality of storage units, respectively connected to the other ends of the first and second load elements of each storage unit of the corresponding row, and at a selection level corresponding to the first power supply potential; A plurality of word lines that select each of these storage units are provided corresponding to each row of the plurality of storage units, and are connected to the emitters of the first and second bipolar transistors of each storage unit in the corresponding row. a plurality of word bottom lines, and a plurality of low current sources provided correspondingly between the plurality of word bottom lines and the second power supply terminal and supplying a data holding current to each storage element in a corresponding row. a first ohmic element forming a current path between each of the word lines and the second power supply terminal; and a first ohmic element forming a current path between each of the word lines and the first power supply terminal; and a second ohmic element forming a current path therebetween.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

This embodiment includes two emitter-type first and second bipolar transistors whose bases and collectors are cross-connected to each other and whose first emitters are commonly connected.
and first and second load elements, each of which has one end connected to the collectors of the first and second bipolar transistors, respectively, and whose other ends are commonly connected, and arranged in a matrix of multiple rows and columns. A plurality of flip-flop circuit type storage units C, and first and second power supply terminals that respectively receive a high potential first power supply potential V _CC and a low potential second power supply potential V _EE from the outside. T1, T2
and are provided corresponding to each row of the plurality of storage units C, respectively connected to the other ends of the first and second load elements of each storage unit C in the corresponding row, and correspond to the first power supply potential V _CC . At the selection level, a plurality of word lines W _TO ~ with each of these storage units in the selected state
W _T63 , and the first memory unit C of each memory unit C in the corresponding row is provided corresponding to each row of the plurality of memory units C.
and a plurality of word bottom lines W _{BO ~} connected to the emitters of the second bipolar transistors, respectively.
W _B63 and these multiple word bottom lines W _BO ~
A plurality of constant current sources I _HO to I _H63 are respectively provided between W _B63 and the second power supply terminal T2 and supply data holding current to each memory element C in the corresponding row.
and a plurality of pairs provided correspondingly to each column of the plurality of memory units C and respectively connected to the second emitters of the first and second bipolar transistors of each memory unit C of the corresponding column. first and second digit lines D _LO , D _RO to D _L63 , D _R63 ;
A plurality of constant current sources are connected correspondingly to these digit lines D _LO , D _RO to D _L63 , D _R63 and supply current for writing and reading to the corresponding memory unit C.
I _LO , I _RO to I _L63 , I _R63 and transistors are provided corresponding to the word lines W _TO to W _T63 , respectively, and the corresponding word lines (W _TO to W T63) are provided in accordance with the row address signal.
A semiconductor memory integrated circuit having a plurality of word driver transistors Q _WO to Q W63 and resistors that set the word lines WT to W _T63 to a selected level, respectively, between each word line _{W TO} to W _T63 and the second power supply terminal T2. resistance of a plurality of first ohmic elements to create a current path
Resistances of a plurality of second ohmic elements forming corresponding current paths between R _TO to R _T63 , each word bottom line W _BO to _{W B63} , and the first power supply terminal T1, respectively.
The configuration includes R _BO to R _B63 . Resistance R _TO
~R _T63 , R _BO ~ R _B63 are set to high resistance values that do not interfere with normal operation.

Therefore, if there is a leak in even one of the bipolar transistors constituting the memory unit C, a leak current flows between the first power supply terminal T1 and the second power supply terminal T2, and this can be directly observed. Most leaks occur between the emitter and base or emitter and collector of the transistor. The first power terminal T1 and the second
A peripheral circuit for normal operation is connected between the power supply terminal T2 of the
Diode forward voltage (hereinafter referred to as V _F ) approximately 0.7
(V), almost no current flows. Therefore, if a voltage lower than V _F is applied between the power supply terminals T1 and T2, only the leakage current of the memory unit C can be observed.

At this time, a voltage with a polarity opposite to that during normal operation is applied to the memory unit C. The number of memory units C is large, and in this embodiment, 64×64=4096 units are connected to the power supply terminal T.
1 and T2 are connected in parallel. Therefore 0.7V
Even if the voltage is below, if this voltage is applied to the memory unit C with the same polarity (forward direction) as during normal operation, even if the memory unit C is normal, this memory unit C
A very small forward current flows through the
As the number of memory units increases, the current flowing through all of these memory units C cannot be ignored, and it is difficult to distinguish whether the current flows due to a leak in these memory units C or the current flows despite normality. It becomes difficult to do.

However, in the present invention, as described above, since a voltage of opposite polarity is applied to the memory unit C, the current flowing to the memory unit C is orders of magnitude smaller than when a forward voltage is applied, Even if the number of memory units C increases, the current flowing through all of these memory units C can be ignored, making it possible to easily and reliably detect leaks in the memory units C and improve reliability.

In addition, as shown by the broken lines in FIG. 1, decoupling diodes T _TO to T _T63 whose one ends are connected to the word lines W _TO to _{W T63} in correspondence with each other,
A resistor R _TT whose one end is connected to the other end of these diodes T _TO ~T _T63 and whose other end is connected to the second power supply terminal T2
Accordingly, a current path can be created between the word lines W _TO to W _T63 and the power supply terminal T2, and in this case, the number of resistors can be reduced. However, in this case, it is necessary to observe the leakage of the memory unit C by applying a voltage higher than one stage of V _F (for example, 1.0V), and therefore the peripheral circuit has a current of up to two stages of V _F (approximately 1.4V). It is necessary to prevent it from flowing. The same applies to word bottom lines W _BO to W _B63 .

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

In this embodiment, in order to make the rise of the word lines W _TO -W _T63 steep, the word line discharge circuit D connects the word bottom lines W _BO - corresponding to each word line W _TO -W _T63 .
The present invention is applied to a semiconductor memory integrated circuit inserted between the W B63 and the W _B63 .

Each word line discharge circuit D has resistors R _D10 and R _D20 connected between the corresponding word line (W _TO - W _T63 ) and the second power supply terminal T2.
R _D10 and R _D20 are used as the first ohmic elements.

Figure 3a shows the power supply terminal T in these embodiments.
The voltage V vs. current I characteristics between T1 and T2 are shown. 4.0V
~5.5V is the normal operating area. In addition, Fig. 3b shows
This is an enlarged view of the area near the OV in Figure 3a. The case where there is no leakage current in the memory unit is shown by a solid line, and the case where there is a leakage current is shown by a dotted line. In the case of the dotted line, it is not known whether it is between the emitter and base of the transistor or between the emitter and collector, but in any case, it can be seen that there is a seek in the bipolar transistor of one of the memory units C.

〔Effect of the invention〕

As explained above, the present invention is arranged between each word line and the second power supply terminal, and between each word bottom line and the By having a configuration in which a current path is provided by an ohmic element between the first power supply terminal and the second power supply terminal, it is possible to detect the presence or absence of a leak in the memory unit simply by observing the current between the first and second power supply terminals. Even if the number of memory units increases, the normal current flowing through all of these memory units can be ignored and the presence or absence of leaks in memory units can be reliably detected, reducing inspection time and improving product reliability. There is an effect that can be done.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention,
FIG. 2 is a circuit diagram showing a second embodiment of the present invention, and FIGS. 3a and 3b are power supply voltages between the first and second power supply terminals for explaining the first and second operations and effects, respectively. FIG. 2 is a current characteristic diagram. C...memory unit, D...word line discharge circuit,
D _LO , D _RO ~ _{D L63} . D _R63 ……digit line, I _DO ,
I _HO ~ I _H63 , I _LO , I _RO ~ I _L63 , I _R63 ... Constant current source, Q _WO
~Q _W63 ...Word driver transistor, R _BO ~
R _B63 , R _D10 , R _D20 , R _TO ~ R _T63 , R _TT ...Resistance,
T _TO ~ _{T T63} ...Diode, T1, T2...Power supply terminal, W _BO ~W _B63 ...Word bottom line, W _TO ~
W _T63 ...Word line.

Claims (1)

[Claims] 1 first and second bipolar transistors whose bases and collectors are cross-connected to each other and whose emitters are commonly connected; one end is connected correspondingly to the collectors of these first and second bipolar transistors, and the other end is commonly connected; A plurality of flip-flop circuit type memory units each having first and second load elements and arranged in a matrix of multiple rows and columns, and receiving power from the first and second power supply potentials from the outside, respectively. first and second power supply terminals provided corresponding to each row of the plurality of storage units, respectively connected to the other ends of the first and second load elements of each storage unit of the corresponding row; a plurality of word lines which put these storage units in a selected state when the selection level corresponds to one power supply potential; and a plurality of word bottom lines respectively connected to the emitters of the second bipolar transistors, and a plurality of word bottom lines respectively provided between the plurality of word bottom lines and the second power supply terminal and connected to each storage element in the corresponding row. A semiconductor memory integrated circuit having a plurality of constant current sources supplying a data retention current, a first ohmic element forming a current path between each of the word lines and the second power supply terminal; A semiconductor comprising a second ohmic element forming a current path between the word bottom line and the first power supply terminal. Memory integrated circuit.