EP0032015B1

EP0032015B1 - Field programmable device with test-bits

Info

Publication number: EP0032015B1
Application number: EP80304531A
Authority: EP
Inventors: Toshitaka Fukushima; Kazumi Koyama; Kouji Ueno
Original assignee: Fujitsu Ltd
Current assignee: Fujitsu Ltd
Priority date: 1979-12-18
Filing date: 1980-12-16
Publication date: 1990-02-28
Anticipated expiration: 2000-12-16
Also published as: EP0032015A2; DE3072171D1; IE55516B1; US4429388A; EP0032015A3; CA1177956A; JPS5693189A; IE802647L; JPS6330720B2

Description

The present invention relates generally to the testing of field programmable devices with unprogrammed memory cell parts, for example PROM's (Programmable Read Only Memories), capable of being subjected to functional tests before information is written therein.
In field programmable devices such as PROM's, that is, memory devices capable of having information written therein on the spot, all memory cells within the memory device, before write-in of information, are in a "0" (low) or "1" (high) state, and hence tests cannot be performed to detect whether a memory cell selected is in a normal or abnormal state.
One example of a conventional memory device of the above type comprises X and Yaddress inverters, an X-decoder driver, a Y-decoder, a memory cell part, a multiplexer, and an output circuit. However, when all the memory cells of the memory cell part are in the same state, even in the event of breakdown of one or more peripheral circuits (address inverters, decoder driver, or output circuit, for example) the contents read-out from the memory cells are all the same. Accordingly, it is impossible to determine whether the cells are in normal or abnormal states, and even upon the assumption that there are abnormalities, it is not possible to determine where the abnormalities exist.
Hence, a system was devised in which a row of extra test bits and a test word are provided within the memory cell part. In this system, by storing codes of predetermined code patterns, "1,0,1,0,...", for example, into the test bit row and test word, a test can be performed for detecting the states of the peripheral circuits, by reading out these code patterns. However, since there are a plurality of items or factors which should be tested in relation to a memory device, the above system is not sufficient insofar as it is only capable of performing certain kinds of tests. Therefore, it is not enough simply to provide a test bit row and a test word within the memory cell part, and write in code patterns such as "1,0,1,0,..."; in addition an ingenious code pattern must be devised. Even such an ingenious code pattern is still not sufficient for performing all the necessary tests, since short-circuits in wiring which occur under certain conditions cannot always be detected.
In view of the above problems, the present applicant has proposed a field programmable device, in European Patent Application No. 79302622.0, publication No. 0 011 974, which falls within the scope of Article 54, paragraph 3, EPC, which can be subjected to various tests, and accordingly is capable of being tested before shipment of the memory device. However, it has been revealed that this system is still imperfect in that the system is incapable of performing complete tests in relation to the operational speed of the memory device. The capacitance of a memory cell in the field programmable device before information is written-in may be different from that after information is written-in. Accordingly, word line capacity varies with respect to the write-in ratio (of cells along the word line).
Variations of word line capacity cause change in rise-up characteristics of a word line and in read-out time. Such changes are generally of small amounts, but since field programmable devices, especially high-speed Schottky-type PROM's and the like, have a fast average access time of 20 nsec in the 4-kilobit class, even the slightest change can become a problem.
Word line capacity is affected by manufacturing processes, and thus, computation of word line capacity by calculation is difficult, and preferably actual measurements should be made.
In the case of the above field programmable device proposed by the Applicant, the write-in ratio of the test bit row and test word are both 50%, and hence the device is capable of being subjected to a speed check relating to a 50% write-in ratio, but incapable of being subjected to speed checks in remaining parts or for other write-in ratios. Therefore, when a user performs a 100% write-in (this is done quite often), access time can be much higher than the nominal value indicated by a 50% write-in check.
IBM Technical Disclosure Bulletin, Vol. 21, No. 10, March 1979, discloses a method of testing ROM modules which are written and tested in the factory before being released to users. During the write operation four addresses are dedicated to test operations. First and last addresses in the memory store respectively a pattern of alternate 1 and 0 bits and an inverted version of that pattern, and addresses 1 and 2 store information relating to the contents of the memory.
US-A-3 420 991 discloses an error detecting system for a ROM. The ROM holds information words and test words which are read in sequence. Each information word contains an indication of whether or not a word next to be read in sequence is a test word and an indication of the address of the next word. If the next word is not of the kind indicated by the preceding word an error is detected. The test words may comprise all 1 bits or all 0 bits.
An article by Waser entitled "What is necessary for testing ROM's and PROM's", published in the Digest of Papers of the 1974 Semi-Conductor Test Symposium, Cherry Hill, New Jersey, November 1974, pages 87-113, discloses a PROM with an additional row and column, each containing alternate "1"'s and "0"'s, for testing output selector circuitry.
There is also disclosed a test for PROM's in which a row containing alternate "1"'s (HIGH's) and "0"'s (LOW's), is zapped with the object of providing the row with all "0"'s (LOW's), for the purpose of testing programmability (i.e. that zapping is performed correctly).
Waser also contains disclosure relating to the dynamic testing of ROM's (non-field programmable).
An article by Kondo entitled "Test Pattern for EPROM's", published in IEEE Journal of Solid State Circuits, Vol. SC 14, No. 4, August 1979, pages 730-734, discloses testing of an EPROM by writing in test bit patterns filling the storage space of the EPROM. Use of an all "1" (or all "0") pattern, a matrix analyzed pattern, a checker and inverted checker patterns is mentioned.
IEEE Spectrum, December 1971, pages 28 to 37, in an article by F. van Veen entitled "An Introduction to IC Testing", discusses testing of digital bipolar IC's, linear IC's and semiconductor memories. It distinguishes between dc parametric and pulse parametric (dynamic) testing. In relation to semiconductor memories, it is said that they are functionally and parametrically tested like other IC's.
Siemens Forschungs- und Entwicklungs-berichte, Vol. 4, No. 4,1975, at pages 245 to 249, in an article entitled "A High-Speed 1024-bit ECL Programmable Read-Only Memory" mentions that the (32x32) PROM matrix is provided with a 32-bit test area which is addressed separately and which allows checking of static, dynamic and programming performance.
According to the present invention there is provided a method of testing a field programmable device, having an unprogrammed memory cell part, comprising:-
providing a first test bit row, along a bit line of the memory cell part, and/or a first test word row, along a word line of the memory cell part, with a first code pattern, and
testing DC characteristics of the device by reading out from the first code pattern,
characterised by providing the first code pattern as "0,1,1,0,1,0,0,1,...", obtained by setting an address signal bit A_o of an address signal to "1" and forming a code beginning with A_oA_o, succeeded by an inverted code A_oA_o to form a code A ₀A₀A₀ A ₀, succeeded by an inverted code A_oA_oA_oA_o to form a code A ₀A₀A₀ A ₀A₀ A ₀ A ₀A₀ and so on,
providing a second test bit row, along another bit line of the memory cell part, and/or a second test word row, along another word line of the memory cell part, with a second code pattern, having a write-in ratio significantly different from the write-in ratio of the first code pattern, and
testing access time characteristics of the device, by reading out from the second code pattern.
An embodiment of the present invention can provide field programmable device testing whereby the above-described problems have been overcome.
An embodiment of the present invention can provide for the performance of complete tests on DC and AC characteristics of the field programmable device before the shipment of the device.
Reference is made, by way of example, to the accompanying drawings, in which:-

Fig. 1 is a block diagram illustrating one example of the construction of a previously proposed PROM device;
Fig. 2 is an equivalent circuit diagram of a pn-junction type memory cell part of the device of Fig. 1, showing test bit and test word rows;
Fig. 3A to 3C are, respectively, an equivalent circuit diagram and cross-sections taken along line II and I in the equivalent circuit diagram, of a memory cell part of the device of Fig. 1 in a non-written state;
Fig. 4 is a schematic illustrative diagram of a memory cell part of the device of Fig. 1 for assistance in explanation of the written-in state shown in Fig. 2;
Figs. 5 and 6 are block circuit diagrams illustrating the construction of address inverters, a decoder driver, and a memory cell part of the device of Fig. 1;
Fig. 7 is a schematic diagram showing information to be written into test bits for performing a DC test;
Figs. 8A and 8B are respective block circuit diagrams, and Figs. 9A, and 9B are schematic diagrams for assistance in describing an actual test bit arrangement and its use for performing a DC test;
Fig. 10 is a block circuit diagram of a multiplexer test circuit;
Figs. 11A, 12A and 11B and 12B are, respectively, simplified cross-sectional diagrams of a cell and equivalent circuit diagrams;
Fig. 13 is a schematic diagram for assistance in describing a memory device used in connection with a method embodying the present invention; and
Figs. 14A, 15A, and 16A are respective equivalent circuit diagrams of different types of memory cells, and Figs. 14B, 15B and 16B are corresponding cross-sectional diagrams.

Prior to a description of the present invention, the field programmable device previously proposed by the present Applicant in European Patent Application No. 79302622.0, publication No. 0 Oil 974, will be described, in order to provide for a ready understanding of the details of the present invention.

Fig. 1 shows an example of the construction of a PROM device as previously proposed, which comprises X and Y address inverters 10 and 12, an X-decoder driver 11, a Y-decoder 13, a memory cell part 14, a multiplexer 15, an output circuit 16, and test bit and test word groups 17 and 18.
Fig. 2 shows an equivalent circuit diagram of a memory cell part of Fig. 1. In Fig. 2, two test bit rows TB₁ and TB₂ are provided along with bit lines b₁ to b₄ on one hand, and two test word rows TW, and TW₂ are provided along with word lines 1₁ to 1₄ on the other, within memory cell part 14. A code of a predetermined code pattern, namely "0,1,1,0,1,0,0,1 ...", is written into the first test bit row TB₁ (Fig. 2 does not illustrate this code pattern but rather a code pattern employed in connection with the explanation of Figs. 5 and 6 and Figs. 8B and 9A; the code pattern mentioned above will be understood to relate to Fig. 7). The above code pattern is obtained by setting the address signal bit A_o of the address signal to "1" (high), and forming a code beginning with A_oA_o, succeeded by an inverted code A_oA_o which forms a code A_oA_oA_oA_o, then succeeded by an inverted code A_oA_oA_oA_o which forms a code A_oA_oA_oA_oA_oA_oA_oA_o and so on. A code having a code pattern inverted with respect to that of the first test bit row TB₁ is written into the second test bit row TB₂. Similarly, predetermined code patterns are written into both the test word rows TW₁ and TW₂. Therefore, the states of test bits in test bit rows TB, and TB₂ in corresponding positions are respectively inverted states, and the same is true for the test rows TW, and TW₂.
Transistors TR, are transistors in output stages of decoder driver 11, which are connected to corresponding word lines I₁, 1₂, .... Transistors TR₂ represent memory cells not yet having information written therein. Diodes D₁ represent diodes formed when transistor emitter and base junctions are short circuited, to show memory cells having written-in information "1" (high).
Figs. 3A to 3C are, respectively, an equivalent circuit diagram of the memory cell part not yet having written information therein, and respective cross-sectional diagrams of the memory cell part respectively taken along broken lines I and II of Fig. 3A. In this semiconductor device, an n-type semiconductor layer 20 which is to provide the functions of a collector, is epitaxially grown on a p--type silicon semiconductor base 19. A plurality of p^+-type regions 21 which are to be the bases, are formed on top of the n-type semiconductor layer 20, and n^+-type regions 22 are formed on top of the p^+-type regions 21. The word lines I₁ and I₂ are ormed by the n⁺-type regions 23 embedded below the n-type layer 20, while the bit lines b₁ to b₃ are provided by metal wirings 24 formed on the surface. Layers 25 are insulative membranes, and p⁺-type isolation regions 26 separate the different word lines.
Fig. 4 is a diagram illustrative of the memory cell part of Fig. 2. In Fig. 4, all the memory cells of the memory cell part 14 are in a state in which information is not written in the cells, but information is written selectively in test bits and the test words. The cells in which information is written are shown by the cross-hatched squares, and the remaining (un-written) cells are shown by unmarked squares.

The reason for the necessity to selectively write in the information "0" and "1" will now be described. The selection of the memory cells is performed by the Y-address inverter 12, Y-decoder 13, and multiplexer 15 in relation to the bit line side, and performed by the X-address inverter 10, and X-decoder driver 11 in relation to the word line side. However, to simplify the description, the latter, concerning the word line side, will be described along with Figs. 5 and 6 which outline circuits for the word line side.
As shown in Fig. 5, the address inverter 10 comprises a plurality of rows each having two inverters connected in series, namely, I₁ and I₂, 1₃ and 1₄, and so on. On the other hand, the decoder driver 11 comprises a plurality of rows each having a NAND-gate, namely, NG₁, NG₂, and so on. Respective address signal bits A_o, A₁, A₂ ... of an address signal are applied to respective input terminals of the rows having two series connected inverters. Accordingly, inverted and non-inverted signals, namely, A_o, A_o, A ₁, A₁, ... can be obtained.
In this example, the NAND-gate NG, is supplied with the signals A_o and A ₁, and accordingly generates a "0" (low-level) output when A₀=A₁=0, which means that the word line I₁ has been selected. On the other hand, the NAND-gate.NG₂ is supplied with the signals A_o and A ₁, and generates a low-level output when A_o=₁, and A₁=0, which means that the word line I₂ has been selected. Similarly, the NAND-gates NG₃ and NG₄ respectively generate low-level outputs when A_o=0 and A,=1, and A₀=A₁=1, and respectively select the word lines 1₃ and 1₄. A decoder driver 11 corresponding to the two-bit address signal bits A_o and A₁, is shown in Figure 5 for this example in which the selection from four word lines is performed by using two bits; however, if an address signal has five address signal bits, namely A_o through A4, word line selection from 2⁵, or thirty-two word lines is possible, and in this case, ten inverters, I₁ to I₁₀, and thirty-two NAND-gates are required.
Fig. 6 further illustrates a selection system on the word line side and including a portion of the memory cell part 14. In Fig. 6, memory cells M₁₁, M₁₂, ... M₂₁, M₂₂, ... are respectively provided at each of the intersection points between the word lines I₁, 1₂, ... and bit lines b₁, b₂, .... Furthermore, to simplify the diagram only the address signal bit A_o of the address signal is shown. Generally, the memory cells of a PROM are constructed of fuses or p-n junctions; in this example the latter is indicated, and the write-in of information is effected by destroying the junction between the base and emitter of an npn-transistor. Accordingly, when this junction is destroyed, in a memory cell, a current flows towards the NAND-gate through the bit line and word line crossing at the cell upon generation of a low-level output by the NAND-gate. On the other hand, when this junction is not destroyed, the above current does not flow. Hence, the former situation, in which the junction is destroyed, indicates a write-in of information "1", and the latter situation, in which the junction is not destroyed, indicates a write-in of the information "0".
In PROM devices, the write-in of information is performed by the user, and the write-in of information is not performed before shipment of the devices by the manufacturer. Hence, because the write-in of information has not been performed, the above current which flows toward the NAND-gate through the bit line and word line upon generation of a low-level output by the NAND-gate, as described above, does not flow upon addressing. Accordingly, it is impossible (for the manufacturer, before write in) to detect whether a desired word line has actually been selected or not, or whether a problem such as a break in the wiring exists or not. In addition, the selection of a word line can be successfully performed only when the address inverters, decoder driver, and their wiring are normal, and therefore, even though assumptions can be made in relation to non-selection of a word line due to abnormalities, it is impossible to detect the whereabouts of the cause.
Test bits can be provided in the memory cell part to overcome the above problem. If it is assumed that the memory cells M₁₁, M₁₂, ... of Fig. 6 are for test bits inserted in an additional (test) bit line of the memory cell part, and that a code "1,0,1,0, ..." are written in these test bits, a current flows and the line I₁ is selected when the address signal bit A_o is "0", and, no current flows and the line 1₂ is selected when the address signal bitAo is "1". Accordingly, it can be assumed that the inverter I₁, NAND-gate NG₁ and their wiring are normal when current flows and does not flow as expected. This test cannot provide for detection of abnormalities in the inverter 12 and NAND-gate NG₂; when both the inverter 1₂ and NAND-gate NG₂ are in abnormal states in which the inverter 1₂ constantly produces low-level output and the NAND-gate NG₂ constantly produces high-level output, or when there is a break in the wiring, current would not flow (as expected) in these cases either, and thus it cannot be concluded from the above test alone that the system of the inverter I₂ and NAND-gate NG₂ is in a normal state.
Accordingly, it becomes necessary to consider the possible combinations of output states of each of the elements shown in Fig. 6. There are three possible output states for inverters, mainly; a normal state, an abnormal state in which output is always "1" (referred to as fixed "1" state hereinafter), and an abnormal state in which output is always "0" (referred to as fixed "0" state hereinafter). Therefore, when two inverters are connected in series, there are "3x3=9" possible output states. However, the resultant overall output state is the same when the inverter 1₁ is in a fixed "1" state and the inverter I₂ is in a normal state, as when the inverter 1₁ is in a fixed "1" state and the inverter 1₂ is in a fixed "0" state. Similarly the result is the same when the inverter 1₁ is in a fixed "0" state and the inverter 12 is in a normal state, as when the inverter I₁ is in a fixed "0" state and the inverter 12 is in a fixed "1" state. Hence there are seven possible output state combinations, as shown in Table 1.
Of the cases (1) to (7) in Table 1, the only normal state obtained is in case (1), and all the other cases (2) through (7) are abnormal states (cases (2) and (3) are partially normal and partially abnormal, and thus abnormal considered as a whole). The object is to detect the above abnormal cases by use of the test bits, but differences occur according to the contents stored in the test bits, as shown in Table 2.
As seen in case (I) of Table 2, when information "1" and "0" is written in the memory cells M₁₁ and M₂₁ of test bit line b₁, respectively, upon normal selection of case (1), the memory cell M₁₁ is conductive when the input address signal A_o is "0" and the line 1₁ is selected, and the memory cell M₂₁ is not conductive when the input address signal A_o is "1" and the line 1₂ is selected. Accordingly, the read-out values of the test bit memory cells M₁₁ and M₂, are "1" and "0", respectively, the same as those values written therein. Hence, this case can be judged as being normal. However, upon mixed selection (inverter 1₁ is in a normal state, and inverter 1₂ is in a fixed "1" state) as in case (2), in the case where information "1" and "0" is written in the memory cells M₁₁ and M₂, respectively, when the input address signal A_o is "0" and the line 1₁ is selected, the memory cell M₁₁ conducts, and when the input address signal A_o is "1" and the line 1₂ is selected, the memory cell M₂, does not conduct. Therefore, as a result, the read-out contents become the same as those corresponding to written-in contents. But in this case, the case where be judged as being abnormal, since the inverter 1₂ is in an abnormal state, namely, in a fixed "1" state. Accordingly, the abnormality in the case (2) cannot be detected by this arrangement of the test bit code. The same is true for the case (3), because here too, the abnormality in the inverter I₂ cannot be detected by the above coding of the case (I).
On the other hand, when information "0" and "1" is written in the memory cells M₁₁ and M₂₁ of the test bit line b₁, respectively, the contents of the written-in and read-out information of the above respective memory cells are the same upon normal selection of the case (1). In the mixed selection state of the case (2), there is no current passing through the memory cell M₁₁ when the input address signal A_o is "0" and the line 1₁ is selected since the memory cell M₁₁ (transistor) is not conductive, but because the inverter 1₂ is in a fixed "1" state and the line I₂ is selected as well, there is a current flowing through the memory cell M₂₁, and the resultant read-out content of the memory cell M₁₁ is "1". When the input address signal A_o is "1" and the line I₂ is selected, there is a current flowing through the memory cell M₂₁, and thus the read-out signal of the memory cell M₂, becomes "1". Accordingly, the read-out contents "1, 1" differ from the written-in contents "0, 1", and judgement is made that an abnormality exists in this case. This judgement is, of course, correct.
Similarly, correct judgements can be made for all the cases (1) through (7), in case (II) of Table 2. It is thus understood that the write-in contents for the memory cells M₁₁ and M₂₁ should be M₁₁=0 and M₂₁=1, and that the other combination (case I) is unacceptable. However, the above description is for the case when the address signal has only one bit, namely A_o, and when there are a plurality of bits, for example, in the case of five bits, the acceptable coding is as shown in Fig. 7.
Fig. 7 shows that test bits b₁₁ and b₂₁, corresponding to the above memory cells M₁₁ and M₂₁, are respectively "0" and "1" as described above, and that succeeding test bits b₃₁ and b₄₁ should contain the inverse code of that formed by the test bits b₁₁ and b₂₁, namely "1" and "0", respectively. The next succeeding test bits b₅₁, b₆₁, b₇₁ and b₈₁ should contain the inverse code of that formed by the test bits b₁₁, b₂₁, b₃₁, and b₄₁, namely "1,0,0,1". Similarly, the rest of the code can be obtained as shown in Fig. 7, and the same code pattern should be inserted into the test word TW₁ to perform the above described valid judgements (see Fig. 2).
By using the above described information (code) to be written-in into the test bits, the address inverters as well as the decoder driver can be checked for normal or abnormal states. However, only the current absorbing capacity of half the decoder drivers can be checked, since the other half of the decoders are connected to bits containing the information "0" (this is because the code pattern contains the same number of "0"s and "1"s).
The write-in of information is performed by selecting a word line, and applying a large voltage on the bit line to pass a large current of about 200 mA through the bit line, memory cell, word line, and NAND-gate. However, this large current cannot be passed through the NAND-gates connected to the test bits in an OFF state, and the current absorbing capacity of the NAND-gates cannot be checked. The object of the above stated invention in European Patent Application No. 79302622.0, publication No. 0 011 974, was to compensate for the above described problems. As seen in Figs. 2 to 4, an additional bit line and an additional word line were provided and a test bit row TB₂ and test word row TW₂ were connected to these additional lines. Furthermore, the information written-in into these test bit cells were made to be the inverse of those written-in into the first test bit line and first test word line, namely, "1,0,0,1,0,....
When the code "0,1,1,0,1,0,0,1,1,0,..." shown in Fig. 7 is written-in into a test bit line, the second and third test bits, the sixth and seventh test bits,..., comprise same contents. Accordingly, the result of tests as outlined above in relation to Tables 1 and 2 would be the same for each of those pairs of test bits if a short-circuit in the wiring thereof existed, and the short-circuit in the wiring cannot be detected. Thus, in the above proposed device, the contents written-in into the test bit pairs mentioned are the same, but the actual physical geographical test bit arrangement in the memory cell part is changed so that the stored contents of those test bits are the inverse of those of their neighbouring test bits (in the same test bit line), namely, "0,1,0,1,0,1 ..." or "1,0,1,0,1 ...".
Figs. 8A and 8B illustrate the above described test bit arrangement for a two-bit address signal and four word lines. Fig. 8A shows the case where the code "0,1,1,0" is stored in the test bits (i.e. in actual physical consecutive test bits in a test bit line), and Fig. 8B shows a case where the code "0,1,0,1" is stored in the test bits (i.e. in actual physically consecutive test bits in a test bit line). In either of the above cases, the test bits b_", b₂₁, b₃₁, and b₄, selected by the two-bit address signals "00", "01", "10", and "11" are written-in with the information "0,1,1,0", respectively, but the actual physical geographical arrangement of bits in the memory cell part in the case shown by Fig. 8B is "0,1,0,1". The circuit of Fig. 8B processes address signal bits differently. Accordingly, by the arrangement shown in Fig. 8B, a different result is obtained when a short-circuit exists between neighbouring wires of a word line, as opposed to that of a normal state, and the abnormality can be detected immediately.
Figs. 9A and 9B respectively show test bit arrangements for six-bit address signal and sixty-four memory cells. Fig. 9A shows a test bit arrangement including a countermeasure against short-circuits in the wiring, while the arrangement of Fig. 9B does not. The cross-hatched squares (bits) indicate bits containing the information "1", and the unmarked squares (bits) indicate bits containing the information "0". In the arrangement of Fig. 9A, besides arranging the bits so that the neighbouring bits (in one line and in different lines) contain the reverse contents from one to another, that is, the neighbouring bits of a bit containing "0" contain "1" and vice versa, the position of the test bits are arranged so that their addresses, (of actual consecutive test bit locations) are arranged in an order S32, S0, S1, S33, S35,....
A detection circuit for detecting the defect in the multiplexer is shown in Fig. 10. When memory capacity becomes large, the memory cell part 14 of Fig. 1 is divided into a plurality of memory cell groups, and a system is used in which each of the memory cell groups are selectively connected to the output circuit 16 by use of a multiplexer 15 connected between the output circuit 16 and the memory cell groups. However, this multiplexer 15 also needs to be tested as to whether it is normally operational or not. To perform the above test, a test word can be provided which generates an output representing the output of each of the memory cell groups, and an output can be obtained by switching over these outputs by a switching signal.
In Fig. 10, G, to G₈ are AND-gates, and Gg is an OR-gate constructing the multiplexer 15. Output circuits of each of the memory cell groups are designated by g, through go, and selection signals bits for selecting the AND-gates G, to G₈ are designated by A₆ through As. In this example, there are eight memory cell groups, that is, there are eight AND-gates, and hence the output of one of the AND-gates is selected to be high ("1") by the selection signal formed by the three selection signal bits As through A₈. Abnormalities can be checked by setting a test word to contain "0,1,1,0,1,0,0,1" and considering a possibility of breaks in the wiring, it is desirable to set the physical arrangement of the test word row to contain "0,1,0,1,...".
Normal or abnormal state judgement in the above cases (1) through (7), tests on the current absorbing capacity of the decoder driver, and checks for short-circuits in the wiring, can thus be performed in the improved field programmable device described above, and practically complete tests can be performed on the field programmable device in the manufacturing stage and before its shipment. Moreover, the test word and the test bit are used in a similar manner, thus enabling DC tests on the output voltage and output short circuit current, as well as AC tests, and hence judgements can be made on write-in current absorption, multiplexer system, comparing voltages.
However, these AC and DC tests on the peripheral circuits of a memory device, are sufficient only for PROMs and the like having relatively slow operational speeds. In high-speed devices such as high-speed Schottky-type PROM's, the average access time is fast, in the 20 ns range for the 4-kilobit class of device. Accordingly, the AC characteristic of the peripheral circuits within the memory cannot be fully guaranteed merely by providing test words or test bits having a 50% write-in ratio (meaning, there are same number of "0"'s and "1"'s written into the test word or test bit).
A memory cell having no information written-in can be shown as in Figs. 11A and 11 B, where Fig. 11 B is an equivalent circuit diagram of the memory cell shown in Fig. 11A. On the other hand, a memory cell having information written-in, can be shown as in Figs. 12A and 12B, where Fig. 12B is an equivalent circuit diagram of the memory cell shown in Fig. 12B. As opposed to the memory cell of Fig. 11A in which the junction capacitance C₁ between the emitter E and base B in the reverse-biased state, and the junction capacitance C₂ between the base B and collector C in the forward-biased state, are connected in series, the memory cell having information written-in only has the capacitance C₂ since a conductive channel CH is formed between the emitter E and base B by destroying the emitter-base junction as shown in Fig. 12A. This junction capacitance C₂ between the base B and collector C is forward-biased, and therefore, usually does not introduce a problem. However, this capacitance does introduce a problem in this case for the following reasons.
When the emitter-base junction is short-circuited, a pnp-type transistor is formed by the base B, collector C (the collector region n and the buried layer n⁺b), and the base plate 19, and a current flows through this pnp-type transistor upon selection, as can be clearly seen from the diagram of Fig. 12A. Hence, when the word line is non-selected, the base current of pnp-type transistor is cut-off, and the pnp-type transistor accordingly is turned OFF. However, a charge due to the current which has been flowing remains, and thus, until this charge disappears, the word line voltage does not rise to the high ("1") level of non-selection.
The above capacitance C₂ is much larger than the capacitance of a non-written cell (approximately equal to the capacitance C₁). Accordingly, the capacity of a word line or bit line may become larger than that provided for by test bit lines TB₁ and TB₂ or test word line TW₁ and TW₂ having a 50% write-in ratio. That is, in the case of a pn-junction type PROM, the word line or bit line having a 100% write-in ratio has the heaviest load, and when the AC characteristics of the memory device including its internal peripheral circuits is not tested (checked) under such conditions before its shipment, the access time of the memory device under maximum load cannot be guaranteed.
A type of sectional diagram of a memory cell part of a field programmable device used in connection with an embodiment of the present invention is shown in Fig. 13. The point of difference between the present embodiment shown in Fig. 13 from the device shown in Fig. 4 lies on the fact that, in Fig. 13, a third test word TW₃ having a write-in ratio of 100% has been added (the cross-hatched squares represent the written-in bits). The test word TW₃ is, for example, formed by short-circuiting the emitter-base junctions of all the memory cells in the word line 1₄ shown in Fig. 2, to convert them into the equivalent of diodes D₁.
Fig. 14A shows a more detailed equivalent circuit diagram of a memory cell as illustrated above, and Fig. 14B shows a cross-sectional diagram of the memory cell. In Fig. 14B, those parts that are the same as those corresponding parts in Figs. 3A and 3B are designated by the like reference numbers. A pnp-type transistor (transistor TR₃ of Fig. 14A) employing the p--type semiconductor substrate 19, is parasitically formed. Accordingly, a junction capacitance C_o (capacitance C_o is larger than the above described capacitance C₁) is formed between the n-type semiconductor layer 20 and the p--type semiconductor substrate 19 in the reverse-biased state, and this capacitance C_o acts as a load by the formation of a conducting channel CH. Hence, the capacitance of the written-in cells becomes larger than thaf of the non-written cells, and the load as seen from the peripheral circuit side differs according to the write-in ratio. Therefore, in accordance with the present embodiment, a test word line TW₃ having a maximum load is provided, to guarantee the AC characteristics or the access time of the field programmable device being shipped, by obtaining the slowest access time by the test performed under selection of this additional test word TW₃. The test words TW₁ and TW₂ are also provided, of course, and thus the DC characteristic on the word line side is also fully guaranteed. The same is true on the bit line side, but to describe this would simply repeat the description above, and will be omitted. These test cells for measuring the access time of the memory device can be provided on the test bit side, or on the test word side, or on both the test word and test bit sides.
Moreover, as long as the load is heavy enough to practically guarantee the AC characteristic of the device, the code pattern written-in onto the test word TW₃ does not necessarily have to be of a 100% write-in ratio, that is, some bits may be non-written cells. Furthermore, it is also possible to assume (or estimate or evaluate) a slowest access time, by providing two rows of test bits or test words having different write-in ratios between 0% and 100%, and measuring their access time. In this case, one of the test bit or test word rows for performing the DC tests can be used as one of the above test bit and test word rows. Even more, according to the type of memory device being used, it is necessary in some cases to set the code pattern of the test word TW₃ to a pattern in which the bits (cells) are all zeros (or nearly all zeros).
Figs. 15A and 15B show a ROM (or EAROM) having memory cells made out of amorphous semiconductor (chalcogenied glass). In this case, the cells have "1" states as in the pn-junction type, but in the case of a fuse type device, the memories (for shipping) must all contain the reverse of the above namely "0"'s as shown in Figs. 16A and 16B. In Figs. 15B and 16B, those parts that are the same as those corresponding parts in Figs. 3A and 3B are designated by the like reference numerals, and their description will be omitted.
In the devices of Figs. 15A and 15B, a chalcogenied glass layer 27 and a metal electrode 28 are inserted between the metal electrode (bit line) 24 and the anode 21 of the diode D₁ to provide a bias voltage at the electrodes 24 and 28. By forming a conductive channel CH between these electrodes 24 and 28 by applying a bias current and transforming the single crystal into a polycrystalline structure by Joule heating, write-in is performed. Accordingly, these type of memory cells are of the same type as the pn-junction type cells. However, the cell shown in Figs. 16A and 16B performs the write-in by passing an overcurrent to melt and break a fuse 29. This is of an opposite type to that of the above two examples, and comprises a maximum capacitance in the word line (or bit line) having 100% non-written cells and the capacitance is minimum for the 100% written-in word line (or bit line).

Claims

1. A method of testing a field programmable device, having an unprogrammed memory cell part (14), and a first test bit row (TB,), along a bit line of the memory cell part (14), and/or a first test word row (TW,), along a word line of the memory cell part (14), with a first code pattern, said method comprising testing DC characteristics of the device by reading out from the first code pattern, and being characterised by

providing the first code pattern as "0,1,1,0,1,0,0,1, ...", obtained by setting an address signal bit A_o of an address signal to "1" and forming a code beginning with A ₀A₀, succeeded by an inverted code A₀ A ₀ to form a code A ₀A₀A₀ A ₀, succeeded by an inverted code A₀ A ₀ A ₀A₀ to form a code A_oA_oA_oA_oA_oA_oA_oA_o and so on,

providing a second test bit row, along another bit line of the memory cell part (14), and/or a second test word row (TW₃), along another word line of the memory cell part (14), with a second code pattern, having a write-in ratio significantly different from the write-in ratio of the first code pattern, and

testing access time characteristics of the device, by reading out from the second code pattern.

2. A method as claimed in claim 1, in which a third test bit row (TB₂), along a further bit line of the memory cell part, and/or a third test word row (TW₂), along a further word line of the memory cell part (14), is provided with a code pattern inverted with respect to the first code pattern.

3. A method as claimed in claim 1 or 2, in which the first code pattern is arranged so that actual physically geographically neighbouring bits in the row in which that pattern is provided contain inverse information from one bit to the other, e.g. "1"'s and "0"'s.

4. A method as claimed in claim 1, 2 or 3, in which the second code pattern has a 100% write-in ratio, containing all "1"'s.

5. A method as claimed in claim 1, 2 or 3 in which the second code pattern has a 0% write-in ratio, containing all "0"'s.