KR100451489B1 - Test pattern of semiconductor device and forming method thereof to precisely measure junction leakage current of storage node electrode and substrate - Google Patents

Abstract

PURPOSE: A test pattern of semiconductor device is provided to precisely measure a junction leakage current of a storage node electrode and a substrate by using a predetermined storage under plate. CONSTITUTION: A semiconductor substrate(1) is separated into respective dies(10) by scribe lines(11). A transistor including gate, source and drain regions is formed in the separated die. An insulation layer having a capacitor formation contact hole exposing the source region is formed over the transistor. A storage under plate(20) is formed on the front surface of each die, exposing the scribe line of the substrate. The storage under plate comes in contact with the source region of the substrate through the contact hole, made of a polysilicon material for measuring a leakage current with the substrate.

Description

Test pattern of semiconductor device and formation method thereof

The present invention relates to a test pattern of a semiconductor device, and more particularly, to a test pattern of a semiconductor device capable of efficiently measuring a leakage current of a DRAM (DRAM) device.

In general, in the manufacturing process of a semiconductor device, a test pattern is formed on a scribe line between a die and a die for a predetermined test on the device, and wafers are cut by die through the scribe line after the test is completed. .

However, in the case of DRAM devices, the refresh characteristic is affected by the leakage current caused by the PN junction generated in the storage node. Since the amount of leakage current per unit cell is very small, the measurement of the conventional test pattern is not possible. it's difficult. Therefore, it is difficult to monitor the refresh characteristics with process-related electrical characteristics, and it is difficult to improve the refresh characteristics through process improvement.

Accordingly, the present invention has been made in view of the above-described problems, and in the manufacture of DRAM devices, a storage underplate is formed on each die of a substrate to test the leakage pattern between the storage underplate and the substrate. And a method for forming the same.

1 is a plan view showing a test pattern of a semiconductor device according to an embodiment of the present invention.

2 is a plan view showing a test pattern of a semiconductor device according to another embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

1: semiconductor substrate 11: scribe line

10: die 20, 100: storage underplate

A, B: cell area

The test pattern of the semiconductor device according to the first aspect of the present invention for achieving the above object is provided with a predetermined transistor and an insulating film provided with a contact hole for forming a capacitor thereon and separated into each die by a scribe line Semiconductor substrates; In addition to the contact with the substrate through the contact hole is formed on the front surface of each die, characterized in that it comprises a storage under plate for measuring the leakage current with the substrate.

In addition, the test pattern of the semiconductor device according to the second aspect of the present invention for achieving the above object is provided with a predetermined transistor and an insulating film having a contact hole for forming a capacitor thereon, each die by a scribe line A semiconductor substrate separated by; And a storage under plate formed on the die such that the one side cell region and the other side cell region in the die are spaced apart from each other in contact with the substrate through the contact hole to measure leakage current between the die and the substrate. It features.

In addition, a method of forming a test pattern of a semiconductor device according to the first aspect of the present invention for achieving the above object includes a gate, a source, a drain region, and a contact hole exposing a predetermined portion of the source thereon. And providing a semiconductor substrate separated into each die by a scribe line; Forming a storage electrode material of a capacitor on the front surface of the substrate; And patterning the storage electrode material to form a storage underplate only on the die.

The forming of the storage under plate may include forming a predetermined mask pattern on the storage electrode material; Etching the storage electrode material to expose the scribe lines using the mask pattern; And removing the mask pattern.

In addition, a method of forming a test pattern of a semiconductor device according to a second aspect of the present invention for achieving the above object includes a gate, a source, a drain region, and a contact hole exposing a predetermined portion of the source thereon. And providing a semiconductor substrate separated into each die by a scribe line; Forming a storage electrode material of a capacitor on the front surface of the substrate; And patterning the storage electrode material to form a storage underplate on the die such that one cell region and the other cell region in the die are separated by a predetermined portion.

The forming of the storage under plate may include forming a predetermined mask pattern on the storage electrode material; Etching the storage electrode material to expose the scribe line and the predetermined portion in the die using the mask pattern; And removing the mask pattern.

According to the present invention having the above configuration, the junction leakage current between the storage node electrode of the capacitor and the substrate related to the re-flash characteristics of the DRAM can be accurately measured using a predetermined storage under plate.

In addition, the junction leakage current distribution between the storage node electrode and the substrate in the die can be confirmed.

EXAMPLE

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.

FIG. 1 is a plan view illustrating a test pattern of a semiconductor device according to an exemplary embodiment of the present invention. As shown in FIG. 1, a predetermined transistor (not shown) and a contact hole for a storage node electrode of a capacitor are disposed on an upper portion thereof. For measuring the leakage current between the semiconductor substrate 1 having an insulating film (not shown), each die 10 formed by separating the substrate 1 from the scribe line 11, and the substrate 1. The contact hole is formed of a storage under plate 20 formed on the front surface of each die 10 in addition to contact with the substrate 1.

Looking at the method of forming a test pattern of a semiconductor device having the above-described configuration, although not shown, an insulating film having a gate, a source, a drain region, and a contact hole exposing a predetermined portion of the source is formed thereon. A polysilicon film, which is a storage electrode material of a capacitor, is deposited on the entire surface of the semiconductor substrate 1 so as to contact the source through the contact hole. Subsequently, a predetermined mask pattern is formed by photolithography on the polysilicon film, and the polysilicon film is etched to expose the scribe line 11 using the mask pattern. Then, by removing the mask pattern in a known manner, the storage under plate 20 is formed on the front of the die 10.

That is, by measuring the leakage current between the substrates 1 for each die 10 through the storage under plate 20 formed on the front surface of the die 10, the leakage current of the storage node electrode can be measured. For example, in the case of 16M DRAM, the total measured current generated in 16 million cells is measured in amperes, assuming a leakage current per cell of tens of fA. In addition, the measurement system at this time can be measured using a normal system.

2 is a plan view illustrating a test pattern of a semiconductor device according to another exemplary embodiment of the present invention. Unlike the exemplary embodiment of the present invention, FIG. 2 illustrates a comparison of the leakage current distribution in the die 10. The storage underplate 100 is formed on the die 10 by dividing the central cell areas A and the outer cell areas B from each other.

That is, a semiconductor substrate 1 having a predetermined transistor (not shown) and an insulating film (not shown) having a contact hole for a storage node electrode of a capacitor thereon, and the substrate 1 are a scribe line 11. Each die 10 formed separately in the contact with the substrate 1 through the contact hole for measuring the leakage current with the substrate 1 and one cell area A of the die 10 and the other It is composed of a storage under plate 100 formed on the die 10 so that the side cell region B is separated.

Looking at the method of forming a test pattern of a semiconductor device according to another embodiment of the present invention having the above configuration, although not shown, a contact having a gate, a source, and a drain region and exposing a predetermined portion of the source thereon. A polysilicon film, which is a storage electrode material of a capacitor, is deposited on the entire surface of the semiconductor substrate 1 on which an insulating film having holes is formed so as to contact the source through the contact hole. Subsequently, a predetermined mask pattern is formed by photolithography on the polysilicon film, and the polysilicon film is etched using the mask pattern to expose a predetermined portion of the scribe line 11 and the die 10. Then, by removing the mask pattern in a known manner, the storage underplate 100 is formed to be spaced apart from each other on one cell area A and the other cell area B of the die 10.

Therefore, by measuring the leakage current between the substrate 1 through the storage under plate 100 into one cell region and the other cell region of the die, the leakage current distribution of the storage node electrode in the die can be confirmed.

According to the above embodiment, the junction leakage current between the storage node electrode of the capacitor and the substrate related to the re-flash characteristics of the DRAM can be accurately measured using a predetermined storage under plate. In addition, the junction leakage current distribution between the storage node electrode and the substrate in the die can be confirmed.

In addition, monitoring is possible in the input line process, and thus it is applicable to process monitoring and improvement of the refresh characteristics.

In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.

Claims (7)

A semiconductor substrate having a transistor including a gate, a source and a drain region, and an insulating layer having a capacitor forming contact hole exposing the source region over the transistor; Exposed scribe line of the substrate, is formed on the front surface on each die, and contact with the source region of the substrate through the contact hole includes a polysilicon storage under plate for measuring leakage current with the substrate A test pattern of a semiconductor device, characterized in that. The test pattern of claim 1, wherein the leakage current per cell in the die is measured by the leakage current measured by the storage under plate. A semiconductor substrate having a transistor including a gate, a source and a drain region, and an insulating layer having a capacitor forming contact hole exposing the source region over the transistor; The scribe line and a predetermined portion of the die are exposed, and the one cell region and the other cell region of the die are formed to be spaced apart from each other by the exposed predetermined portion of the die, and the source region and the contact of the substrate through the contact hole. And a storage under plate made of polysilicon for measuring leakage current with a substrate and comparing leakage currents of the one side and the other cell region. The test pattern of claim 3, wherein the leakage current per cell of the separated cell area is measured and compared through leakage current measured by the storage under plate. A semiconductor substrate is provided, which is separated into respective dies by scribe brine, wherein the separated die includes a transistor including gate, source and drain regions, and an insulating layer having a capacitor forming contact hole exposing the source region over the transistor. Doing; Forming a polysilicon film for a storage electrode of a capacitor on the entire surface of the substrate; And And etching the polysilicon layer to expose a scribe line of the substrate, and covering a front surface of each die, and a storage under plate contacting the source region of the substrate through the contact hole. Formation method. A semiconductor substrate is provided, which is separated into respective dies by scribe brine, wherein the separated die includes a transistor including gate, source and drain regions, and an insulating layer having a capacitor forming contact hole exposing the source region over the transistor. Doing; Forming a polysilicon film for a storage electrode of a capacitor on the entire surface of the substrate; and The polysilicon layer is etched to expose the scribe line and a predetermined portion of the die, and the one side cell region and the other cell region of the die are spaced apart from each other by the exposed predetermined portion of the die, thereby allowing the substrate to pass through the contact hole. And a storage under plate in contact with the source region of the semiconductor device. The semiconductor device test pattern of claim 6, wherein the storage underplate is used to measure a leakage current with the substrate in the die and to compare leakage currents of the one and the other cell regions. Formation method.