KR100214279B1 - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor device Download PDFInfo
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- KR100214279B1 KR100214279B1 KR1019960050632A KR19960050632A KR100214279B1 KR 100214279 B1 KR100214279 B1 KR 100214279B1 KR 1019960050632 A KR1019960050632 A KR 1019960050632A KR 19960050632 A KR19960050632 A KR 19960050632A KR 100214279 B1 KR100214279 B1 KR 100214279B1
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- contact
- contact hole
- forming
- bit line
- insulating film
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
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- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체소자의 제조방법에 관한 것으로, 트랜지스터가 형성된 반도체기판 상부에 얇은 두께의 절연막을 수정두께 형성하고 반도체기판을 노출시키는 콘택패드용 콘택홀을 경사지게 형성한 다음, 상기 콘택패드용 콘택홀을 통하여 소오스/드레인 접합영역에 접속하는 콘택패드를 형성하고 그 상부를 다른 절연막으로 평탄화시킨 다음, 비트라인과 저장전극을 형성함으로써 상기 반도체기판의 손상없이 셀의 크기 축소를 용이하며 공정마진을 증가시켜 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집집적화를 가능하게 하는 기술이다.The present invention relates to a method of manufacturing a semiconductor device, in which a contact hole for a contact pad, which exposes a semiconductor substrate, is formed obliquely on an upper surface of a semiconductor substrate on which a transistor is formed, And the upper surface of the contact pad is planarized by another insulating film. Then, the bit line and the storage electrode are formed, thereby facilitating the size reduction of the cell without damaging the semiconductor substrate and increasing the process margin Thereby improving the characteristics and reliability of the semiconductor device and enabling the integration of the semiconductor device with high precision.
Description
본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 셀 크기가 작은 고집적화된 반도체소자의 비트라인 및 저장전극 콘택공정을 용이하게 실시할 수 있는 반도체소자의 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device capable of easily conducting a bit line and a storage electrode contact process of a highly integrated semiconductor device having a small cell size.
일반적으로, 메모리 소자에서 중요한 특성인 리프레쉬 타임(refresh time)은 주로 저장전극 노드와 트랜지스터의 드레인을 연결하는 저장전극 콘택공정시 상기 드레인이 손상되어 발생되는 누설전류에 의하여 결정된다.Generally, a refresh time, which is an important characteristic in a memory device, is mainly determined by a leakage current generated by damaging the drain during a storage electrode contact process connecting a storage electrode node and a drain of a transistor.
종래기술을 설명하면 다음과 같다.The conventional technology will be described as follows.
먼저, 반도체기판 상부에 트랜지스터를 형성하고, 그 상부를 평탄화시킨 다음, 비트라인 콘택공정으로 비트라인을 형성하고 저장전극 형성공정으로 저장전극을 형성한 다음, 후속공정을 실시하여 반도체소자를 제조하였다.First, a transistor is formed on a semiconductor substrate, a top surface thereof is planarized, a bit line is formed in a bit line contact process, a storage electrode is formed in a storage electrode formation process, and a subsequent process is performed to fabricate a semiconductor device .
도 1은 종래기술에 따른 셀의 레이아웃도를 도시한 것으로, 게이트전극(53)과 비트라인 콘택홀(55) 또는 게이트전극(53)과 저장전극 콘택홀(57)이 일정간격 유지한 채 형성하여야 함을 도시한다.FIG. 1 shows a layout of a cell according to the related art. In FIG. 1, a gate electrode 53 and a bit line contact hole 55 or a gate electrode 53 and a storage electrode contact hole 57 are formed .
이상에서 설명한 바와 같이 종래기술에 따른 반도체소자의 제조방법은, 소자분리절연막, 게이트전극, 비트라인과 같은 하부구조물을 형성하고 그 상부를 평탄화 시키는 하부절연층을 형성하고 저장전극 마스크를 이용한 식각공정으로 상기 반도체기판의 드레인 접합영역을 노출시키는 콘택홀을 형성함으로써 상기 반도체기판을 손상시켜 상기 드레인 접합영역에서의 누설전류를 증가시켜 반도체소자의 리프레쉬 특성을 저하시킴으로써 반도체소자의 특성 및 신뢰도를 저하시켜 반도체소자의 고집적화를 어렵게 하는 문제점이 있다.As described above, in the conventional method of fabricating a semiconductor device, a lower insulating layer for forming a lower structure such as a device isolation insulating film, a gate electrode, and a bit line is formed, a lower insulating layer for planarizing the upper portion is formed, The semiconductor substrate is damaged by forming contact holes exposing the drain junction regions of the semiconductor substrate to increase the leakage current in the drain junction regions to lower the refresh characteristics of the semiconductor elements, There is a problem that it becomes difficult to highly integrate the semiconductor device.
본 발명은 상기한 종래기술의 문제점은 해결하기 위하여, 비트라인 콘택홀과 저장전극 콘택홀이 형성될 부분을 식각하여 노출된 반도체기판의 소오스/드레인 접합영역 콘택패드를 형성하고 후속콘택공정으로 상기 콘택패드에 접합되는 비트라인과 저장전극을 형성함으로써 셀 크기를 작게 하는 동시에 콘택공정을 용이하게 실시할 수 있어 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 반도체소자의 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION In order to solve the problems of the prior art described above, it is an object of the present invention to provide a method of manufacturing a semiconductor device, which comprises etching a portion where a bit line contact hole and a storage electrode contact hole are to be formed to form a contact pad of a source / Since the bit line and the storage electrode are formed on the contact pad, the cell size can be reduced and the contact process can be easily performed, thereby improving the characteristics and reliability of the semiconductor device and enabling high integration of the semiconductor device. And a manufacturing method thereof.
제1도는 종래기술에 따른 반도체소자의 제조방법을 도시한 단면도.FIG. 1 is a sectional view showing a method of manufacturing a semiconductor device according to a conventional technique; FIG.
제2a도는 본 발명에 따른 반도체소자의 제조방법을 도시한 레이아웃도.Fig. 2a is a layout diagram showing a method of manufacturing a semiconductor device according to the present invention;
제2b도 내지 제2f도는 본 발명의 실시예에 따른 반도체소자의 제조방법을 도시한 단면도.2b to 2f are sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명DESCRIPTION OF THE REFERENCE NUMERALS
11, 51 : 반도체기판 13 : 소자분리절연막11, 51: semiconductor substrate 13: element isolation insulating film
15, 53 : 게이트전극 17 : 절연막 스페이서15, 53: gate electrode 17: insulating film spacer
19 : 소오스/드레인 접합영역 21 : 제1절연막19: source / drain junction region 21: first insulating film
23 : 콘택패드용 제1콘택홀 25 : 콘택패드용 제2콘택홀23: first contact hole for a contact pad 25: second contact hole for a contact pad
27 : 콘택패드 29 : 제2절연막27: contact pad 29: second insulating film
31, 55 : 비트라인 콘택홀 33 : 비트라인31, 55: bit line contact hole 33: bit line
35 : 제3절연막 37 : 감광막패턴35: third insulating film 37: photosensitive film pattern
39, 57 : 저장전극 콘택홀 41 : 저장전극39, 57: storage electrode contact hole 41: storage electrode
35 : 제3절연막 37 : 감광막패턴35: third insulating film 37: photosensitive film pattern
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 제조방법은, 반도체기판 상부에 게이트전극을 형성하는 공정과, 상기 게이트전극 상부를 평탄화시키는 제1절연막을 얇게 형성하는 공정과, 상기 게이터전극 간의 반도체기판에 형성된 소오스/드레인 접합영역을 노출시키는 콘택패드용 제1콘택홀과 콘택패드용 제2콘택홀을 형성하되, 경사지게 형성하는 공정과, 상기 콘택패드용 콘택홀을 통하여 상기 소오스/드레인 접합영역에 접속되는 콘택패드를 형성하되, 선택성장 방법으로 상기 게이트전극의 일측을 도포하는 크기로 형성하는 공정과, 전체표면상부을 평탄화시키는 제2절연막을 소정두께 형성하는 공정과, 상기 제2절연막을 식각하는 비트라인 콘택공정으로 비트라인 콘택홀을 형성하는 공정과, 상기 비트라인 콘택홀을 통하여 콘택패드에 접속되는 비트라인을 형성하는 공정과, 전체표면상부를 평탄화시키는 제3절연막을 소정두께 형성하는 공정과, 상기 제3절연막과 제2절연막을 식각하는 저장전극 콘택공정으로 저장전극 콘택홀을 형성하는 공정과, 상기 저장전극 콘택홀을 통하여 상기 콘택패드에 접속되는 저장전극을 형성하는 공정을 포함하는 것을 특징으로 한다.According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a gate electrode over a semiconductor substrate; thinning a first insulating film for planarizing an upper portion of the gate electrode; A step of forming a first contact hole for a contact pad and a second contact hole for a contact pad exposing a source / drain junction region formed in a semiconductor substrate and forming the contact hole so as to be inclined; Forming a contact pad to be connected to a region of the gate electrode, the gate electrode having a size to coat one side of the gate electrode by a selective growth method, a step of forming a predetermined thickness of a second insulating film for planarizing the entire upper surface, Forming a bit line contact hole in a bit line contact process to be etched; A step of forming a predetermined thickness of a third insulating film for planarizing an upper surface of the entire surface; a step of forming a storage electrode contact hole in the storage electrode contact step for etching the third insulating film and the second insulating film; And forming a storage electrode connected to the contact pad through the storage electrode contact hole.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2f는 본 발명의 실시예에 따른 반도체소자의 제조방법을 도시한다.2A to 2F show a method of manufacturing a semiconductor device according to an embodiment of the present invention.
도 2a는 종래기술에 따른 도 1과 대비하여 도시한 레이아웃도로서, 반도체기판(11) 상부에 게이트전극(15)을 형성하고, 상기 반도체기판(11)의 소오스/드레인 접합영역(도시안됨)에 접속되는 콘택패드(27)를 형성한 다음, 상기 콘택패드를 노출시키는 비트라인 콘택홀(31)과 저장전극 콘택홀(39)을 형성한 것이다.1, a gate electrode 15 is formed on a semiconductor substrate 11 and a source / drain junction region (not shown) of the semiconductor substrate 11 is formed. A bit line contact hole 31 and a storage electrode contact hole 39 are formed to expose the contact pad.
여기서, 상기 콘택홀(31,39)은 상기 게이트전극(15)간의 거리에 별도의 공간을 필요로 하지 않아 콘택공정의 공정마진을 향상시켜 콘택공정을 용이하게 하고 그에 따른 반도체소자의 특성 및 신뢰성을 향상시킬 수 있다.Since the contact holes 31 and 39 do not require a space in the distance between the gate electrodes 15, the process margin of the contact process is improved to facilitate the contact process, and the characteristics and reliability of the semiconductor device Can be improved.
도 2b 내지 도 2f는 상기 도2a의 ⓐ - ⓐ 절단면을 따라 본 발명의 실시예에 의한 반도체소자 제조방법을 도시한 단면도이다.2B to 2F are cross-sectional views illustrating a method of fabricating a semiconductor device according to an embodiment of the present invention along a cutting plane a-a of FIG. 2A.
먼저, 반도체기판(11) 상부에 소자분리절연막(13)을 형성한다. 그리고 상기 반도체기판(11) 상부에 게이트전극(15)을 형성하고, 상기 게이트전극(15) 측벽에 절연막 스페이서(17)를 형성한 다음, 상기 반도체기판(11)에 소오스/드레인 접합영역(19)을 형성한다.First, an element isolation insulating film 13 is formed on a semiconductor substrate 11. A gate electrode 15 is formed on the semiconductor substrate 11 and an insulating film spacer 17 is formed on a sidewall of the gate electrode 15. A source / drain junction region 19 ).
그리고 전체표면상부를 평탄화 시키는 제1절연막(21)을 평탄화될 수 있을 정도로 얇게 형성한다.The first insulating film 21 for planarizing the entire upper surface is formed to be thin enough to be flattened.
이때, 상기 제1절연막(21)은 산화막으로 형성한다. (도 2b)At this time, the first insulating film 21 is formed of an oxide film. (Figure 2b)
그 다음에, 콘택마스크(도시안됨)를 이용한 경사식각공정으로 상기 게이트전극(15)과의 단선을 방지하며 상기 소오스/드레인 접합영역(19)을 노출시키는 콘택패드용 제1콘택홀(23)과 콘택패드용 제2콘택홀(25)을 형성한다.Thereafter, a first contact hole 23 for a contact pad, which prevents disconnection from the gate electrode 15 and exposes the source / drain junction region 19 by a tilt etching process using a contact mask (not shown) And a second contact hole 25 for a contact pad.
이때, 상기 콘택마스크는 반도체기판(11)의 소오스/드레인 접합영역(19)을 노출시킬 수 있는 것이다.At this time, the contact mask can expose the source / drain junction region 19 of the semiconductor substrate 11.
그리고 상기 콘택패드용 제1콘택홀(23)과 콘택패드용 제2콘택홀(25)은 상기 반도체기판(11)의 셀부과 주변회로부에 동시에 형성하거나 셀부에만 형성한다.The first contact hole 23 for the contact pad and the second contact hole 25 for the contact pad are formed simultaneously in the cell portion and the peripheral circuit portion of the semiconductor substrate 11 or only in the cell portion.
그 다음에, 상기 콘택패드용 콘택홀(23,25)을 통하여 상기 반도체기판(11)의 소오스/드레인 접합영역(19)에 접속되는 콘택패드(27)를 형성한다.Then, contact pads 27 connected to the source / drain junction regions 19 of the semiconductor substrate 11 are formed through the contact pads 23 and 25 for the contact pads.
이때, 상기 콘택패드(27)는 선택적 에피탁셜 성장(Seletive Epitaxial Growth, 이하에서 SEG라함) 방법이나 선택적 다결정실리콘막 성장방법을 이용하여 성장시킨 다음, 불순물을 도핑하여 형성한다.At this time, the contact pad 27 is grown by selective epitaxial growth (SEG) or an optional polycrystalline silicon film growth method, and then doped with impurities.
여기서, 상기 불순물 도핑공정은 임플란트(implant)공정이나 가스를 이용하여 실시한다.(도 2c)Here, the impurity doping process is performed using an implant process or gas (FIG. 2C)
그 다음에, 전체표면상부에 제2절연막(29)을 소정두께 증착하여 평탄화시킨다.그리고, 비트라인 콘택마스크(도시안됨)를 이용한 식각공정으로 상기 제2절연막(29)을 식각하여 상기 제1콘택홀(23) 상부의 콘택패드(27)를 노출시키는 비트라인 콘택홀(31)을 형성한다.Then, a second insulating film 29 is deposited on the entire surface to a predetermined thickness to be planarized. Then, the second insulating film 29 is etched by an etching process using a bit line contact mask (not shown) The bit line contact hole 31 exposing the contact pad 27 on the contact hole 23 is formed.
이때, 상기 제2절연막(29)은 플로우가 잘되는 산화막으로 형성한다.At this time, the second insulating layer 29 is formed of a well-flowable oxide layer.
그리고 상기 비트라인 콘택홀(31)을 통하여 상기 콘택패드(27)에 접속되는 비트라인(33)을 형성한다.(도 2d)And a bit line 33 connected to the contact pad 27 through the bit line contact hole 31 is formed (FIG. 2D)
그 다음에, 전체표면상부에 제3절연막(35)으로 평탄화시키고 그 상부에 감광막패턴(37)을 형성한다. 이때, 상기 감광막패턴(37)은 저장전극 콘택마스크(도시안됨)를 이용하여 감광막을 노광 및 현상하여 형성한다.Then, the third insulating film 35 is planarized on the entire upper surface, and the photoresist pattern 37 is formed on the third insulating film 35. At this time, the photoresist pattern 37 is formed by exposing and developing the photoresist using a storage electrode contact mask (not shown).
그리고 상기 감광막패턴(37)을 마스크로하여 상기 제3절연막(35)과 제2절연막(29)을 순차적으로 식각하여 상기 제2콘택홀(25) 상부의 콘택패드(27)를 노출시키는 저장전극 콘택홀(39)을 형성한다.(도 2e)The third insulating film 35 and the second insulating film 29 are sequentially etched using the photoresist pattern 37 as a mask to expose the contact pad 27 on the second contact hole 25. Then, Thereby forming a contact hole 39 (Fig. 2E)
그 다음에, 상기 감광막패턴(37)을 제거하고, 상기 저장전극 콘택홀(39)을 통하여 상기 콘택패드(27)에 접속되는 저장전극을 형성한다.Then, the photoresist pattern 37 is removed, and a storage electrode connected to the contact pad 27 is formed through the storage electrode contact hole 39.
이때, 상기 저장전극은 텅스텐이나 백금과 같은 금속물질로 형성한다.(도 2f)At this time, the storage electrode is formed of a metal material such as tungsten or platinum (Figure 2F). [
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 제조방법은, 반도체기판에 게이트 전극을 형성하고 전체표면상부를 평탄화시키는 제1절연막을 얇게 형성한 다음, 비트라인과 저장전극이 접속될 셀부의 소오스/드레인 접합영역을 노출시키는 콘택피트용 콘택홀을 형성하고, 상기 노출된 소오스/드레인 접합영역에 접속되는 콘택패드를 형성한 다음, 상기 노출된 소오스/드레인 접합영역에 접속되는 콘택패드를 형성한 다음, 후속공정으로 용이하게 비트라인 콘택공정 및 저장전극 콘택공정을 실시하여 공정마진을 증가시키고 셀 크기를 감소시키며 상기 반도체기판의 손상없이 비트라인과 저장전극을 형성함으로써 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 잇점이 있다.As described above, the method of manufacturing a semiconductor device according to the present invention is characterized in that a gate electrode is formed on a semiconductor substrate and a first insulating film for planarizing the entire upper surface is formed thin, and then a bit line and a source electrode / Drain junction region, forming a contact pad connected to the exposed source / drain junction region, and then forming a contact pad connected to the exposed source / drain junction region Next, the bit line contact process and the storage electrode contact process are easily performed in the subsequent process to increase the process margin, decrease the cell size, and form the bit line and the storage electrode without damaging the semiconductor substrate, thereby improving the characteristics and reliability of the semiconductor device So that it is possible to achieve high integration of the semiconductor device.
Claims (6)
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| KR1019960050632A KR100214279B1 (en) | 1996-10-31 | 1996-10-31 | Method of manufacturing semiconductor device |
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