KR100290479B1 - Test Pattern Formation Method of Semiconductor Device - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

A test pattern forming method of a semiconductor device of the present invention.

2. The technical problem of the invention

Solving the problem that the electrical properties between the plug and the bit line (or the charge storage electrode) cannot be monitored because the polysilicon deposited to form the plug is removed by the front etching or CMP process in the manufacturing of the semiconductor device to which the landing plug is applied I would like to.

3. Summary of the Solution of the Invention

When the first insulating oxide film is etched to form the landing plug in the cell region, the silicon oxide is deposited after etching to the size of the test pattern requiring the first insulating oxide film in the test pattern region.

Description

Test Pattern Formation Method of Semiconductor Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a test pattern of a semiconductor device, and more particularly, to a chain resistance between a bit line contact or a charge storage electrode contact and a landing plug in a semiconductor device manufacturing process using a landing plug process. The present invention relates to a method of forming a test pattern of a semiconductor device capable of monitoring electrical characteristics such as leakage current and stabilizing a process.

As the semiconductor device is highly integrated, the size of the contact becomes smaller and the depth of the contact increases. In particular, when the bit line is formed of polyside (polysilicon / tungsten silicide) in the active region, it is difficult to embed the bit line contact due to the poor step coverage property of the tungsten silicide, which significantly lowers the electrical characteristics. In addition, when the charge storage electrode contact is formed due to the increase of the step, the contact is difficult to be formed because the deep contact is formed, and the substrate loss is severely generated at the junction, thereby increasing the leakage current. Being derived.

In order to solve this problem, a landing plug process of forming a plug at a position where a bit line contact and a charge storage electrode contact are to be formed is applied to a device of 256M DRAM class or more. The landing plug is formed by the following process. After forming the gate electrode, an insulating oxide film is formed over the entire structure. A contact is formed by selectively etching the insulating oxide film of the portion where the bit line and the charge storage electrode are to be formed. After depositing a polysilicon film having a predetermined thickness, a polysilicon film is left only inside the contact by a front etching or a CMP process, and the remaining part is removed to form a plug. Thereafter, a bit line or a charge storage electrode is formed on the plug.

1 (a) and 1 (b) are cross-sectional photographs of devices in which bit lines are formed by applying a landing plug process. Since the bit line or the charge storage electrode formed by applying the landing plug process has good contact resistance characteristics and leakage current characteristics, the refresh characteristics are remarkably improved. However, there is a disadvantage that it is difficult to stabilize the process because the number of processes is increased and the process is complicated compared to the existing process. In particular, when the landing plug process is applied, the interface between the thin films is increased to the junction / plug / bit line (or charge storage electrode) compared to the conventional junction / bit line (or charge storage electrode), making monitoring for process evaluation difficult. .

All devices currently under research and development form test patterns for evaluating the characteristics of each process, and each process characteristic is monitored on this test pattern.

In the case where the landing plug process is applied, conditions for electrically affecting the bit line or the charge storage electrode may include a junction condition, a plug formation condition, a bit line or a charge storage electrode formation condition. Therefore, a test pattern for monitoring electrical characteristics such as a chain resistance and a leakage current between the junction and the plug and between the plug and the bit line (or the charge storage electrode) is necessary. However, in the current process, the plug is left only inside the contact of the cell region by the front etching or CMP process, and the rest is removed, thereby forming a test pattern for monitoring the electrical characteristics of the plug and bit line (or charge storage electrode). none. Currently, only test patterns that can evaluate the overall electrical characteristics of the junction / plug / bit line (or charge storage electrode) can be formed, and the electrical characteristic values are the combined values of the junction, plug, and bit line (or charge storage electrode) processes. to be. Therefore, it is not possible to know in which process a problem occurs during the process integration (initialization) process in the early stage of research and development, and there is a problem that process stabilization is also difficult.

2 is a cross-sectional view of a device for explaining a test pattern forming method of a conventional semiconductor device. As illustrated, an insulating oxide layer 13 is formed on the entire structure including the lower layer pattern 12 selectively formed on the semiconductor substrate 11. The selected region of the insulating oxide film 13 is etched to form the contact hole 14. After depositing a polysilicon layer on the entire structure, the surface is etched or a CMP process is performed to form a plug. An upper layer pattern 15 is formed on the contact hole 14 on which the plug is formed.

In the test pattern formed as described above, since the contact chain resistance is monitored by the current path 16 between the upper layer pattern 15, the plug and the lower layer pattern 12, the lower layer pattern 12 is necessary. However, the landing plug process cannot form a lower layer pattern because the polysilicon for forming the plug is completely removed by the front etching or the CMP process.

Accordingly, an object of the present invention is to provide a method of forming a test pattern of a semiconductor device for evaluating respective processes such as evaluating contact chain resistance characteristics between a bit line (or a charge storage electrode) and a plug.

According to an aspect of the present invention, there is provided a method of forming a first insulating film on a semiconductor substrate on which a device isolation film is formed in a selected region, exposing the semiconductor region by etching the selected region of the first insulating film, and Forming a first polysilicon film on the exposed portion of the semiconductor substrate by etching the first insulating film, and forming a second insulating film on the entire structure, and then patterning the second insulating film to expose two selected portions of the first polysilicon film. And forming a second polysilicon film over the entire structure, and then patterning the same to expose a selected region of the second insulating oxide film exposing selected two portions of the first polysilicon film.

1 (a) and 1 (b) are cross-sectional photographs of devices in which bit lines are formed by applying a landing plug process.

2 is a cross-sectional view of a device for explaining a test pattern forming method of a conventional semiconductor device.

3 (a) to 3 (c) are cross-sectional views of devices for explaining a test pattern forming method of a semiconductor device according to the present invention.

<Description of the symbols for the main parts of the drawings>

11 semiconductor substrate 12 lower layer pattern

13 insulating oxide film 14 contact hole

15: upper layer pattern 16: current pass

A: cell area B: test pattern area

21 semiconductor substrate 22 device isolation film

23 gate electrode 24 first insulating oxide film

25: first contact hole 26: first polysilicon film

27: second insulating oxide film 28: second polysilicon film

The present invention will be described in detail with reference to the accompanying drawings.

3 (a) to 3 (c) are cross-sectional views of a device for explaining a test pattern forming method of a semiconductor device according to the present invention. The cell region A and the test pattern region B are shown separately.

Referring to FIG. 3A, the device isolation layer 22 is formed in a selected region on the semiconductor substrate 21. The gate electrode 23 is formed in the selected region on the semiconductor substrate 21 in the cell region A in which the device isolation layer 22 is formed. When the first insulating oxide 24 is formed on the entire structure, the selected region of the first insulating oxide 24 of the cell region A is etched to form the first contact hole 25 in which the landing plug is to be formed. The first insulating oxide film 24 in the test pattern region B is etched to the size of the test pattern required.

Referring to FIG. 3B, the first polysilicon layer 26 is deposited on the entire structure including the cell region A and the test pattern region B, and then planarized by performing an entire surface etching or CMP process. In this process, a plug is formed in the cell region A, and the first insulating oxide film 24 is etched in the test pattern region B to the size of the test pattern required. The buried first polysilicon film 26 is not etched.

Referring to FIG. 3C, after forming the second insulating oxide film 27 over the entire structure, the second contact hole is formed by etching the selected region of the second insulating oxide film 27 formed in the cell region A. Referring to FIG. do. At the same time, the second insulating oxide film 27 formed on the first polysilicon film 26 in the test pattern region B is patterned so that a part of the first polysilicon film 26 is exposed. The second contact hole formed in the cell region A is formed to be in contact with the landing plug. The second polysilicon layer 28 is deposited on the entire structure to fill the second contact hole formed in the cell region A, and then patterned to form a bit line. At the same time, the second polysilicon film 28 is patterned so that a part of the second insulating oxide film 27 formed on the first polysilicon film 26 in the test pattern region B is exposed.

As described above, according to the present invention, the contact resistance and the leakage current between the plug formed by the landing plug process and the bit line (or the charge storage electrode) can be measured, so that it is easy to monitor in which process the problem occurs.

Claims (2)

Forming a first insulating film on the semiconductor substrate on which the device isolation film is formed in the selected region; Etching the selected region of the first insulating layer to expose the semiconductor region; Forming a first polysilicon film on a portion of the semiconductor substrate exposed by etching the first insulating film; Forming and then patterning a second insulating film over the entire structure to expose two selected portions of the first polysilicon film; Forming a second polysilicon film over the entire structure and patterning the semiconductor substrate to expose the selected region of the second insulating oxide film exposing selected two portions of the first polysilicon film. Pattern formation method. The method of claim 1, wherein the first insulating layer is etched by a size of a required test pattern.