KR20070005321A - Test pattern for measuring the contact resistance of metal interconnection - Google Patents

Test pattern for measuring the contact resistance of metal interconnection Download PDF

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Publication number
KR20070005321A
KR20070005321A KR1020050060597A KR20050060597A KR20070005321A KR 20070005321 A KR20070005321 A KR 20070005321A KR 1020050060597 A KR1020050060597 A KR 1020050060597A KR 20050060597 A KR20050060597 A KR 20050060597A KR 20070005321 A KR20070005321 A KR 20070005321A
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South Korea
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test
contact resistance
film
metal line
metal wiring
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KR1020050060597A
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Korean (ko)
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노일철
김춘환
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주식회사 하이닉스반도체
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Priority to KR1020050060597A priority Critical patent/KR20070005321A/en
Publication of KR20070005321A publication Critical patent/KR20070005321A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line

Abstract

A test pattern for measuring contact resistance of a metal line is provided to acquire exact contact resistance by forming a line pitch of a test metal line layer same as that of a real metal line layer. A test pattern is used for measuring a contact resistance of a metal line structure, wherein the metal line structure is composed of a first metal line layer of a first level, a second metal line layer of a second level, and a via contact for connecting the first and second metal line layers with each other. The test pattern is composed of a first test metal line layer(310) corresponding to the first metal line layer and a second test metal line layer(320) corresponding to the second metal line layer, The first and second test metal line layers have the same line pitches as those of the first and second metal line layers.

Description

금속배선의 컨택저항 측정을 위한 테스트패턴{Test pattern for measuring the contact resistance of metal interconnection}Test pattern for measuring the contact resistance of metal interconnection

도 1은 종래의 컨택저항 측정을 위한 테스트패턴을 나타내 보인 단면도이다.1 is a cross-sectional view illustrating a test pattern for measuring a conventional contact resistance.

도 2는 도 1의 테스트패턴의 평면도이다.FIG. 2 is a plan view of the test pattern of FIG. 1.

도 3은 본 발명에 따른 컨택저항 측정을 위한 테스트패턴을 나타내 보인 평면도이다.3 is a plan view illustrating a test pattern for measuring contact resistance according to the present invention.

본 발명은 반도체소자의 금속배선에 있어서의 컨택저항측정에 관한 것으로서, 특히 금속배선의 컨택저항 측정을 위한 테스트패턴에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the measurement of contact resistance in metal wiring of semiconductor devices, and more particularly to a test pattern for measuring contact resistance of metal wiring.

최근 소자의 집적도가 증가함에 따라 금속배선도 점점 다층화 되어 가고 있다. 이와 같이 다층금속배선구조에 있어서 서로 다른 레벨의 금속배선막을 전기적으로 연결시키는 비아컨택의 개수도 늘어나고 있으며, 이와 같은 비아컨택의 컨택저항은 소자의 전기적인 특성에 영향을 끼칠 수 있다. 이에 따라 금속배선을 형성한 후에 컨택저항을 측정하여 소망하는 전기적인 특성을 얻는 것이 일반적이다. 통상적으로 컨택저항의 측정은 실제 금속배선구조와 유사한 테스트패턴을 사용하여 이루어진다.With the recent increase in the degree of integration of metals, metallization has become increasingly multilayered. As described above, the number of via contacts electrically connecting different levels of metal wiring layers in a multilayer metal wiring structure is increasing, and the contact resistance of the via contacts may affect the electrical characteristics of the device. Accordingly, it is common to obtain a desired electrical characteristic by measuring contact resistance after forming metal wiring. Typically, the contact resistance is measured using a test pattern similar to the actual metal wiring structure.

도 1은 종래의 컨택저항 측정을 위한 테스트패턴을 나타내 보인 단면도이다. 그리고 도 2는 도 1의 테스트패턴의 평면도이다.1 is a cross-sectional view illustrating a test pattern for measuring a conventional contact resistance. 2 is a plan view of the test pattern of FIG. 1.

도 1 및 도 2를 참조하면, 하부 레벨의 제1 테스트금속배선막(110)이 배치되고, 그 위에는 상부 레벨의 제2 테스트금속배선막(120)이 배치된다. 도면에 나타내지는 않았지만, 제1 테스트금속배선막(110)과 제2 테스트금속배선막(120) 사이에는 금속간절연막(미도시)이 배치될 수 있다. 제2 테스트금속배선막(120)의 양 단부에는 각각 외부로의 전기적인 신호전달을 위한 제1 패드(131) 및 제2 패드(132)가 배치된다. 제1 테스트금속배선막(110)과 제2 테스트금속배선막(120)은 금속간절연막을 관통하는 비아컨택(140)에 의해 상호 전기적으로 연결된다.1 and 2, a lower level first test metal interconnection film 110 is disposed, and an upper level second test metal interconnection film 120 is disposed thereon. Although not shown in the drawings, an intermetallic insulating film (not shown) may be disposed between the first test metal wiring layer 110 and the second test metal wiring layer 120. The first pad 131 and the second pad 132 are disposed at both ends of the second test metal wiring layer 120 to transmit electrical signals to the outside. The first test metallization film 110 and the second test metallization film 120 are electrically connected to each other by a via contact 140 penetrating the intermetallic insulating film.

이와 같이 종래의 컨택저항 측정을 위한 테스트패턴은, 제1 테스트금속배선막(110)과 제2 테스트금속배선막(120) 사이의 컨택을 직렬로 연결한 체인(chain) 형태로 이루어진다. 특히 비아컨택(140)과 연결되는 테스트금속배선막의 경우, 충분한 오버레이 마진(overlay margin)을 위해 실제 금속배선막의 폭보다 큰 폭을 갖는 직사각형 형태로 형성된다.As described above, the test pattern for measuring the conventional contact resistance is formed in a chain form in which contacts between the first test metal wiring layer 110 and the second test metal wiring layer 120 are connected in series. In particular, the test metal interconnection film connected to the via contact 140 is formed in a rectangular shape having a width larger than that of the actual metal interconnection film for sufficient overlay margin.

그러나 소자의 집적도가 증가함에 따라, 컨택저항은 컨택을 구성하는 물질과 컨택 계면상태에 의한 컨택 자체의 저항에 의해서만 결정되는 것이 아니라, 비아컨택과 금속배선막의 미스얼라인(misalign)에 의해 영향을 받는다. 즉 미스얼라인이 증가할수록 컨택저항도 증가한다. 또한 웨이퍼 내의 위치별 미스얼라인의 크기가 다를 경우 컨택저항의 균일도(uniformity) 측면에서 열화된 특성을 나타낸다. 즉 테스트패턴이 아닌 실제 소자의 컨택과 금속배선라인 사이의 오버레이가 정렬되지 못하면, 컨택저항은 증가하고 소자 내의 컨택저항 균일도 특성도 달라지게 된다. 그러나 종래의 테스트패턴의 경우 오버레이의 미스얼라인을 고려하지 않은 구조이므로, 실제 소자 내에서의 컨택저항의 오버레이 미스얼라인에 따른 변화에 따른 컨택저항과는 차이를 나타내며, 이에 따라 컨택저항을 정확하게 측정하는데 한계를 나타낸다.However, as the density of devices increases, the contact resistance is not only determined by the resistance of the contact itself due to the material constituting the contact and the contact interface state, but is influenced by the misalignment of the via contact and the metallization layer. Receive. In other words, as misalignment increases, contact resistance also increases. In addition, when the size of the misalignment for each position in the wafer is different, it shows deteriorated characteristics in terms of uniformity of contact resistance. In other words, if the overlay between the contact of the actual device and the metal wiring line, not the test pattern, is not aligned, the contact resistance is increased and the contact resistance uniformity characteristics of the device are changed. However, since the conventional test pattern does not consider the overlay misalignment, it shows a difference from the contact resistance caused by the change of the overlay misalignment of the contact resistance in the actual device. Indicates a limit to measurement.

본 발명이 이루고자 하는 기술적 과제는, 실제 금속배선패턴에서의 오버레이 미스얼라인에 따른 컨택저항의 변화를 반영하여 정확한 컨택저항을 측정할 수 있도록 하는 테스트패턴을 제공하는 것이다.The technical problem to be achieved by the present invention is to provide a test pattern that can accurately measure the contact resistance by reflecting the change in contact resistance according to the overlay misalignment in the actual metal wiring pattern.

상기 기술적 과제를 달성하기 위하여, 본 발명에 따른 금속배선의 컨택저항 측정을 위한 테스트패턴은, 제1 레벨의 제1 금속배선막과, 제2 레벨의 제2 금속배선막과, 그리고 상기 제1 금속배선막 및 제2 금속배선막을 연결하는 비아컨택을 갖는 금속배선구조의 컨택저항 측정을 위한 테스트패턴에 있어서, 상기 제1 금속배선막에 대응하는 제1 테스트 금속배선막과, 상기 제2 금속배선막에 대응하는 제2 테스트 금속배선막을 구비하며, 상기 제1 테스트 금속배선막 및 제2 테스트 금속배선막은 상기 제1 금속배선막 및 제2 금속배선막과 각각 동일한 라인 피치를 갖는 것을 특징으로 한다.In order to achieve the above technical problem, the test pattern for measuring the contact resistance of the metal wiring according to the present invention, the first metal wiring film of the first level, the second metal wiring film of the second level, and the first A test pattern for measuring contact resistance of a metal wiring structure having a via contact connecting a metal wiring film and a second metal wiring film, the test pattern comprising: a first test metal wiring film corresponding to the first metal wiring film, and the second metal And a second test metal interconnection film corresponding to the interconnection film, wherein the first test metal interconnection film and the second test metal interconnection film have the same line pitch as the first metal interconnection film and the second metal interconnection film, respectively. do.

상기 제1 테스트 금속배선막의 단부에 연결되는 제1 패드와, 상기 제2 테스 트 금속배선막의 단부에 연결되는 제2 패드를 더 구비할 수 있다.The display device may further include a first pad connected to an end of the first test metal interconnection film and a second pad connected to an end of the second test metal interconnection film.

이하 첨부 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다. 그러나, 본 발명의 실시예들은 여러 가지 다른 형태로 변형될 수 있으며, 본 발명의 범위가 아래에서 상술하는 실시예들로 인해 한정되어지는 것으로 해석되어져서는 안된다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below.

도 3은 본 발명에 따른 컨택저항 측정을 위한 테스트패턴을 나타내 보인 평면도이다. 본 발명에 따른 컨택저항 측정을 위한 테스트패턴의 단면도는 도 1과 동일하며, 따라서 이하에서는 단면구조의 설명에 대해서는 생략하기로 한다.3 is a plan view illustrating a test pattern for measuring contact resistance according to the present invention. The cross-sectional view of the test pattern for measuring contact resistance according to the present invention is the same as that of FIG. 1, and therefore, the description of the cross-sectional structure will be omitted below.

도 3을 참조하면, 하부 레벨에는 제1 테스트금속배선막(310)이 배치되고, 그 위의 상부 레벨에는 제2 테스트금속배선막(320)이 배치된다. 제1 테스트금속배선막(310)은 실제 소자의 하부 레벨의 제1 금속배선막에 대응된다. 제2 테스트금속배선막(320)은 실제 소자의 상부 레벨의 제2 금속배선막에 대응된다. 도면에 나타내지는 않았지만, 제1 테스트금속배선막(310)과 제2 테스트금속배선막(320) 사이에는 금속간절연막(미도시)이 배치될 수 있다. 제2 테스트금속배선막(320)의 양 단부에는 각각 외부로의 전기적인 신호전달을 위한 제1 패드(331) 및 제2 패드(332)가 배치된다. 제1 테스트금속배선막(310)과 제2 테스트금속배선막(320)은 금속간절연막을 관통하는 비아컨택(340)에 의해 상호 전기적으로 연결된다.Referring to FIG. 3, a first test metal wiring layer 310 is disposed at a lower level, and a second test metal wiring layer 320 is disposed at an upper level thereof. The first test metallization film 310 corresponds to the first metallization film of a lower level of the actual device. The second test metallization film 320 corresponds to the second metallization film of the upper level of the actual device. Although not shown in the drawings, an intermetallic insulating film (not shown) may be disposed between the first test metal wiring film 310 and the second test metal wiring film 320. First and second pads 331 and 332 are disposed at both ends of the second test metal wiring layer 320 to transmit electrical signals to the outside, respectively. The first test metal interconnection layer 310 and the second test metal interconnection layer 320 are electrically connected to each other by a via contact 340 penetrating the intermetallic insulation layer.

상기 제1 테스트금속배선막(310)의 라인 피치(line pitch)는 실제 소자의 제1 금속배선막의 라인 피치와 실질적으로 동일하다. 마찬가지로 제2 테스트금속배선막(320)의 라인 피치도 실제 소자의 제2 금속배선막의 라인 피치와 동일하다. 따라 서 실제 소자의 제1 금속배선막이나 제2 금속배선막의 오버레이 미스얼라인이 발생하는 경우, 본 발명에 따른 테스트패턴에 있어서도 동일한 오버레이 미스얼라인이 발생하고, 이에 따라 실제 소자의 오버레이 미스얼라인에 의한 컨택저항의 변화와 동일하게 테스트패턴에 있어서도 실질적으로 동일한 컨택저항의 변화를 나타낸다.The line pitch of the first test metal interconnection film 310 is substantially the same as the line pitch of the first metal interconnection film of the actual device. Similarly, the line pitch of the second test metal wiring film 320 is also the same as the line pitch of the second metal wiring film of the actual device. Therefore, when overlay misalignment of the first metal interconnection film or the second metal interconnection film of the actual device occurs, the same overlay misalignment occurs in the test pattern according to the present invention, and thus overlay misalignment of the actual device. Similarly to the change in the contact resistance due to phosphorus, the same change in the contact resistance in the test pattern is shown.

지금까지 설명한 바와 같이, 본 발명에 따른 금속배선의 컨택저항 측정을 위한 테스트패턴에 의하면, 테스트 금속배선막의 라인 피치를 실제 금속배선막의 라인 피치와 동일하게 형성함으로써, 실제 금속배선막에서의 오버레이 미스얼라인에 따른 컨택저항의 변화를 반영하는 정확한 컨택저항 측정을 가능하게 한다는 이점이 제공된다.As described above, according to the test pattern for measuring the contact resistance of the metal wiring according to the present invention, by forming the line pitch of the test metal wiring film to be the same as the line pitch of the actual metal wiring film, the overlay miss in the actual metal wiring film An advantage is provided to enable accurate contact resistance measurements that reflect changes in contact resistance over alignment.

이상 본 발명을 바람직한 실시예를 들어 상세하게 설명하였으나, 본 발명은 상기 실시예에 한정되지 않으며, 본 발명의 기술적 사상 내에서 당 분야에서 통상의 지식을 가진 자에 의하여 여러 가지 변형이 가능함은 당연하다.Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the technical spirit of the present invention. Do.

Claims (2)

제1 레벨의 제1 금속배선막과, 제2 레벨의 제2 금속배선막과, 그리고 상기 제1 금속배선막 및 제2 금속배선막을 연결하는 비아컨택을 갖는 금속배선구조의 컨택저항 측정을 위한 테스트패턴에 있어서,For contact resistance measurement of a metal wiring structure having a first metal wiring film of a first level, a second metal wiring film of a second level, and a via contact connecting the first metal wiring film and the second metal wiring film. In the test pattern, 상기 제1 금속배선막에 대응하는 제1 테스트 금속배선막과, 상기 제2 금속배선막에 대응하는 제2 테스트 금속배선막을 구비하며, 상기 제1 테스트 금속배선막 및 제2 테스트 금속배선막은 상기 제1 금속배선막 및 제2 금속배선막과 각각 동일한 라인 피치를 갖는 것을 특징으로 하는 금속배선의 컨택저항 측정을 위한 테스트패턴.A first test metal interconnection film corresponding to the first metal interconnection film, and a second test metal interconnection film corresponding to the second metal interconnection film, wherein the first test metal interconnection film and the second test metal interconnection film are A test pattern for measuring contact resistance of a metal wiring, wherein each of the first and second metal wiring films has the same line pitch. 제1항에 있어서,The method of claim 1, 상기 제1 테스트 금속배선막의 단부에 연결되는 제1 패드와, 상기 제2 테스트 금속배선막의 단부에 연결되는 제2 패드를 더 구비하는 것을 특징으로 하는 금속배선이 컨택저항 측정을 위한 테스트패턴.And a first pad connected to an end of the first test metal interconnection film, and a second pad connected to an end of the second test metal interconnection film.
KR1020050060597A 2005-07-06 2005-07-06 Test pattern for measuring the contact resistance of metal interconnection KR20070005321A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11480537B2 (en) * 2020-07-31 2022-10-25 International Business Machines Corporation Methods and structure to probe the metal-metal interface for superconducting circuits

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11480537B2 (en) * 2020-07-31 2022-10-25 International Business Machines Corporation Methods and structure to probe the metal-metal interface for superconducting circuits

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