KR20030056601A - Method of forming a source line in flash memory device - Google Patents

Abstract

PURPOSE: A method for forming a source line of a flash memory device is provided to be capable of improving process margin and overlap margin by using RELACS(Resolution Enhancement Lithography Assist Inspection Supplies System) and reducing variation of DICD(Develop Inspection Critical Dimension) and a photo resist pattern. CONSTITUTION: A semiconductor substrate(101) including an isolation layer, floating gate(105), a control gate(107), a source(102) and a drain(103), is prepared. After exposing the source and isolation layer using the first photoresist pattern, the exposed isolation layer is removed. After exposing the source(102) using the second photoresist pattern, source ions are implanted into the exposed source(102), thereby forming a source line(112).

Description

Method of forming a source line in flash memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor flash device manufacturing process, and more particularly, to source junction formation of a 128 mega flash device having a thickness of 0.18 μm or less.

In forming a cell source junction in a flash device, the prior art forms a source and a drain junction using a cell source / drain mask after completion of control gate formation.

1 is a layout for configuring a flash memory device according to the prior art.

2A to 2D are cross-sectional views taken along the line X-X 'of the layout diagram shown in FIG.

3A and 3B are cross-sectional views taken along the line X-X 'of the layout diagram shown in FIG.

Reference numeral 1 denotes a semiconductor substrate, 2 field oxide film, 3 source, 4 drain, 5 tunnel oxide film, 6 floating gate, 7 ONO insulating film, 8 control gate, 9 pad nitride film, 10 antireflection film 11 denotes a photoresist pattern for SAS, 12 denotes a bit line, 13 denotes a word line, and 14 denotes a source line.

Referring to FIGS. 1, 2A, and 3A, after a photoresist is applied over an entire structure, an exposure and vision process using a self-aligned source mask (hereinafter referred to as a 'SAS') mask is performed. The source 3 region is exposed by forming the SAS photoresist pattern 11.

1 and 2B, the field oxide film 2 in the source region exposed by the SAS photoresist pattern 11 is removed by performing an etching process.

1, 2C, 2D, and 3B, source ions are implanted into the entire structure to form a source junction 14, and then to a bit line 12 in a subsequent process. It will be connected and used.

In the conventional process, since the photoresist acts as a barrier during the source etching and ion implantation processes, the thickness of the photoresist is about 1.0 μm or more. In flash memory with 0.18 tags or less, deep ultraviolet (DUV) process is performed when SAS photoresist pattern is formed to solve the lack of overlap margin and lack of lithography process on layout. Doing.

However, if the source line is defined to have a thickness of more than about 1.0 μm, the shape of the photoresist pattern for SAS is poor, resulting in a large variation in development inspection critical dimensions (DICD) due to lack of process margins. In addition, the photoresist slope reduces the overlap margin compared to 70 nm, which is currently 128M design overlap margin, there is a difficulty in not accurately knowing the thickness of the slope, and misalignment occurs. As a result, the cell source mask process margin cannot be secured by the conventional process, and may cause more problems when the device mass proceeds.

Therefore, in order to solve the above problems, a stable photoresist shape and process margin can be secured by applying a thin photoresist by performing a photoresist pattern twice during source etching and source ion implantation. An object of the present invention is to provide a method of forming a source line of a flash memory device capable of maximizing overlap margin.

In addition, the cell source mask is subjected to over-development of the DICD (develop inspection critical dimension) target site to obtain a good photoresist shape. It is an object of the present invention to provide a method of forming a source line of a flash memory device capable of securing a process margin and compensating for an overlap margin by protecting a photoresist pattern.

1 is a layout for configuring a flash memory device according to the prior art.

2A to 2D are cross-sectional views taken along the line X-X 'of the layout diagram shown in FIG.

3A and 3B are sectional views taken along the line Y-Y 'of the layout diagram shown in FIG.

4A to 4F are cross-sectional views illustrating a process for forming a source line of a flash memory device according to an embodiment of the present invention.

5A through 5G are cross-sectional views illustrating a process for forming a source line of a flash memory device according to another exemplary embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

1, 101, 201: semiconductor substrate 2: device isolation film

3, 102, 202: source 4, 103, 203: drain

5, 104, 204: tunnel oxide film 6, 105, 205: floating gate

7, 106, 206: insulating film 8, 107, 207: control gate

9, 108, 208: pad nitride film 10, 109, 209: antireflection film

11, 110, 111, 210: photoresist pattern 12: bit line

13: word line 14, 112, 213: source line

211: RELACS material 212: coating layer

Providing a semiconductor substrate having a device isolation layer, a floating gate, a control gate, a source and a drain, applying a first photoresist over the entire structure, and then exposing a portion of the source and device isolation layer; Removing the first photoresist after the removal of the first photoresist; applying a second photoresist on the entire structure; exposing the semiconductor substrate from which the source and the device isolation layer are removed; and the exposed source; And removing the second photoresist after implanting ions into a semiconductor substrate, thereby providing a source line forming method of a flash memory device.

Providing a semiconductor substrate having a device isolation film, a floating gate, a control gate, a source and a drain, forming a photoresist pattern exposing a portion of the source and device isolation film after applying a photoresist on the semiconductor substrate, Forming a coating layer on a surface of the photoresist pattern; exposing the semiconductor substrate from which the source and the device isolation layer are removed; implanting ions; and removing the coating layer and the photoresist pattern. A source line forming method of a flash memory device is provided.

Hereinafter, a first embodiment of the present invention will be described in more detail with reference to the accompanying drawings.

4A through 4F are cross-sectional views illustrating a process for forming a source line of a flash memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 4A, a tunnel oxide 104, a floating gate 105, an oxide / nitride / oxide (ONO) insulating layer 106, and a control gate layer (on a semiconductor substrate 101 on which an isolation layer is formed) are formed. 107). The pad nitride film 108 and the anti-reflection film 109 are sequentially deposited on the semiconductor substrate 101 on which the control gate layer 107 is formed. A flash memory cell is formed by performing a gate mask and etching process and a self aligned mask and etching process.

The thickness of the photoresist may be reduced by depositing the pad nitride layer 108 to a thickness of 2500 to 3000 microns and using it as a barrier during subsequent cell source etching and cell ion implantation. The anti-reflection film 109 is formed by depositing an anti-reflection film made of inorganic material having a thickness of 600 to 1500 Å or an anti-reflective film made of organic material having a thickness of about 300 Å on an anti-reflective film made of an inorganic material having a thickness of 600 to 1200 Å (ie, a photoresist serving as an anti-reflective film) ). The thickness of the photoresist may be reduced by using the pad nitride layer 108 and the anti-reflection layer 109 as barriers during source region etching and ion implantation after subsequent cell formation.

Referring to FIG. 4B, after the photoresist is applied on the semiconductor substrate 101 on which the flash memory cell is formed, the first photoresist pattern 110 is formed by performing an exposure and etching process using a photo mask. Expose the source region. The first photoresist pattern 110 is formed by a deep ultraviolet (DUV) process or an ArF process. In this case, since the first photoresist pattern 110 is used as a barrier only during subsequent cell source etching, the thickness of the photoresist may be reduced to 0.4 to 0.7 μm.

After the first photoresist pattern 110 is formed, the first photoresist pattern 110 is optimized by performing a heat treatment process for 90 to 110 seconds at a temperature of 90 to 110 ° C. In addition, by performing the heat treatment step 1 to 5 times to improve the curability of the photoresist can further lower the thickness of the photoresist.

Referring to FIG. 4C, using the first photoresist pattern 110 as a first cell source mask, the field oxide layer of the exposed source region 102 is removed by performing a predetermined etching process. The field oxide film of the drain region 103 is not removed, only the field oxide film of the source region 102 is removed. In this case, a first photoresist pattern 110, a pad nitride layer 108, and an antireflection layer 109 are used as the etching barrier. The first photoresist pattern 110 is removed by an etching process.

Referring to FIG. 4D, after the photoresist is applied over the entire structure, the source region 102 is exposed again by forming the second photoresist pattern 111 by performing an exposure and etching process using a photo mask. Let's do it. The second photoresist pattern 111 is formed by a DUV process or an ArF process. In this case, since the second photoresist pattern 111 is used as a barrier only in subsequent cell source ion implantation, the height of the photoresist may be reduced to 0.4 to 0.7 μm.

After the second photoresist pattern 111 is formed, heat treatment is performed for 90 to 110 minutes at a temperature of 90 to 110 ° C. to optimize the second photoresist pattern 111. In addition, by performing the heat treatment step 1 to 5 times to improve the curability of the photoresist can further lower the thickness of the photoresist.

4E and 4F, ions are implanted into the entire structure to form the source junction 112. By using the second photoresist pattern 111 as a second cell source mask, ions are implanted only in the exposed source region 102, and then a predetermined etching process is performed to remove the second photoresist pattern 111. Source junction 112 is formed.

By reducing the thickness of the photoresist to 0.5㎛ through the above method it is possible to secure a wide process margin and the vertical shape of the photoresist pattern. Therefore, it is easy to control development inspection critical dimensions (DICD) and overlay during the cell source mask process. In addition, the yield can be improved and the development time of the device can be shortened.

The above effects can be obtained through the RELACS process when forming the source junction.

Hereinafter, a second embodiment of the present invention will be described in detail with reference to the accompanying drawings.

5A through 5G are cross-sectional views illustrating a process for forming a source line of a flash memory device according to another exemplary embodiment of the present invention.

Referring to FIG. 5A, a tunnel oxide layer 204, a floating gate 205, an oxide / nitride / oxide (ONO) insulating layer 206, and a control gate layer may be formed on a semiconductor substrate 201 on which an isolation layer is formed. 207). The pad nitride film 208 and the anti-reflection film 209 are sequentially deposited on the semiconductor substrate 201 on which the control gate layer 207 is formed. A flash memory cell is formed by performing a gate mask and etching process and a self aligned mask and etching process.

The thickness of the photoresist may be reduced by depositing the pad nitride layer 208 to a thickness of 2500 to 3000 microns and using it as a barrier during subsequent cell source etching and cell ion implantation. The anti-reflection film 209 is formed by depositing an anti-reflection film made of an inorganic material having a thickness of 600 to 1500 kPa, or forming an anti-reflection film made of an organic material having a thickness of about 300 kPa on the anti-reflection film made of an inorganic material having a thickness of 600 to 1200 kPa. The thickness of the photoresist may be reduced by using the pad nitride layer 208 and the anti-reflection layer 209 as barriers during source region etching and ion implantation after subsequent cell formation.

Referring to FIG. 5B, a photoresist is coated on a semiconductor substrate 201 on which a flash memory cell is formed, and then a third photoresist pattern 210 is formed by performing an exposure and etching process using a photo mask. Source region 202 is exposed. The third photoresist pattern 210 is formed by a deep ultraviolet (DUV) process or an ArF process. The photoresist is tuned to overexposure and overfocus to form a vertical profile.

Referring to FIGS. 5C and 5D, a Resolution Enhancement Lithography Assist Chemical Supplies System (RELACS) material 211 is coated on a semiconductor substrate including the third photoresist pattern 210. Thereafter, a coating layer 212 is formed on the surface of the third photoresist pattern 210 by crosslinking through exposure and heating.

At this time, the heat treatment process for 90 to 110 seconds at a temperature of 90 to 110 ℃ to optimize the thickness of the coating layer (212). The thickness including the third photoresist pattern 210 and the coating layer 212 formed on the surface of the third photoresist pattern 210 is 0.7 to 1 μm. In addition, when the third photoresist pattern 210 is formed, the overlay margin, which is reduced by excessive exposure, is compensated by forming the coating layer 212.

Referring to FIG. 5E, the RELACS material 211 that does not react with the third photoresist pattern 210 is removed through a predetermined etching process. The field oxide layer of the exposed source region 202 is removed by a predetermined etching process by using the coating layer 212 on the third photoresist pattern 210 as a third cell source mask.

After the coating layer 212 is formed, a heat treatment process is performed at a temperature of 90 to 110 ° C. for 90 to 110 seconds, and the heat treatment process is performed 1 to 5 times to improve the curability of the photoresist and to form a third photoresist pattern 210. The thickness of the photoresist may be further lowered by optimizing the upper coating layer 212.

When the field oxide film is removed, the coating layer 212, the pad nitride film 208, and the anti-reflection film 209 on the third photoresist pattern 210 are used as an etching barrier.

5F and 5G, ions are implanted to form a source junction over the entire structure. Ions are implanted only into the exposed source region 202 using the coating layer 212 on the surface of the third photoresist pattern 210 as a third cell source mask. The source junction 213 is formed by removing the coating layer 212 and the third photoresist pattern 210 by performing a predetermined etching process.

By over-exposure and Kaito focus was adjusted to form a third photoresist pattern in a vertical shape to maximize the process margin, the RELACS process was applied to compensate for the overlap margin. In addition, since the mask process is performed only once, the process can be simplified and the effect of improving the yield and shortening the development period of the device can be increased.

As described above, in the method of forming a source line of a flash memory device according to the present invention, a vertical photoresist pattern may be formed by performing an etching and ion implantation process using two photoresist patterns and a development inspection critical dimension (DICD). Change can be reduced.

In addition, by reducing vertical photoresist patterns and DICD variations, process margins can be maximized and overlap margins improved.

In addition, the process margin and overlap margin may be improved by forming a single vertical photoresist pattern and forming a coating layer on the surface of the photoresist pattern through a Resolution Enhancement Lithography Assist Chemical Supplies System (RELACS) process.

Forming a single vertical photoresist pattern also simplifies the process, improves yield, and reduces device development time.

Claims (24)

Providing a semiconductor substrate on which an isolation layer, a floating gate, a control gate, a source, and a drain are formed; Exposing a portion of the source and device isolation film after applying a first photoresist over the entire structure; Removing the first photoresist after removing the exposed device isolation layer; Exposing the semiconductor substrate from which a portion of the source and the device isolation layer is removed after applying a second photoresist over the entire structure; And And removing the second photoresist after implanting ions into the exposed source and the semiconductor substrate. The method of claim 1, And the first and second photoresists are applied in a thickness of 0.4 to 0.7 mu m. The method of claim 1, And applying the first and second grape resists, exposing the source region, and then performing a heat treatment. The method of claim 3 The heat treatment process is a source line forming method of the flash memory device, characterized in that performed for 90 to 110 seconds at a temperature of 90 to 110 ℃. The method of claim 3, wherein The heat treatment process is a method for forming a source line of a flash memory device, characterized in that to perform repeatedly 1 to 5 times. The method of claim 1, And forming a nitride film and an anti-reflection film over the control gate. The method of claim 6, The nitride film is a source line forming method of the flash memory device, characterized in that deposited to a thickness of 2500 to 3000Å. The method of claim 6, And the anti-reflection film is formed of an inorganic anti-reflection film. The method of claim 8, The inorganic anti-reflection film is a source line forming method of the flash memory device, characterized in that deposited to a thickness of 600 to 1500Å. The method of claim 6, And the anti-reflection film is formed of an inorganic anti-reflection film and an organic anti-reflection film. The method of claim 10, The inorganic anti-reflection film is a source line forming method of the flash memory device, characterized in that deposited to a thickness of 600 to 1200Å. The method of claim 10, The organic anti-reflection film is a source line forming method of the flash memory device, characterized in that consisting of 1 to 300 GHz. Providing a semiconductor substrate on which an isolation layer, a floating gate, a control gate, a source, and a drain are formed; Forming a photoresist pattern exposing a portion of the source and device isolation film after applying the photoresist on the semiconductor substrate; Forming a coating layer on a surface of the photoresist pattern; Implanting ions after exposing the semiconductor substrate from which the source and the device isolation layer are removed; And And removing the coating layer and the photoresist pattern. The method of claim 13. The coating layer is formed by applying a heat treatment process after applying the RELACS material source line forming method of the flash memory device. The method of claim 14, The heat treatment process is a source line forming method of the flash memory device, characterized in that performed for 90 to 110 seconds at a temperature of 90 to 110 ℃. The method of claim 14, The heat treatment process is a method for forming a source line of a flash memory device, characterized in that to perform repeatedly 1 to 5 times. The method of claim 13, And the thickness of the photoresist pattern and the coating layer is 0.7 to 1 µm. The method of claim 13, And forming a nitride film and an anti-reflection film over the control gate. The method of claim 18, The pad nitride film is a source line forming method of the flash memory device, characterized in that deposited to a thickness of 2500 to 3000Å. The method of claim 18, And the anti-reflection film is formed of an inorganic anti-reflection film. The method of claim 20, The inorganic anti-reflection film is a source line forming method of the flash memory device, characterized in that deposited to a thickness of 600 to 1500Å. The method of claim 18, And the anti-reflection film is formed of an inorganic anti-reflection film and an organic anti-reflection film. The method of claim 22, The inorganic anti-reflection film is a source line forming method of the flash memory device, characterized in that deposited to a thickness of 600 to 1200Å. The method of claim 22, The organic anti-reflection film is a source line forming method of the flash memory device, characterized in that consisting of 1 to 300 GHz.