KR20030056321A - A forming method for self align contact of semiconductor device - Google Patents
A forming method for self align contact of semiconductor device Download PDFInfo
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- KR20030056321A KR20030056321A KR1020010086521A KR20010086521A KR20030056321A KR 20030056321 A KR20030056321 A KR 20030056321A KR 1020010086521 A KR1020010086521 A KR 1020010086521A KR 20010086521 A KR20010086521 A KR 20010086521A KR 20030056321 A KR20030056321 A KR 20030056321A
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- etching
- forming
- photoresist pattern
- hard mask
- insulating film
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- 238000000034 method Methods 0.000 title claims abstract description 32
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 39
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 31
- 239000010410 layer Substances 0.000 claims abstract description 17
- 239000011229 interlayer Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 150000004767 nitrides Chemical class 0.000 claims abstract description 10
- 229920000642 polymer Polymers 0.000 claims abstract description 10
- 239000007789 gas Substances 0.000 description 7
- 125000006850 spacer group Chemical group 0.000 description 4
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- ISQINHMJILFLAQ-UHFFFAOYSA-N argon hydrofluoride Chemical compound F.[Ar] ISQINHMJILFLAQ-UHFFFAOYSA-N 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 기술에 관한 것으로 특히, 불화아르곤(ArF) 노광원을 이용한 자기정렬콘택(Self Align Contact; 이하 SAC라 함) 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and in particular, to a method of forming a Self Align Contact (hereinafter referred to as SAC) using an argon fluoride (ArF) exposure source.
식각 공정에서 트랜지스터와 캐패시터를 연결하는 콘택 공정에서 0.18㎛ 이하의 미세 선폭을 갖는 반도체 소자에서는 직접 콘택 대신에 SAC 공정을 도입하여 사용하는 바, SAC 공정에서는 질화막과 산화막의 선택비를 이용하여 식각하는 방식식으로서 C2F6또는 C4F8등의 카본 'C'에 의해 다량의 폴리머를 발샹하여 식각시 질화막을 폴리머로 보호하는 개념이다. 그러나, 식가시 가스에 의한 폴리머 생성에는 한계가 있고 대부분의 폴리머 소스는 포토레지스트이다.In the etching process, a semiconductor device having a fine line width of 0.18 μm or less is used to introduce a SAC process instead of a direct contact in a contact process connecting a transistor and a capacitor. It is a concept of protecting the nitride film with a polymer by etching a large amount of polymer by carbon 'C' such as C 2 F 6 or C 4 F 8 as an anticorrosive formula. However, there is a limit to the production of polymers by gas upon eating and most polymer sources are photoresists.
그러나, 식각시 반도체 소자의 집적도가 증가함에 따라 원하지 않는 현상 즉, 포토레지스트의 변형(Deformation)에 의하여 포토레지스트에 의한 식각 대신에 하드마스크에 의한 식각의 필요성이 대두되었다. 따라서, 포토레지스트는 단지 매우 얇은 층의 하드마스크를 사용하는데 사용되고 그 후에는 정의된 하드마스크에 원하는 원하는 층의 식각이 필요하다. 그러나, SAC의 경우에는 전술한 바와 같이 질화막과 산화막의 선택비를 얻기가 힘들다.However, as the degree of integration of semiconductor devices increases during etching, an undesired phenomenon, that is, a need for etching by a hard mask instead of etching by a photoresist due to deformation of the photoresist has emerged. Thus, photoresists are only used to use very thin layers of hardmask and then the desired hardmask is required for etching the desired desired layer. However, in the case of SAC, it is difficult to obtain a selectivity ratio between the nitride film and the oxide film as described above.
상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 본 발명은, 자기정렬콘택 형성시 질화막과 산화막의 식각 선택비를 갖도록 하여 양호한 식각 프로파일을 얻을 수 있는 자기정렬콘택 형성 방법을 제공하는데 그 목적이 있다.The present invention proposed to solve the problems of the prior art as described above, has an etching selectivity of the nitride film and the oxide film when forming a self-aligned contact to provide a self-aligned contact forming method that can obtain a good etching profile. have.
도 1a 내지 도 1d는 본 발명의 일실시예에 따른 SAC 형성 공정을 도시한 단면도.1A to 1D are cross-sectional views illustrating a SAC forming process according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
10 : 기판 11 : 게이트전극10 substrate 11 gate electrode
12 : 게이트 하드마스크 13 : 스페이서12 gate hard mask 13 spacer
14 : 층간절연막 15 : 하드마스크14 interlayer insulating film 15 hard mask
16 : 포토레지스트 패턴 17 : 콘택홀16 photoresist pattern 17 contact hole
상기와 같은 문제점을 해결하기 위해 본 발명은, 이웃하는 다수의 도전패턴이 형성된 전체 구조 상부에 층간절연막을 형성하는 단계; 상기 절연막 상에 하드마스크용 절연막과 콘택 형성용 포토레지스트 패턴을 차례로 형성하는 단계; 상기 포토레지스트 패턴을 식각마스크로 해서 상기 절연막을 식각하여 하드마스크를 형성하는 단계; 상기 포토레지스트 패턴을 일부 제거하는 단계; 및 상기 잔류하는 포토레지스트 패턴을 폴리머 소스원으로 이용하며, 상기 하드마스크를 식각마스크로 해서 상기 층간절연막을 선택적으로 식각하여 상기 기판 표면을 노출시키는 콘택홀을 형성하는 단계를 포함하는 반도체 소자의 자기정렬콘택 형성 방법을 제공한다.In order to solve the above problems, the present invention includes the steps of forming an interlayer insulating film on the entire structure of the plurality of neighboring conductive patterns formed; Sequentially forming a hard mask insulating film and a contact forming photoresist pattern on the insulating film; Etching the insulating layer using the photoresist pattern as an etching mask to form a hard mask; Partially removing the photoresist pattern; And forming a contact hole exposing the surface of the substrate by selectively etching the interlayer insulating layer using the remaining photoresist pattern as a polymer source source and using the hard mask as an etch mask. A method of forming an alignment contact is provided.
본 발명은, SAC 형성시 하드마스크인 질화막과 층간절연용 산화막 간의 식각선택비를 억기 위하여 포토레지스트의 일부를 제거하는 공정을 실시하여 포토레지스트를 식각마스크가 아닌 단지 식각시 폴리머 소스로 사용함으로써, 양호한 식각 프로파일을 얻도록 하는 것을 기술적 특징으로 한다.According to the present invention, a part of the photoresist is removed to suppress the etching selectivity between the nitride film, which is a hard mask, and the interlayer insulating oxide film, when the SAC is formed. It is a technical feature to obtain a good etching profile.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 첨부한 도면을 참조하여 상세하게 설명하는 바, 도 1a 내지 도 1d는 본 발명의 일실시예에 따른 자기정렬콘택 형성 공정을 도시한 단면도이다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may more easily implement the present invention. 1D is a cross-sectional view illustrating a process of forming a self-aligned contact according to an embodiment of the present invention.
먼저 도 1a에 도시된 바와 같이, 반도체 소자를 이루기 위한 여러 요소가 형성된 기판(10) 상에 폴리실리콘과 텅스텐 실리사이드 등의 실리사이드가 적층된 다수의 게이트전극(11) 예컨대, 워드라인 또는 비트라인 등을 형성한다.First, as shown in FIG. 1A, a plurality of gate electrodes 11 in which silicides such as polysilicon and tungsten silicide are stacked on a substrate 10 on which various elements for forming a semiconductor device are formed, for example, a word line or a bit line To form.
즉, 기판(10)과 게이트전극(11)의 접촉 계면에 게이트 산화막(도시하지 않음)을 형성하며, 게이트전극(11) 상에 후속의 SAC 공정에 의한 게이트전극(11)의 손실을 방지하기 위한 질화막 등의 게이트 하드마스크(12)를 형성한다.That is, a gate oxide film (not shown) is formed at the contact interface between the substrate 10 and the gate electrode 11, and the loss of the gate electrode 11 is prevented by the subsequent SAC process on the gate electrode 11. A gate hard mask 12, such as a nitride film, is formed.
이어서, 게이트전극(11)을 포함한 기판 전면에 질화막 등의 스페이서용 절연막을 증착한 후 전면식각 공정을 통해 게이트전극(11) 측벽에 스페이서(13)를 형성한 다음, 전체 구조 상부에 예컨대, APL(Advanced Planarization Layer) 산화막, BPSG(Boro Phospho Silicate Glass), SOG(Spin On Glass) 또는 HDP(High Density Plasma) 산화막 등을 포함하는 층간절연용 절연막(14)을 형성한다.Subsequently, an insulating film for a spacer such as a nitride film is deposited on the entire surface of the substrate including the gate electrode 11, and then a spacer 13 is formed on the sidewall of the gate electrode 11 through an entire surface etching process. (Advanced Planarization Layer) An interlayer insulating film 14 including an oxide film, Boro Phospho Silicate Glass (BPSG), Spin On Glass (SOG), or High Density Plasma (HDP) oxide film is formed.
구체적으로, 스페이서용 절연막은 50Å ∼ 500Å의 두께로 증착하며, 전면식각시 20mTorr ∼ 50mTorr의 압력과 300W ∼ 800W의 파워를 유지하며, CHF3/CF4/Ar 등의 식각가스를 이용한다.Specifically, the insulating film for spacers is deposited to a thickness of 50 kPa to 500 kPa, and maintains a pressure of 20 mTorr to 50 mTorr and a power of 300 W to 800 W when etching the entire surface, and uses an etching gas such as CHF 3 / CF 4 / Ar.
이어서, 절연막(14) 상에 질화막을 포함하는 물질막을 이용하여 하드마스크용 절연막(15')을 10nm ∼ 150nm의 두께로 증착한 다음, 그 상부에 포토레지스트를 도포한 다음, 소정의 노광원을 이용한 사진식각 공정을 통해 포토레지스트 패턴(16')을 형성한다.Subsequently, a hard mask insulating film 15 'is deposited to a thickness of 10 nm to 150 nm using a material film including a nitride film on the insulating film 14, and then a photoresist is applied thereon, and then a predetermined exposure source is applied. The photoresist pattern 16 ′ is formed through the photolithography process.
구체적으로, 절연막(15') 상에 포토레지스트를 소정의 두께가 되도록 도포한 다음, 소정의 노광원(도시하지 않음)과 소정의 레티클(도시하지 않음)을 이용하여 포토레지스트의 소정 부분을 선택적으로 노광하고, 현상 공정을 통해 노광 공정을통해 노광되거나 혹은 노광되지 않은 부분을 잔류시킨 다음, 후세정 공정 등을 통해 식각 잔유물 등을 제거함으로써 포토레지스트 패턴(16')을 형성한다.Specifically, the photoresist is coated to a predetermined thickness on the insulating film 15 ', and then a predetermined portion of the photoresist is selectively selected using a predetermined exposure source (not shown) and a predetermined reticle (not shown). The photoresist pattern 16 ′ is formed by exposing the photoresist to the photoresist layer, leaving the exposed or unexposed portion through the developing process, and then removing the etch residue through a post-cleaning process or the like.
다음으로 도 1에 도시된 바와 같이, 기판(10)의 온도를 적당히 조절하며 포토레지스트 패턴(16')을 식각마스크로 해서 절연막(15')을 선택적으로 식각하여 하드마스크(15)를 형성하며 이 때, CD의 넓어짐(Widending)은 물론 포토레지스트의 변형이 거의 발생하지 않는 실험상의 테스트 결과를 나타내는 SF6또는 CF4/CHF3가스를 이용한 플라즈마 식각 조건을 이용하는 바, 이 때 포토레지스트 패턴(16')의 변형은 거의 일어나지 않는다.Next, as shown in FIG. 1, the temperature of the substrate 10 is appropriately adjusted, and the insulating film 15 ′ is selectively etched using the photoresist pattern 16 ′ as an etch mask to form a hard mask 15. At this time, the plasma etching conditions using SF 6 or CF 4 / CHF 3 gas, which shows experimental test results of hardening of photoresist as well as CD widening, are used. 16 ') hardly occurs deformation.
다음으로 도 1c에 도시된 바와 같이, 포토레지스트 패턴(16')을 일부 제거하는 공정 즉, 디스컴(De-scum) 공정을 실시하여 포토레지스트 패턴(16)이 후속 공정시 식각마스크로서의 역할을 하지 못하고 단지 폴리머를 발생시키는 소스원으로서의 역할을 한다.Next, as shown in FIG. 1C, a process of removing a portion of the photoresist pattern 16 ′, that is, a descum process, is performed so that the photoresist pattern 16 serves as an etching mask in a subsequent process. It simply does not act as a source source for generating polymers.
다음으로, 도 1d에 도시된 바와 같이 하드마스크(15)를 식각마스크로 하여 절연막(14)을 식각하여 기판 (10) 표면을 노출시키는 콘택홀(17)을 형성하는 바, 통상의 SAC 공정이 이루어지며, 이 때 포토레지스트 패턴(16)은 폴리머를 발생시키는 소스원으로서 작용하므로 식각 프로파일을 향상시킬 수 있게 된다.Next, as illustrated in FIG. 1D, the contact hole 17 exposing the surface of the substrate 10 is formed by etching the insulating layer 14 using the hard mask 15 as an etching mask. In this case, the photoresist pattern 16 acts as a source source for generating the polymer, thereby improving the etching profile.
구체적으로, 기판(10)의 온도를 적절히 유지하여 실시하며, C4F6, C4F8또는 C5F8등의 가스를 이용하여 식각공정을 실시하며, 전술한 주식각가스에 O2또는 Ar의 식각가스를 더 첨가하여 식각 프로파일과 안정성을 확보하도록 하는 바, 주식각가스와 상기 O2를 1.5:1 ∼ 2.0:1의 비율로 사용하는 것이 바람직하다.Specifically, the temperature of the substrate 10 is properly maintained, and the etching process is performed using a gas such as C 4 F 6 , C 4 F 8, or C 5 F 8 , and O 2 is applied to the above-described stock angle gas. Or to further add an etching gas of Ar to secure the etching profile and stability, it is preferable to use the stock angle gas and the O 2 in a ratio of 1.5: 1 to 2.0: 1.
여기서, 식각 타겟 선정은 게이트전극(11), 여기서는 게이트 하드마스크(12) 상에 형성된 절연막(14)의 두께를 고려하여 결정한다.Here, the etching target selection is determined in consideration of the thickness of the insulating film 14 formed on the gate electrode 11, in this case, the gate hard mask 12.
계속해서, 세정 공정을 통해 전술한 SAC 공정시 발생한 부산물을 제거한 다음, 절연막(14) 표면이 노출될 때까지 평탄화 공정을 실시한다.Subsequently, the by-products generated in the above-described SAC process are removed through the cleaning process, and then the planarization process is performed until the surface of the insulating film 14 is exposed.
전술한 본 발명은, SAC 공정시 포토레지스트 패턴을 일부 제거하여 식각마스크가 아닌 폴리머 소스원으로 사용함으로써, SAC 공정시 식각 프로파일을 양호하게 할 수 있음을 실시예를 통해 알아 보았다.The present invention described above, through the embodiment was found that by removing a portion of the photoresist pattern in the SAC process to use as a polymer source source rather than an etching mask, it is possible to improve the etching profile during the SAC process.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
상술한 바와 같은 발명은, 자기정렬콘택 형성시 양호한 식각 프로파일을 얻을 수 있어 후속 공정에 따른 공정 마진을 확보할 수 있을 뿐만아니라 소자의 불량 발생을 줄여, 궁극적으로 반도체 소자의 수율을 향상시킬 수 있는 탁월한 효과를기대할 수 있다.According to the above-described invention, it is possible to obtain a good etching profile when forming a self-aligned contact, thereby securing process margins according to subsequent processes, reducing defects of the device, and ultimately improving semiconductor device yield. You can expect an excellent effect.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7741174B2 (en) | 2007-01-30 | 2010-06-22 | Samsung Electronics Co., Ltd. | Methods of forming pad structures and related methods of manufacturing recessed channel transistors that include such pad structures |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7741174B2 (en) | 2007-01-30 | 2010-06-22 | Samsung Electronics Co., Ltd. | Methods of forming pad structures and related methods of manufacturing recessed channel transistors that include such pad structures |
| US7936012B2 (en) | 2007-01-30 | 2011-05-03 | Samsung Electronics Co., Ltd. | Recessed channel transistors that include pad structures |
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