KR20030053217A - Method for forming dual gate electrode - Google Patents
Method for forming dual gate electrode Download PDFInfo
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- KR20030053217A KR20030053217A KR1020010083286A KR20010083286A KR20030053217A KR 20030053217 A KR20030053217 A KR 20030053217A KR 1020010083286 A KR1020010083286 A KR 1020010083286A KR 20010083286 A KR20010083286 A KR 20010083286A KR 20030053217 A KR20030053217 A KR 20030053217A
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
Abstract
Description
본 발명은 반도체장치의 형성 방법에 관한 것으로, 보다 구체적으로, 듀얼 게이트를 이용한 게이트 전극 형성 방법에 관한 것이다.The present invention relates to a method of forming a semiconductor device, and more particularly, to a method of forming a gate electrode using a dual gate.
저전압 풀씨모스(full CMOS) 에스램(SRAM)을 구현하기 위하여 표면 채널(surface channel) pMOS가 필요하다. 표면 채널 pMOS를 형성하기 위해서는 듀얼 게이트 전극를 사용하여야 한다. 이때, nMOS는 인(phosphor) 등의 n타입 도판트(dopant)가 도핑된 다결정 실리콘층을 사용하여야 하며, pMOS는 붕소(boron) 등의 p타입 도판트(dopant)가 도핑된 다결정 실리콘층을 사용하여야 한다.Surface channel pMOS is needed to implement low voltage full CMOS SRAM. Dual gate electrodes must be used to form the surface channel pMOS. In this case, the nMOS should use a polycrystalline silicon layer doped with n-type dopant such as phosphor, and the pMOS should be a polycrystalline silicon layer doped with p-type dopant such as boron. Should be used.
일반적으로 다결정 실리콘층은 도핑되는 도판트가 상기 n타입이냐 또는 p타입이냐에 따라 식각 속도가 많이 달라진다. 즉, n타입의 도판트에 의해 도핑된 다결정 실리콘층이 가장 식각 속도가 빠르고, 그 다음 p타입의 도판트에 의해 도핑된 다결정 실리콘층과 도판트가 도핑되지 않은 다결정 실리콘층 순으로 식각 속도가 결정된다.In general, the etching rate of the polycrystalline silicon layer varies greatly depending on whether the dopant to be doped is n type or p type. That is, the polycrystalline silicon layer doped with the n-type dopant has the highest etching rate, followed by the polycrystalline silicon layer doped with the p-type dopant and the polycrystalline silicon layer without the dopant doped. Is determined.
풀 씨모스 에스램의 셀은 2개의 pMOS와 4개의 nMOS로 이루어져 있으며, 주변회로(peripheral) 역시 pMOS와 nMOS로 이루어져 있다. 일반적으로 식각 공정에 서 패턴 밀도가 조밀한 셀지역과 패턴이 성긴 주변지역 간에 식각비 차이가 발생하며 이를 로딩 효과(loading effect)라 한다. 따라서, 식각 공정 시 항상 발생하는 로딩 효과에 덧붙여서 듀얼 게이트 전극는 pMOS와 nMOS의 식각속도 차이가 발생되므로 공정이 매우 어렵다.The full CMOS SRAM cell consists of two pMOS and four nMOS, and the peripheral circuit is also composed of pMOS and nMOS. In general, in the etching process, there is a difference in etching ratio between a cell region with a dense pattern density and a region with a sparse pattern, which is called a loading effect. Therefore, in addition to the loading effect that always occurs during the etching process, the dual gate electrode is very difficult because the etching rate difference between the pMOS and nMOS occurs.
실제 식각속도가 가장 느린 셀 지역의 pMOS는 다결정 실리콘 잔류물이 발생하고, 식각 속도가 가장 빠른 주변영역의 nMOS는 기판이 손상된다.The pMOS in the cell region with the lowest etch rate generates polycrystalline silicon residue, and the nMOS in the peripheral region with the fastest etch rate damages the substrate.
따라서, 게이트 식각 이전에 열공정을 진행하여 도판트의 활성(activation)을 조절하면 pMOS와 nMOS 간의 식각 속도 차를 줄일 수 있다.Therefore, by adjusting the activation of the dopant by performing a thermal process before the gate etching, it is possible to reduce the etching rate difference between the pMOS and the nMOS.
도 1은 종래 기술에 따른 듀얼 게이트 전극 형성을 보인 공정순서도이다.1 is a process flowchart showing the formation of a dual gate electrode according to the prior art.
그리고 도 2a 내지 도 2b는 종래 기술에 따른 듀얼 게이트 전극 식각 결과를 보인 도면으로, 도 2a는 주변영역의 nMOS 게이트 전극을 도시한 것이고, 도 2b는 셀영역의 pMOS 게이트 전극을 도시한 것이다.2A and 2B illustrate a result of etching a dual gate electrode according to the prior art, in which FIG. 2A illustrates an nMOS gate electrode in a peripheral region, and FIG. 2B illustrates a pMOS gate electrode in a cell region.
종래 기술에 따른 듀얼 게이트 전극 형성방법은, 도 1에 도시된 바와 같이,먼저 반도체기판 상에 소자격리 공정 및 웰 형성용 도판트 도핑 공정을 차례로 진행하여 각각의 소자격리막 및 웰을 형성한다.In the method of forming a dual gate electrode according to the related art, as shown in FIG. 1, a device isolation process and a dopant doping process for forming a well are sequentially performed on a semiconductor substrate to form respective device isolation films and wells.
이어, 소자격리막 및 웰을 포함한 기판 상에 유전 산화막(SiO2)과 게이트 전극 형성용 도판트가 도핑되지 않은 다결정 실리콘층을 차례로 증착한 다음, pMOS 형성영역을 덮고 nMOS 형성영역의 다결정 실리콘층에 n타입의 도판트를 도핑하고 다시 nMOS 형성영역을 덮고 pMOS 형성영역의 다결정 실리콘층에 p타입의 도판트를 도핑한다.Subsequently, a dielectric oxide film (SiO 2 ) and a doped polycrystalline silicon layer doped with a gate electrode dopant are sequentially deposited on the substrate including the device isolation layer and the well, and then cover the pMOS formation region and the polycrystalline silicon layer of the nMOS formation region. The n-type dopant is doped, the n-type dopant is covered again, and the p-type dopant is doped in the polycrystalline silicon layer of the pMOS-forming region.
그 다음, 상기 각각의 도판트가 도핑된 다결정 실리콘층 상에 실리콘 질화막을 증착한다. 이때, 상기 실리콘 질화막은 얇은 막질을 얻기 위해 저압화학기상증착(Low Pressure Chemical Vapor Deposition) 방식으로 증착한다. 또한, 상기 실리콘 질화막의 증착 온도가 650℃ 이상되면 nMOS 게이트 전극은 전기적으로 활성화되지만 pMOS 게이트 전극은 비활성화된 상태이다. 따라서, 전기적으로 활성화된 셀지역의 nMOS 게이트 전극과 전기적으로 활성화되지 않은 주변영역의 pMOS 게이트 전극은 식각 속도 차이가 발생되므로 상기 실리콘 질화막은 650℃ 이하의 온도에서 증착하여야 한다.Then, a silicon nitride film is deposited on each of the dopant doped polycrystalline silicon layers. At this time, the silicon nitride film is deposited by a low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition) method to obtain a thin film quality. In addition, when the deposition temperature of the silicon nitride film is 650 ° C. or more, the nMOS gate electrode is electrically activated, but the pMOS gate electrode is inactivated. Therefore, since the etching rate difference occurs between the nMOS gate electrode of the electrically activated cell region and the pMOS gate electrode of the peripheral region that is not electrically activated, the silicon nitride film should be deposited at a temperature of 650 ° C. or less.
상기 실리콘 질화막은 이 후의 게이트 전극 재산화 공정 진행 시 게이트 전극 탑부분에 발생되는 이상(abnormal)산화를 방지하는 산화방지막 역할을 한다.The silicon nitride film serves as an anti-oxidation film to prevent abnormal oxidation that occurs at the top portion of the gate electrode during the subsequent gate electrode reoxidation process.
이 후, 게이트 전극 형성용 마스크를 이용하여 상기 각각의 도판트가 도핑된 다결정 실리콘층을 식각하여 게이트 전극을 형성한다. 이어, 상기 게이트 전극 식각 공정 시 발생한 식각 데미지(damage)를 제거하기 위해 게이트 전극 재산화 공정을 실시한다.Thereafter, the polycrystalline silicon layer doped with each dopant is etched using a mask for forming a gate electrode to form a gate electrode. Subsequently, a gate electrode reoxidation process is performed to remove etch damage generated during the gate electrode etching process.
그러나, 종래 기술에서는 셀지역의 nMOS 게이트 전극 및 주변영역의 pMOS 게이트 전극 형성 시, 도 2a 및 도 2b에 도시된 바와 같이, 식각 속도가 비교적 빠른 셀지역의 nMOS 게이트 전극을 기준으로 하여 식각 타겟(target)을 정하면 주변영역의 pMOS 다결정 실리콘층이 완전히 식각되지 않아 다결정 실리콘 잔류물이 발생하며, 식각 속도가 비교적 느린 pMOS 게이트 전극을 기준으로 식각 타겟을 정하면 주변영역의 nMOS 다결정 실리콘층이 과도하게 식각되어 기판이 손상되는 문제점이 발생되었다.However, in the related art, when forming the nMOS gate electrode in the cell region and the pMOS gate electrode in the peripheral region, as shown in FIGS. 2A and 2B, an etching target ( target), the pMOS polycrystalline silicon layer in the peripheral region is not completely etched, resulting in polycrystalline silicon residue.If the etch target is determined based on the pMOS gate electrode with a relatively slow etching rate, the nMOS polycrystalline silicon layer in the peripheral region is excessively etched. This caused a problem of damage to the substrate.
이에 따라, 본 발명은 상기과 같은 문제점을 해결하기 위해 안출된 것으로, 셀지역의 nMOS 게이트 전극 및 주변영역의 pMOS 게이트 전극 간의 식각 속도 차이를 억제할 수 있는 듀얼 게이트 전극 형성 방법을 제공하는데에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a dual gate electrode capable of suppressing an etching rate difference between an nMOS gate electrode in a cell region and a pMOS gate electrode in a peripheral region. There is this.
도 1은 종래 기술에 따른 듀얼 게이트 전극 형성을 보인 공정순서도.1 is a process flowchart showing the formation of a dual gate electrode according to the prior art.
도 2a 내지 도 2b는 종래 기술에 따른 듀얼 게이트 전극 식각 결과를 보인 도면.2A to 2B illustrate a dual gate electrode etching result according to the related art.
도 3는 본 발명에 따른 듀얼 게이트 전극 형성을 보인 공정순서도.Figure 3 is a process flowchart showing the formation of a dual gate electrode according to the present invention.
도 4a 내지 도 4b는 본 발명에 따른 듀얼 게이트 전극 식각결과를 보인 도면.4A to 4B are diagrams illustrating results of etching dual gate electrodes according to the present invention.
상기와 같은 문제점을 해결하기 위한 본 발명의 듀얼 게이트 전극 형성방법은 nMOS 형성영역 및 pMOS 형성영역이 정의된 반도체기판 상에 소자격리막 및 웰을 형성하는 단계와, 결과물 상에 게이트 전극 형성용 실리콘층 및 산화방지막을 차례로 형성하는 단계와, 실리콘층의 nMOS 형성영역 및 pMOS 형성영역에 각각의 n타입 및 p타입 도판트를 도핑하는 단계와, 산화방지층 및 도핑된 실리콘층을 식각하여 각각의 nMOS 게이트 전극 및 pMOS 게이트 전극을 형성하는 단계를 포함한 것을 특징으로 한다.The dual gate electrode forming method of the present invention for solving the above problems is to form a device isolation film and a well on a semiconductor substrate in which the nMOS formation region and the pMOS formation region defined, and the silicon layer for forming a gate electrode on the resultant And sequentially forming an anti-oxidation film, doping n-type and p-type dopants into the nMOS forming region and the pMOS forming region of the silicon layer, and etching each of the nMOS gates by etching the antioxidant layer and the doped silicon layer. Forming an electrode and a pMOS gate electrode.
(실시예)(Example)
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 3는 본 발명에 따른 듀얼 게이트 전극 형성을 보인 공정순서도이다. 그리고 도 4a 내지 도 4b는 본 발명에 따른 듀얼 게이트 전극 식각결과를 보인 도면으로, 도 4a는 주변영역의 nMOS 게이트 전극의 식각 양상을 도시한 것이고, 도 2b는 셀영역의 pMOS 게이트 전극의 식각 양상을 도시한 것이다.3 is a process flowchart showing the formation of a dual gate electrode according to the present invention. 4A to 4B illustrate a result of etching dual gate electrodes according to the present invention. FIG. 4A illustrates an etching pattern of an nMOS gate electrode in a peripheral region, and FIG. 2B illustrates an etching pattern of a pMOS gate electrode in a cell region. It is shown.
본 발명의 듀얼 게이트 전극 형성방법은, 도 3에 도시된 바와 같이, pMOS 형성영역과 nMOS 형성영역이 정의된 반도체기판에 소자격리막 형성 공정, 웰 형성 공정, 유전 산화막(SiO2) 형성 공정 및 게이트 전극 형성용 도판트가 도핑되지 않은 비정질 또는 다결정 실리콘층 증착 공정을 각각 진행한다.In the method of forming a dual gate electrode of the present invention, as shown in FIG. 3, an isolation layer forming process, a well forming process, a dielectric oxide film (SiO 2 ) forming process, and a gate are formed on a semiconductor substrate on which a pMOS forming region and an nMOS forming region are defined. The amorphous or polycrystalline silicon layer deposition process in which the dopant for forming an electrode is not doped is performed, respectively.
이어, 상기 게이트 전극 형성용 도판트가 도핑되지 않은 비정질 또는 다결정 실리콘층 상에 실리콘 질화막을 증착한다. 이때, 상기 실리콘 질화막은 n타입 또는 p타입의 도판트 분포에 영향을 주지 않을 정도로 얇은 막질을 얻기 위해서 저압화학기상증착 방법으로 30∼100Å 두께로 증착된다. 또한, 상기 실리콘 질화막의 증착 온도가 650℃ 이상되면 nMOS 게이트 전극은 전기적으로 활성화되지만 pMOS 게이트 전극은 비활성화된 상태이다. 따라서, 전기적으로 활성화된 셀지역의 nMOS 게이트 전극과 전기적으로 활성화되지 않은 주변영역의 pMOS 게이트 전극은 식각 속도 차이가 발생되므로 상기 실리콘 질화막은 650℃ 이하의 온도에서 증착하여야 한다.Subsequently, a silicon nitride film is deposited on the amorphous or polycrystalline silicon layer which is not doped with the gate electrode forming dopant. At this time, the silicon nitride film is deposited to a thickness of 30 ~ 100Å by a low pressure chemical vapor deposition method in order to obtain a thin film so as not to affect the dopant distribution of the n-type or p-type. In addition, when the deposition temperature of the silicon nitride film is 650 ° C. or more, the nMOS gate electrode is electrically activated, but the pMOS gate electrode is inactivated. Therefore, since the etching rate difference occurs between the nMOS gate electrode of the electrically activated cell region and the pMOS gate electrode of the peripheral region that is not electrically activated, the silicon nitride film should be deposited at a temperature of 650 ° C. or less.
그 다음, 상기 도판트가 도핑되지 않은 비정질 또는 다결정 실리콘층의 pMOS 형성영역을 덮고 nMOS 형성영역에 n타입의 도판트를 도핑하고 나서, 다시 nMOS 형성영역을 덮고 pMOS 형성영역에 p타입의 도판트를 도핑한다. 이때, 상기 n타입 도판트로는 P 또는 As 중 어느 하나를 사용하고, 상기 p타입 도판트로는 B를 사용한다.Next, the dopant covers the pMOS formation region of the undoped amorphous or polycrystalline silicon layer and the nMOS formation region is doped with an n type dopant, and then covers the nMOS formation region and the pMOS formation region is a p type dopant. Doping In this case, either the P or As is used as the n-type dopant, and B is used as the p-type dopant.
이 후, 게이트 전극 형성용 마스크를 이용하여 상기 산화방지막 및 n타입 또는 p타입의 도판트가 도핑된 다결정 실리콘층을 식각하여 게이트 전극을 형성한다. 이때, 상기 산화방지막은 이 후의 게이트 전극 재산화 공정 진행 시 게이트 전극 탑부분에 발생되는 이상 산화를 방지하는 역할을 할 뿐만 아니라 상기 식각 공정 시, 도 4a 및 도 4b에 도시된 바와 같이, nMOS 및 pMOS 게이트 전극의 식각 속도 차이를 줄이는 역할을 한다. 또한, 상기 nMOS 게이트 전극 및 pMOS 게이트 전극 형성 공정 시,식각가스로 Cl2, Cl2/O2, HBr/O2또는 HBr/Cl2/O2중 어느 하나를 사용한다. 그리고 식각장비로는 ICP(Inductively Coupled Plasma)타입 또는 ECR(Electron Cyclotron Resonance)타입을 사용한다.Thereafter, the gate electrode is formed by etching the anti-oxidation film and the polycrystalline silicon layer doped with the n-type or p-type dopant using a gate electrode forming mask. In this case, the anti-oxidation film not only serves to prevent abnormal oxidation occurring at the top portion of the gate electrode during the subsequent gate electrode reoxidation process, and as illustrated in FIGS. 4A and 4B during the etching process, nMOS and It serves to reduce the etching rate difference of the pMOS gate electrode. In the nMOS gate electrode and pMOS gate electrode forming process, any one of Cl 2 , Cl 2 / O 2 , HBr / O 2, or HBr / Cl 2 / O 2 is used as an etching gas. In addition, ICP (Inductively Coupled Plasma) type or ECR (Electron Cyclotron Resonance) type is used.
이어, 상기 게이트 전극 식각 공정 시 발생한 식각 데미지를 제거하기 위해 게이트 전극 재산화 공정을 실시한다.Subsequently, a gate electrode reoxidation process is performed to remove etch damage generated during the gate electrode etching process.
본 발명에 따른 다른 실시예로는, 반도체기판에 소자격리 공정, 웰 형성용도판트 도핑 공정, 유전 산화막(SiO2) 형성 공정, 게이트 전극 형성용 도판트가 도핑되지 않은 비정질 또는 다결정 실리콘층 증착 공정 및 n타입의 도판트 및 p타입의 도판트 도핑 공정을 모두 진행한 후, 상기 결과물 상에 산화방지막 역할을 하는 실리콘 질화막을 증착한다. 상기 실리콘 질화막은 플라즈마 강화 화학기상증착(Plasma Enhanced Chemical Vapor Deposition) 방법으로 100∼1000Å 두께로 증착한다. 이는 상기 플라즈마 강화 화학기상증착 방법의 증착 온도가 450℃ 이하로, p타입 또는 n타입의 도판트를 활성화시키지 않으므로 결과적으로, pMOS 또는 nMOS 게이트 전극 간의 식각속도 차이가 발생되지 않기 때문이다. 상기 실리콘 질화막 증착 공정은 450∼500℃ 온도에서 진행한다.According to another embodiment of the present invention, a device isolation process, a dopant doping process for forming a well, a dielectric oxide film (SiO 2 ) forming process, an amorphous or polycrystalline silicon layer deposition process without a dopant for forming a gate electrode is formed on a semiconductor substrate. And n-type dopant and p-type dopant doping process, and then a silicon nitride film serving as an antioxidant film is deposited on the resultant. The silicon nitride film is deposited to a thickness of 100 ~ 1000Å by the plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition) method. This is because the deposition temperature of the plasma enhanced chemical vapor deposition method is 450 ° C. or less, and thus do not activate a p-type or n-type dopant, and as a result, there is no difference in etching rate between pMOS or nMOS gate electrodes. The silicon nitride film deposition process is performed at a temperature of 450 ~ 500 ℃.
이어, 게이트 전극 형성용 마스크를 이용하여 상기 n 또는 p타입의 도판트가 도핑된 다결정 실리콘층을 식각하여 게이트 전극을 형성한 후, 게이트 전극 재산화 공정을 실시한다.Subsequently, a gate electrode is formed by etching the polycrystalline silicon layer doped with the n or p type dopant using a gate electrode forming mask, and then performing a gate electrode reoxidation process.
이상에서 자세히 설명한 바와같이, 본 발명에서는 nMOS 및 pMOS 게이트 전극 형성용 실리콘층을 증착한 후에 상기 실리콘층 상에 산화방지막을 증착함으로써, nMOS 및 pMOS 게이트 전극의 식각 속도 차이를 줄일 수 있으며, 이를 통해 듀얼 게이트 전극 식각 공정 마진을 확보할 수 있다.As described in detail above, in the present invention, by depositing an oxide layer on the silicon layer after depositing the silicon layer for forming the nMOS and pMOS gate electrode, it is possible to reduce the difference in etching rates of the nMOS and pMOS gate electrode, Dual gate electrode etching process margin can be secured.
기타, 본 발명의 요지에 벗어나지 않는 범위내에서 다양하게 변결하여 실시할 수 있다.In addition, it can carry out in various ways within the range which does not deviate from the summary of this invention.
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