KR100897817B1 - Method for Structuring Gate Of Semiconductor Device - Google Patents

Abstract

The present invention relates to a method of forming a gate of a semiconductor device, in particular, when forming a dual gate of a complementary metal oxide semi-conductor (CMOS) semiconductor device, an oxide film of a specific gate due to an etching rate that depends on the doping material and the doping concentration of the gate. And a method for preventing the active area from being damaged.

In the method of forming a gate of a semiconductor device according to the present invention, the step of sequentially forming a gate oxide film and a gate silicon film on a semiconductor substrate on which the N-Gate and P-Gate active regions are formed, and forming an additional deposition prevention film on the gate silicon film Thereafter, forming a photoresist pattern that separates the N-Gate and P-Gate regions, removing an oxide layer of the N-Gate region, and further depositing gate silicon on the N-Gate region from which the oxide layer is removed. And removing the photoresist pattern and the oxide layer remaining in the P-Gate region and forming a silicon gate on the substrate resultant.

CMOS, Dual Gate, SEG, Semiconductor Devices,

Description

Method for forming gate of semiconductor device {Method for Structuring Gate Of Semiconductor Device}

1a to 1b is a view showing the difference in etching rate according to the doping element and the concentration of N-Gate and P-Gate according to the prior art.

2a to 2b is a view showing the degree of damage of the gate oxide film of N-Gate and P-Gate according to the prior art.

3A to 3D are cross-sectional views illustrating a method of forming a dual gate of a semiconductor device in accordance with an embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a gate of a semiconductor device, and more particularly to a method for forming a dual gate of a CMOS semiconductor device.

Recently, as semiconductor devices have been highly integrated, methods for reducing gate line width, which are most closely related to the high integration of semiconductor devices, have been proposed.

In the gate line width reduction technology, a method of reducing the resistance of the gate by doping the gate through ion implantation or the like before the gate etching is used.

In particular, a semiconductor device using a complementary metal-oxide semiconductor (MOS) is formed of a dual gate structure doped with N-type and P-type, respectively.

Hereinafter, with reference to the accompanying drawings will be described the difference in the etching rate and gate oxide film N-Gate and P-Gate according to the prior art.

1a to 1b is a view showing the difference in etching rate according to the doping element and the concentration of the N-Gate and P-Gate according to the prior art.

Figure 1a shows the difference in etching rate according to the doping element and the doping concentration of N-Gate, Figure 1b shows the difference in etching rate according to the doping element and doping concentration of the P-Gate.

Comparing FIGS. 1A and 1B, it can be seen that the etching rate of the N-Gate region is much faster than that of the P-Gate region.

2a to 2b are views showing the damage degree of the gate oxide film of N-Gate and P-Gate according to the prior art.

Figure 2a shows the degree of damage to the gate oxide film of the N-Gate, Figure 2b shows the degree of damage to the gate oxide film of the N-Gate.

Comparing FIG. 2A and FIG. 2B, it can be seen that the damage level of the gate oxide film in the N-Gate region is much greater than that of the gate oxide film in the P-Gate region.

Therefore, when the two gates are etched at the same time, the difference in etching speed is large according to the doping element and the doping concentration. In addition, the active of the N-Gate region having a high etching rate is easily damaged by a thin gate oxide film.

SUMMARY OF THE INVENTION An object of the present invention has been made in view of the above-described problems, and particularly, when forming a dual gate of a semiconductor device, an oxide film and an active region of a specific gate are prevented from being damaged due to an etching rate that depends on the doping material and the doping concentration of the gate. It is to provide a method for doing so.

According to an aspect of the present invention, there is provided a method of forming a gate of a semiconductor device, the method including sequentially forming a gate oxide film and a gate silicon film on a semiconductor substrate on which N-Gate and P-Gate active regions are formed, After forming a further deposition prevention film on the gate silicon film, forming a photoresist pattern for separating the N-Gate and P-Gate region, by using the photosensitive film pattern to remove the additional deposition prevention film of the N-Gate region The method may further include: depositing gate silicon on the N-gate region from which the additional deposition prevention film has been removed, removing the photoresist pattern and the additional deposition prevention layer remaining on the P-gate region, and including the additional deposition gate silicon. And partially etching the gate silicon film.

More preferably, the additional deposition prevention film comprises an oxide film, a nitride film or a nitride oxide film.

More preferably, the additional deposition preventing film is removed through a wet etching process, and the material used for the wet etching includes hydrofluoric acid, acetic acid, and phosphoric acid.

More preferably, the gate silicon of the N-Gate region is additionally deposited through a selective epitaxial growth of silicon (SEG) process.

More preferably, the gate silicon of the N-Gate region is further deposited to a thickness of 50 to 300 kHz.

More preferably, further comprising the step of annealing at a temperature of about 200 to 1300 ℃ after further depositing the gate silicon in the N-Gate region.

Hereinafter, with reference to the accompanying drawings illustrating the configuration and operation of the embodiment of the present invention, the configuration and operation of the present invention shown in the drawings and described by it will be described by at least one embodiment, By the technical spirit of the present invention described above and its core configuration and operation is not limited.

3A to 3D are cross-sectional views illustrating a method of forming a dual gate of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 3A, an additional deposition prevention layer 3 is formed on a semiconductor substrate (not shown) on which N-Gate and P-Gate active regions are formed, in which a gate oxide layer 1 and a gate silicon layer 2 are sequentially deposited. Form. The additional deposition prevention film (3) is made of an oxide film, a nitride film or a nitride oxide film.

Subsequently, after the photoresist film is applied to the entire upper surface of the additional deposition prevention film 3, a pattern for distinguishing the N-Gate and P-Gate areas is masked, and photo-lithography is performed to form the photoresist pattern 4. To form.

Thereafter, as illustrated in FIG. 3B, etching is performed on the entire upper surface of the formed photoresist pattern 4 to remove the additional deposition preventing film 3 of the N-Gate region. In this case, the additional deposition prevention film 3 is removed through a wet etching process, and materials used for the wet etching include hydrofluoric acid, acetic acid, phosphoric acid, and the like.

For example, when the additional deposition prevention film 3 is an oxide film, the hydrofluoric acid and acetic acid are used as an etching material, and when the additional deposition prevention film 3 is a nitride film, the phosphoric acid is used as an etching material. In addition, when the additional deposition prevention film 3 is a nitric oxide film, a predetermined amount of the hydrofluoric acid and phosphoric acid is mixed and used.

The gate silicon 5 is further deposited on the N-gate region from which the additional deposition prevention film 3 is removed.

In this case, the gate silicon 5 is formed to have a thickness of 50 kHz to 300 Å, and is further deposited through a selective epitaxial growth of silicon (SEG) process.

The SEG is a selective single crystal silicon thin film growth technology, in which silicon is not grown in an insulating layer, and only silicon is selectively grown in a portion in which a silicon substrate is exposed in a state in which crystal orientation is maintained.

delete

After further depositing the gate silicon 5, an annealing process is further performed to maintain the same crystal state between the additionally deposited gate silicon 5 and the lower gate silicon film 2. The annealing process is to stabilize the etching process to be carried out later, it is made at a temperature of 200 ℃ to 1300 ℃.

Thereafter, as shown in FIG. 3C, the photoresist pattern 4 and the additional deposition prevention layer 3 remaining in the P-Gate region are simultaneously removed through a dry etching process. After the gate silicon 5 is further deposited on the N-gate region, a pattern is formed using a gate mask, and the gate silicon layer 2 is partially etched according to the pattern.

delete

At this time, the etching speed according to the doping element and the doping concentration is fast, it can be seen that the amount of gate silicon remaining in the N-Gate region where the gate silicon 5 is additionally deposited and the P-Gate region without additional deposition.

3D shows that the etching is completed, and even though the gate oxide layer 1 of the N-gate region is removed through the etching, a profile without active damage can be secured.

Therefore, by further depositing the gate oxide film in the N-Gate region in advance, the etching degree which varies for each gate according to the doping element and the doping concentration can be compensated for in the subsequent etching process.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

As described above, the present invention has an effect of preventing damage to the oxide film and the active region due to the etching rate in advance by additionally depositing silicon on a specific gate when forming the dual gate.

Claims (6)

Sequentially forming a gate oxide film and a gate silicon film on a semiconductor substrate having N-Gate and P-Gate active regions formed thereon; Forming an additional photoresist layer on the gate silicon layer, and then forming a photoresist pattern that separates the N-Gate and P-Gate regions; Removing the additional deposition prevention film of the N-Gate region by using the photoresist pattern; Depositing additional gate silicon on the N-gate region from which the additional deposition prevention film is removed; Removing the photoresist pattern and the additional deposition preventing film remaining in the P-Gate region; And And partially etching the gate silicon film including the additionally deposited gate silicon. The method of claim 1, The additional deposition preventing film comprises a oxide film, a nitride film or a nitride oxide film forming method of the semiconductor device, characterized in that. The method of claim 1, The additional deposition prevention layer is removed through a wet etching process, the material used for the wet etching method of forming a gate of the semiconductor device, characterized in that it comprises any one of hydrofluoric acid, acetic acid and phosphoric acid. The method of claim 1, The gate silicon of the N-Gate region is further deposited through a selective epitaxial growth of silicon (SEG) process. The method of claim 1, The gate silicon of the N-Gate region is additionally deposited to a thickness of 50 to 300Å thickness gate method of a semiconductor device. The method of claim 1, And further annealing at 200 to 1300 ° C. after further depositing gate silicon on the N-Gate region.

Images