KR100772262B1 - Method for manufacturing non-salicidation film of semiconductor device - Google Patents

Abstract

A method for manufacturing a non-salicidation film of a semiconductor device is provided to minimize a variation of the size of a resistor of a silicide by reducing an etching thickness in a dry etching process. A first silicon oxide film, a silicon nitride film, and a second silicon oxide film are sequentially formed on a semiconductor substrate(100), on which a gate electrode(106) is formed. The second silicon oxide film is dry etched, such that a second silicon oxide film spacer is formed on the silicon nitride film on a sidewall of the gate electrode. A photoresist pattern for defining a non-salicidation region is formed on the silicon nitride film to open a portion of a gate electrode edge. The silicon nitride film and the first silicon oxide film are dry etched, which are exposed by the photoresist pattern, such that a hard mask(116) is formed on the gate electrode. A spacer(118) is formed at the gate electrode sidewall.

Description

METHODS FOR MANUFACTURING NON-SALICIDATION FILM OF SEMICONDUCTOR DEVICE}

1 is a view showing a salicide preventing region mask of a gate electrode in a semiconductor device;

2A to 2E are process flowcharts for sequentially explaining a method for manufacturing a salicide preventing film of a semiconductor device according to the prior art;

3A to 3E are process flowcharts for sequentially explaining a method for manufacturing a salicide preventing film of a semiconductor device according to the present invention;

<Description of the code | symbol about the principal part of drawing>

100 semiconductor substrate 102 device isolation film

104: gate insulating film 106: gate electrode

108: first silicon oxide film 110: silicon nitride film

112: second silicon oxide film 114: photoresist pattern

116: hard mask 118: spacer

120 source / drain junction 122 silicide metal

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for producing a salicide film of a semiconductor device capable of precisely controlling the resistance value of a gate electrode.

In general, silicides are actively applied to semiconductor device processes because of low resistance, high thermal stability, and easy application to current silicon processes. Furthermore, the silicide film formed on the gate electrode or the source / drain junction surface has an advantage of lowering the specific resistance of the gate electrode and the contact resistance of the source / drain, respectively.

In addition, a silicide film is simultaneously formed on the gate electrode and the source / drain junction surface by the spacer insulating film on the sidewall of the gate electrode, which is called a salicide (self-aligned silicide) process.

On the other hand, a product equipped with an analog input / output module or an electrostatic discharge (ESD) fuse is inevitable to control a certain level of current, so a transistor or a resistor is selected according to the design technology. When the circuit is configured as a resistor, a resistor on an active region or a gate poly line is realized through salicide blocking and dopant implantation. In this case, the resistance value is controlled by controlling the dopant concentration in the non-salicidation (NS) region and the dimension of the region. In the case of an analog circuit, the area directly affects the current distribution. As a result, patterning techniques for precise control are required.

Patterning of the salicide prevention (NS) region is a technique of defining a salicide prevention hard mask (a) on the gate electrode 16 formed on the semiconductor substrate 10, as shown in FIG. .

2A to 2E are process flowcharts for sequentially explaining a method for manufacturing a salicide prevention film of a semiconductor device according to the prior art.

Referring to these drawings, the salicide prevention film production process of a semiconductor device according to the prior art proceeds as follows.

First, as shown in FIG. 2A, as the semiconductor substrate 10, a shallow trench isolation (STI) process is performed on a silicon substrate to form an isolation layer 12 that defines an active region and an inactive region of the device. A conductive dopant is ion implanted in (10) to proceed a well process.

A gate insulating film 14 is formed on the semiconductor substrate 10, and as the gate conductive film, doped polysilicon is deposited and patterned to form the gate electrode 16.

As shown in FIG. 2B, the first silicon oxide film 18, the silicon nitride film 20, and the second silicon oxide film 22 are sequentially stacked as a spacer insulating material on the entire surface of the substrate having the gate electrode 16.

As shown in FIG. 2C, the photoresist is coated on the second silicon oxide layer 22 and the exposure and development process using the mask a defining the salicide prevention region as shown in FIG. 1 is performed to perform the gate electrode 16. A photoresist pattern 24 is formed to open a portion of the edge.

As shown in FIG. 2D, the second silicon oxide layer 22 exposed by the photoresist pattern defining the salicide prevention region is wet etched with HF solution, and a dry etching process such as a reactive ion etching (RIE) is performed. The silicon nitride film 20 and the first silicon oxide film 18 are etched. Alternatively, the second silicon oxide film 22, the silicon nitride film 20, and the first silicon oxide film 18 exposed by the photoresist pattern defining the salicide prevention region are etched by a dry etching process such as RIE.

Accordingly, the first silicon oxide film 18a, the silicon nitride film 20a, and the second silicon oxide film 22a are stacked on the gate electrode 16 to prevent salicide that opens a portion of the edges. 26) is formed. A spacer 28 is formed on the sidewall of the gate electrode 16 in which the first silicon oxide film 18b, the silicon nitride film 20b, and the second silicon oxide film 22b are stacked.

As shown in FIG. 2E, the source / drain junction 30 is formed in the substrate 10 exposed by the gate electrode 16 and the spacer 28 by implanting high concentrations of n-type or p-type dopant ions onto the entire surface of the resultant. ). In this case, the source / drain junction 30 may be formed of a lightly doped drain (LDD) structure.

Then, as a silicide metal on the entire surface of the resultant, titanium (Ti) is deposited and annealing is performed to form a source / drain junction with an upper portion of the gate electrode 16 edge exposed by the salicide-preventing hard mask 26. 30) a silicide metal (for example, titanium silicide film (TiSi)) 32 is formed on the surface. The salicide process is then completed by removing the metal for silicide that has not been silicided.

According to the prior art, the method of manufacturing a salicide barrier layer of a semiconductor device is limited in the selection of spacer materials since the use of a wet process in a hard mask manufacturing process presupposes the use of a selectivity for a wet solution. In addition, since there is no reactivity with the photoresist, when a slight photoresist residue occurs after photoresist patterning, an oxide layer remains in a corresponding region, and a dense pattern is realized due to the surface tension of the liquid solution. Will be subject to constraints.

However, when the dry etching process is used in the hard mask manufacturing process, the loading effect of the second silicon oxide film, which is thicker than other films, cannot be excluded. In the process of etching a spacer having a thickness, due to the difference in etching progress for the shape of the size of the pattern, the difference in the pattern size of the final salicide prevention (NS) region, the size of the pattern for the shape, and the difference in etching progress for the shape The size of the final salicide-preventive (NS) region represents an error relative to the design value.

Therefore, the method of manufacturing a salicide barrier film of a semiconductor device according to the prior art is a suitable method for implementing an electrostatic discharge (ESD) fuse, but there is a problem in applying it to a resistor of an analog circuit in which the ratio of the pattern size must be precisely controlled. .

An object of the present invention is to reduce the etching thickness during the dry etching process using the photoresist pattern of the salicide prevention (NS) region, in order to solve the problems of the prior art as described above, precise pattern of the salicide prevention (NS) region The present invention provides a method for manufacturing a salicide prevention film of a semiconductor device that can be controlled and applied to both an electrostatic discharge (ESD) fuse and an resistor of an analog circuit.

In order to achieve the above object, the present invention provides a method of manufacturing a hard mask pattern for preventing salicide on a portion of an upper portion of a gate electrode, the method comprising: forming a first silicon oxide film, a silicon nitride film, and a second silicon oxide film on a semiconductor substrate having a gate electrode; Sequentially stacking, dry etching the second silicon oxide film to form a second silicon oxide spacer on the silicon nitride film on the sidewall of the gate electrode, and defining a salicide prevention region for opening a portion of the gate electrode edge on the silicon nitride film. Forming a photoresist pattern, dry etching the silicon nitride film and the first silicon oxide film exposed by the photoresist pattern, forming a hard mask on the gate electrode, and forming a spacer on the sidewall of the gate electrode; Removing the pattern.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

3A to 3E are process flowcharts for sequentially explaining a method for manufacturing a salicide prevention film of a semiconductor device according to the present invention.

Referring to these drawings, the salicide prevention film production process of the semiconductor device according to the present invention proceeds as follows.

First, as shown in FIG. 3A, as the semiconductor substrate 100, an STI process is performed on a silicon substrate to form an isolation layer 102 defining an active region and an inactive region of the device, and then conducting a conductive layer in the semiconductor substrate 100. Ion implantation of the dopant proceeds to the well process.

A gate insulating film 104 is formed on the semiconductor substrate 100, and as the gate conductive film, doped polysilicon is deposited and patterned to form the gate electrode 106.

As shown in FIG. 3B, the first silicon oxide film 108, the silicon nitride film 110, and the second silicon oxide film 112 are sequentially stacked as a spacer insulating material on the entire surface of the substrate having the gate electrode 106. In this case, the first silicon oxide layer 108 serves as a stress buffer of the gate electrode 106 and the silicon nitride layer 110, and the silicon nitride layer 110 serves as an etch stop layer. Here, the first silicon oxide film 108 and the silicon nitride film 110 are each deposited at a thickness of 180 kV to 220 kV (about 200 kPa in this embodiment) by LPCVD (Low Pressure Chemical Vapor Deposition) method, respectively. Is deposited while maintaining a pressure of 1 torr while supplying 300 sccm and 200 sccm of N ₂ and TEOS at a temperature of 650 ° C., and the silicon nitride film 110 is 800 sccm and NH ₃ and DCS at a temperature of 700 ° C., respectively. The deposition was carried out while maintaining a pressure of 450torr while supplying 80sccm. The second silicon oxide film 112 deposits TEOS at a thickness of 720 kW to 880 kW (in this embodiment, about 750 kW) by LPCVD method, while supplying N ₂ and TEOS by 300 sccm and 200 sccm at 650 ° C., respectively. Deposit under pressure.

As shown in FIG. 3C, the silicon nitride film 110 on the upper surface of the gate electrode 106 is formed by performing a dry etching process such as RIE to make the surface of the silicon nitride film 110 an etch stop point (EPD). The second silicon oxide film 112 is etched until exposed. As a result, only the first silicon oxide film 108 and the silicon nitride film 110 remain on the upper surface of the gate electrode 106, and together with the first silicon oxide film 108 and the silicon nitride film 110 on the side of the gate electrode 106. The second silicon oxide film spacer 112a remains. For example, the second silicon oxide film spacer 112a is formed by etching the oxide film to a thickness of 900 kV to 1000 kV using a selectivity ratio between the oxide film and the nitride film.

Subsequently, a photoresist is coated on the entire surface of the resultant, and an exposure and development process using a mask (a) defining a salicide prevention (NS) region as shown in FIG. 1 is performed to form the silicon nitride layer 110 on the gate electrode 106. A photoresist pattern 114 for opening a portion of the edge of the gate electrode 106 is formed.

As shown in FIG. 3D, the silicon nitride film 110 and the first silicon oxide film 108 exposed by the photoresist pattern defining the salicide prevention (NS) region are etched by a dry etching process such as RIE. Accordingly, a salicide prevention hard mask 116 including a first silicon oxide layer 108a and a silicon nitride layer 110a for preventing salicide that opens a portion of the gate electrode edge on the gate electrode 106 is formed. A spacer 118 including a first silicon oxide film 108b, a silicon nitride film 110b, and a second silicon oxide film 112b is formed on the sidewall of the gate electrode 106.

Thereafter, the photoresist pattern is removed by a process such as etching.

3E, a source / drain junction 120 is formed in the substrate 100 exposed by the gate electrode 106 and the spacer 118 by implanting a high concentration of n-type or p-type dopant ions onto the entire surface of the resultant. ). In this case, the source / drain junction 120 may be formed in an LDD structure.

Then, as a silicide metal on the entire surface of the resultant, titanium (Ti) is deposited and an annealing process is performed to the top of the edge of the gate electrode 106 exposed by the salicide-preventing hard mask 116 and the surface of the source / drain junction 120. Silicide metals (eg, titanium silicide films (TiSi)) 122 are formed on the substrates. The salicide process is completed by removing the metal for silicide that has not been silicided.

Therefore, in the method for manufacturing a salicide barrier layer of the semiconductor device according to the present invention, a dry silicon is first formed by dry etching a second silicon oxide layer having a larger thickness than other layers, and then using a photoresist pattern defining a salicide barrier (NS) region. The etching process is performed to etch a silicon nitride film and a first silicon oxide film having a total film thickness of about 400 microseconds to manufacture a hard mask and a spacer.

Therefore, in the dry etching process for the hard mask and the spacer, since the etching target thickness is about 400 μs, the hard mask pattern which is a salicide prevention (NS) region is minimized by minimizing the loading effect according to the pattern shape formed on the top and sidewalls of the gate electrode. The size of can be implemented close to the design value.

On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.

As described above, the present invention forms a first silicon oxide film, a silicon nitride film, and a second silicon oxide film on the entire surface of a substrate having a gate electrode, and dry-etches the second silicon oxide film to define a salicide prevention (NS) region. The silicon nitride film and the first silicon oxide film exposed by the resist pattern are dry-etched to form a spacer on the hard mask and the gate electrode sidewalls on the upper portion of the gate electrode.

Therefore, in the dry etching process using the photoresist pattern of the salicide prevention (NS) region, the etching thickness is reduced compared to the conventional method, thereby enabling precise control of the hard mask pattern of the silicide prevention (NS) region. This minimizes the resistance area error of the silicide formed at the edge of the gate electrode, allowing precise control of the current distribution by adjusting the size of the resistor, which can be applied to both an ESD discharge and an analog circuit resistor. have.

Claims (3)

In the method of manufacturing a hard mask pattern for preventing salicide on the upper portion of the gate electrode, Sequentially depositing a first silicon oxide film, a silicon nitride film, and a second silicon oxide film on a semiconductor substrate having the gate electrode; Dry etching the second silicon oxide layer to form a second silicon oxide spacer on the silicon nitride layer on the sidewall of the gate electrode; Forming a photoresist pattern on the silicon nitride layer, the photoresist pattern defining a salicide prevention region for opening a portion of the gate electrode edge; Dry etching the silicon nitride film and the first silicon oxide film exposed by the photoresist pattern to form a hard mask on the gate electrode and to form spacers on the sidewalls of the gate electrode; Removing the photoresist pattern Salicide prevention film production method of a semiconductor device comprising a. The method of claim 1, The first silicon oxide film and the silicon nitride film are deposited with a thickness of 180 kV to 220 kV by LPCVD. The method of claim 1, The second silicon oxide film is deposited to a thickness of 720 kPa to 880 kPa by LPCVD method.

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