KR20030051070A - Method for forming of semiconductor memory device - Google Patents

Abstract

PURPOSE: A method for fabricating a semiconductor memory device is provided to reduce fabricating cost and supply convenience for use by forming a flash cell while a merged memory logic(MML) semiconductor device including a dynamic random access memory(DRAM) cell is formed so that the flash cell and the MML semiconductor device are integrated into a single chip. CONSTITUTION: An ion implantation process using dopants for forming an isolation layer(11), a well(12), etc. on a semiconductor substrate(10) is performed to form a DRAM region(C), a flash cell region(B) and a logic region(A). After the first gate oxide layer and the first gate electrode(14) for the logic region and the cell region are deposited, the first gate electrode in the DRAM region is removed through an etch process. The second oxide layer(15) and the second gate electrode(16) for the DRAM region are deposited. After a high temperature low deposition(HLD) oxide layer(17) and a nitride layer(18) as a hard mask(19) are deposited, a DRAM gate(20) and a flash cell control gate are patterned. A logic gate(22) and a flash cell floating gate(23) are simultaneously patterned in the logic region and the flash cell region.

Description

Method of manufacturing a semiconductor memory device {METHOD FOR FORMING OF SEMICONDUCTOR MEMORY DEVICE}

The present invention relates to a method for forming a DRAM cell and a flash cell of an MML semiconductor device, and simultaneously forms a flash cell to form a single chip when forming a complex semiconductor device including a DRAM cell, thereby reducing manufacturing costs of a semiconductor device. A method of manufacturing a semiconductor memory device to provide convenience in use.

In general, a composite semiconductor (MML: Merged Memory Logic), in which memory and logic are formed on a single chip, has been recently used with increasing interest, and this MML semiconductor device has been increasingly used. Since it is possible to manufacture logic, DRAM, and memory such as SRAM in a single process, it has the advantage of being able to operate at a higher speed and use at lower power than existing chips without any special design change.

On the other hand, since the manufacturing process of the memory product and the manufacturing process of the logic product are manufactured at the same time at the same time, the size of the unit chip is increased, and thus, not only has the disadvantage of requiring a lot of difficulty to proceed with the manufacturing process but also in the memory. Transistors are more focused on preventing leakage current than requiring high current driving power, but logic products have to be manufactured in one chip with both characteristics such as high current driving capability. This is accompanied by.

As described above, it is difficult to manufacture different devices on one chip. However, in accordance with the recent trend, methods of manufacturing various different semiconductor devices on one single chip are gradually diversified and become common.

First, a method of manufacturing a flash cell includes partially forming a floating gate node, depositing a dielectric without an interlayer insulating process, and then patterning a large control gate node by deposition and using the same. A self-aligning method forms a following floating gate node to simultaneously form a capacitor and a word line.

At this time, the control gate node should be formed thick so that it can be used as a hard mask. In addition, the photo process is necessary because the cell portion, which is the floating gate node region etched by the self alignment method, and the peripheral circuit portion that does not use the self alignment method are divided.

On the contrary, in the DRAM cell process, the oxide film and word line for the simple word line (gate node of the transistor), not the capacitor, are completely formed by the deposition pattern, and the interlayer insulating film is deposited to form the bit line and the capacitor. .

Therefore, since the word line forming method of the DRAM cell and the word line manufacturing method of the flash cell are different from each other, there is a problem in that the flash cell cannot be simultaneously formed on the composite semiconductor chip including the DRAM.

The present invention has been made to solve the above problems, and an object of the present invention relates to a method for forming a DRAM cell and a flash cell of an MML semiconductor device, and simultaneously forming a flash cell when forming a composite semiconductor device including a DRAM cell. Therefore, the present invention provides a method of manufacturing a semiconductor memory device, which reduces the manufacturing cost of a semiconductor device and provides convenience in use since it is manufactured in one single chip.

1A to 1E are cross-sectional views illustrating a flash cell forming process of a semiconductor device according to the present invention.

-Explanation of symbols for the main parts of the drawings-

10 substrate 11 device isolation film

12 well 13 gate oxide film

14: first gate electrode 15: second oxide film

16 second gate electrode 17 HLD oxide film

18: nitride film 19: hard mask

20: DRAM gate 21: flash cell control gate

22: logic gate 23: flash cell floating gate

A: logic area B: flash cell area

C: DRAM area

According to an aspect of the present invention, there is provided a method of forming a DRAM region, a flash cell region, and a logic region using an ion implantation method of an element forming dopant such as an isolation layer or a well on a semiconductor substrate, and for the logic and cell regions. Removing the first gate electrode of the DRAM region by an etching process after depositing the first gate oxide layer and the first gate electrode, depositing the second oxide layer and the second gate electrode for the DRAM region, and depositing the HLD oxide layer using a hard mask. Patterning a DRAM gate and a flash cell control gate after depositing a night light layer, and simultaneously patterning a logic gate and a flash cell floating gate in the logic and flash cell regions. It relates to a manufacturing method.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same reference numerals and names.

1A to 1E are cross-sectional views illustrating a flash cell forming process of a semiconductor device according to the present invention.

First, as shown in FIG. 1A, a dopant for forming an element, such as an isolation layer 11 and a well 12, is formed on a semiconductor substrate 10 by using an ion implantation method. The DRAM region C, the flash cell region B, and the logic may be formed. After the region (A) is formed, as shown in FIG. 1B, the first gate oxide layer 13 and the first gate electrode 14 for the logic and cell regions are deposited, and then the first gate electrode of the DRAM region A ( 14) is removed by an etching process.

Subsequently, as shown in FIG. 1C, the second oxide film 15 and the second gate electrode 16 for the DRAM region are deposited, and then the HLD oxide film 17 and the nightlight 18 film are deposited using the hard mask 19. Next, as illustrated in FIG. 1D, the DRAM gate 20 and the flash cell control gate 21 are patterned.

Thereafter, as shown in FIG. 1E, the logic gate 22 and the flash cell floating gate 23 are simultaneously patterned.

As described above, when the DRAM cell and the flash cell forming method of the MML semiconductor device according to the present invention are used, a flash cell is formed simultaneously with a complex semiconductor chip process including a DRAM cell on a semiconductor substrate and manufactured as a single chip. Therefore, there is an advantage that the manufacturing cost of the semiconductor device can be reduced, and convenience in use can be provided.

Claims (1)

Forming a DRAM region, a flash cell region, and a logic region on the semiconductor substrate by an ion implantation method of a device forming dopant such as an isolation layer or a well; Removing the first gate electrode of the DRAM region by an etching process after depositing the first gate oxide layer and the first gate electrode for the logic and cell region; Depositing a second oxide film and a second gate electrode for the DRAM region, depositing an HLD oxide film and a night light film using a hard mask, and patterning a DRAM gate and a flash cell control gate; Simultaneously patterning the logic gate and the flash cell floating gate in the logic and flash cell regions A method of manufacturing a semiconductor memory device, comprising.