KR100310256B1 - Formation method of analog capacitor in merged memory &logic device - Google Patents

Abstract

The present invention provides a plug poly during the process of manufacturing a dynamic random access memory (DRAM) in forming an analog capacitor required for the operation of a stable circuit of a logic portion of an MML device. A method for increasing the reliability and productivity of an MML device by manufacturing an analog capacitor using a polysilicon film and a bit line as electrodes for forming a self-aligned contact (SAC). It is about. According to the method of forming an analog capacitor of the MML device according to the present invention, an analog capacitor can be manufactured in a logic part by adding only one step, thereby simplifying the manufacturing process of the MML device and improving the reliability and productivity of the MML device. Indicates.

Description

FORMATION METHOD OF ANALOG CAPACITOR IN MERGED MEMORY & LOGIC DEVICE

The present invention relates to a method of forming a capacitor of an MML device, and more particularly, to a stable circuit operation of a logic part of a MML device during a manufacturing process. Polysilicon film used in the formation of Plug Poly Self Align Contact (SAC) during the production of the Dynamic Random Access Memory (DRAM) in the manufacture of the required analog capacitors; The present invention relates to a method for increasing the reliability and productivity of an MML device by manufacturing an analog capacitor using a bit line as an electrode.

In general, composite semiconductors (MML; Merged Memory & Logic), in which memory and logic are formed on a single chip, have recently become more and more popular, and these MML semiconductor devices have been increasingly used. It is possible to manufacture logic and memory in a single process on a single chip, so it can operate at a higher speed and use at lower power than existing chips without any special design change.

On the other hand, since the manufacturing process of the memory product and the manufacturing process of the logic product are simultaneously manufactured on one chip, the size of the unit chip becomes large, and thus has a disadvantage of requiring a lot of difficulty to proceed with the manufacturing process.

Especially in MML devices that need to form DRAM and logic on a single chip, the analog capacitor used in logic must be included to drive the stable operation of the circuit. The capacitor included in DRAM is used to store information. The breakdown voltage of the capacitor is set relatively low because this is not applied, whereas analog capacitors in logic are frequently applied with alternating current (AC) voltage and direct current (DC) voltage. The breakdown voltage must be made higher than the capacitor of.

In the general process of logic, one poly layer is used, so to form an analog capacitor, an additional poly layer is formed on the gate poly to form an electrode of the capacitor.

When manufacturing an analog capacitor in an MML device in which DRAM and logic are formed on a single chip, if the capacitor manufacturing method of the DRAM is used as it is, the reliability of the analog capacitor is reduced because the breakdown voltage is lowered due to structural problems. In addition, if the logic process is performed using the analog capacitor manufacturing method as it is, the process step is increased more than necessary and the efficiency is reduced.

It is an object of the present invention to manufacture an analog capacitor using a plug poly and a bit line used as an electrode in the method of forming an analog capacitor of an MML device, which can simplify the process while ensuring the stability of a circuit in an MML process. It is to provide a method of forming an analog capacitor of an MML device.

1 to 8 show sequential process diagrams according to suitable embodiments of the present invention.

♣ Explanation of symbols of main part of drawing ♣

101: Substrate

102: Field Oxide

103A: Word Line

103B: Gate Poly

104: N + / P + junction

105: spacer oxide

106: 2nd spacer oxide

107: doped polysilicon (plug poly)

201: Photo Resist

301: Inter Layer Oxide

302 photoresist (P / R)

501: Bit Line Contact Spacer

502: photoresist (P / R)

601 bit line polycide

701: photoresist (P / R)

801: DRAM Bit Line

802: DRAM Cylinder Capacitor

803: Interconnection Metal Line

This object is achieved by depositing a doped polysilicon layer as plug poly on top of a semiconductor substrate on which word lines and gate electrodes are formed;

Thereafter leaving an area of plug poly in the logic portion of the logic portion to form a plug poly pattern of the doped polysilicon layer;

Then depositing and planarizing the interlayer insulating film;

Then forming a pattern through etching with the bit line contact mask to form a bit line contact in the analog capacitor of the logic portion;

Then depositing a bitline contact spacer film and leaving a spacer oxide in the analog capacitor region of the logic portion to form a pattern;

Then depositing the bitline polysides and leaving the polysides in the analog capacitor region of the logic portion to form a pattern;

Thereafter depositing an interlayer insulating film and proceeding to fabricating a DRAM capacitor; And

It is achieved by providing a method for forming an analog capacitor of the MML semiconductor device, characterized in that it comprises the step of performing a metal wiring process on top of the capacitor.

In the method of forming an analog capacitor of the MML semiconductor device according to the present invention, it is preferable that the doping concentration of the doped polysilicon used as the plug poly is 10E20 or more.

In the method of forming an analog capacitor of the MML semiconductor device according to the present invention, the bit line contact spacer film is preferably an oxide film, a nitride film, or a nitride oxide film.

In the method of forming an analog capacitor of the MML semiconductor device according to the present invention, it is preferable to pre-clean by adding an etchant for etching the oxide before the bit line polyside deposition, and the thickness of the oxide film by adjusting the pre-cleaning time during the pre-cleaning. It is desirable to control the.

MML devices that form DRAMs and logic on a single chip must include an analog capacitor used by the logic to drive the stable operation of the circuit.

In particular, in order to have an output having a constant gain with respect to the input, a capacitor more precise than a resistor is used to stably drive the operation of the circuit. Essential use in the circuit.

Although there are capacitors for storing information in DRAM, it is difficult to use DRAM capacitors as analog capacitors because the breakdown voltage is lower than that of logic capacitors. Therefore, in the MML device, it is necessary to form an analog capacitor in a logic region rather than a DRAM region to form a capacitor having a different breakdown voltage and having a different purpose than a DRAM capacitor.

Therefore, in the present invention, the basic process of DRAM is used as it is to form an analog capacitor in an MML device, and the process is performed to form an analog capacitor by leaving an oxide in the logic part through mask and etching after depositing an insulating film on the analog capacitor. It is. In this way, a method of manufacturing an MML device can be simplified by forming an analog capacitor of logic by adding only one mask step to the DRAM forming process.

Hereinafter, with reference to the accompanying drawings will be described in more detail the configuration of the present invention.

1 to 8 show sequential process diagrams according to suitable embodiments of the present invention.

First, as shown in FIG. 1, the plug poly layer 107 is formed on the silicon substrate 101 on which the field oxide film 102 is formed in the DRAM portion and the logic portion, and the word line 103A and the gate electrode 103B are formed. E).

A pattern is formed on the plug poly layer 107 through etching with a mask. At this time, the area where the analog capacitor is to be formed in the logic part should be covered with the photoresist 201 so that the plug poly 107 remains after the etching process is completed. The process is completed as shown in Figure 2 below.

After the photosensitive agent 201 is removed, an oxide film is deposited using the interlayer insulating film 301 and the planarization process is performed, and then the bit line contact mask 302 is processed to form a pattern of the bit line contact portion as shown in FIG. 3. .

Thereafter, as shown in FIG. 4, bit line contact etching is performed to form a bit line contact, and to remove oxide in a region where an analog capacitor of logic is to be formed.

Subsequently, as shown in FIG. 5, an oxide to be used as a bit line contact spacer is deposited and a mask process is performed to open other portions except the analog capacitor region of the logic portion. Thereafter, the etching process is performed to leave oxide 501 in the form of a spacer in the analog capacitor portion and the bit line contact, and then the polyside 601 used as the bit line is deposited. The state completed in the above process is shown in Figure 6 below.

Subsequently, as shown in FIG. 7, the pattern of the bit line 601A is formed in the DRAM portion through the mask and the etching, and the pattern 601B of the polyside is formed in the logic portion.

After the capacitor 802 is formed in the DRAM portion, the metal wire 803 is deposited to use the plug poly 107 portion and the bit line polyside 601B as an electrode of the analog capacitor. The process is completed is shown in Figure 8 below.

As described above, when forming the analog capacitor of the MML device, by using the method of using the plug poly layer and the bit line used in the DRAM process as the electrodes of the analog capacitor of the logic part, only one step is added to the analog part of the logic part. Capacitors can be manufactured to simplify the manufacturing process of MML devices and increase the reliability and productivity of MML devices.

Claims (4)

Depositing a doped polysilicon layer with a plug poly layer on top of the semiconductor substrate on which word lines and gate electrodes are formed; Thereafter leaving an area of plug poly in the logic portion of the logic portion to form a plug poly pattern of the doped polysilicon layer; Then depositing and planarizing the interlayer insulating film; Then forming a pattern through etching with the bit line contact mask to form a bit line contact in the analog capacitor of the logic portion; Then depositing a bitline contact spacer film and leaving a spacer oxide in the analog capacitor region of the logic portion to form a pattern; Then depositing the bitline polysides and leaving the polysides in the analog capacitor region of the logic portion to form a pattern; Thereafter depositing an interlayer insulating film and proceeding to fabricating a DRAM capacitor; And And performing a metallization process on the upper portion of the capacitor. The method of claim 1, wherein the doping concentration of the doped polysilicon used as the plug poly is to be 10E20 or more. 2. The method of claim 1, wherein the bit line contact spacer film is an oxide film, a nitride film, or a nitride oxide film. The analog capacitor of claim 1, wherein the oxide film is pre-cleaned by adding an etchant that etches the oxide prior to the bit line polyside deposition, and the oxide film is adjusted by adjusting the pre-cleaning time during the pre-cleaning. Formation method.