JPH09298283A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique which can improve a processing accuracy in steps of manufacturing a DRAM having various elements. SOLUTION: Polycrystalline silicon films 33, 31 and 30 forming part of a storage electrode SN of a capacitive element for information storage as a memory cell of a DRAM are disposed in logic parts. Thereby, a limitation of a level difference between the memory cell array and logic part of the DRAM can be softened, and the level difference after formation of the capacitive element of the memory cell for information storage can be set to be within a focus depth range allowable by a lithographic technique.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and its manufacturing method, and more particularly to a DRAM (Dynami
C Random Access Memory) and a technology effective when applied to a semiconductor integrated circuit device in which logic is mixed.

[0002]

2. Description of the Related Art In recent years, in a game machine for home use, there is an increasing demand for an image similar to a natural image using computer graphics. However, in order to realize a natural image, the data transfer rate of the DRAM used as the main memory is set to about 1000 from the current 135 Mbyte / sec.
It is necessary to double 100 Gbytes / second or more.
This is difficult to achieve with M alone.

Therefore, as one method for improving the performance of a game machine, DRAM and logic are mixed in one semiconductor chip to form one system to shorten the propagation time of bus signals and avoid propagation delay. Has proposed a method for increasing the data transfer rate.

A semiconductor integrated circuit device in which DRAM and logic coexist (hereinafter referred to as logic-embedded DRAM)
For more information, for example, July 1, 1995, "Nikkei Microdevice", Nikkei McGraw-Hill, P80-P8
5 are described.

[0005]

The present inventors have found the following problems in developing the logic embedded DRAM.

In a large-capacity DRAM, in order to compensate for the decrease in the accumulated charge amount (Qs) of the information storage capacitive element (capacitor) due to the miniaturization of the memory cell, the information storage capacitive element is used as a memory cell selection MISFET (Metal). Insulator Semico
It has a stack structure that is placed above the nductor field effect transistor.

Among the memory cells of the stack structure, a capacitor over bit line (Capacitor Over B) in which an information storage capacitive element is arranged above a bit line.
A memory cell having an itline (COB) structure does not require a margin for alignment between a storage electrode and a connection hole for connecting a bit line to a memory cell selection MISFET. Of the present invention, the bit line is shielded by the information storage capacitive element, so that a high signal-to-noise (S / N) ratio can be obtained.

As the memory cell having the COB structure, for example, a first conductive film (polycrystalline silicon film or polycide film) is formed on the main surface of a semiconductor substrate to select a memory cell MISF.
A gate electrode of ET and a first word line are formed, and a plug of an information storage capacitive element is formed by a second conductive film (polycrystalline silicon film) deposited on the upper layer of the first conductive film.
The third conductive film (polycrystalline silicon film or polycide film) deposited on the conductive film forms a bit line, and the fourth conductive film (polycrystalline silicon film) deposited on the upper layer of the third conductive film.
To form a storage electrode of the information storage capacitor, and a fifth conductive film (polycrystalline silicon film) deposited on the fourth conductive film.
To form the plate electrode of the information storage capacitive element, and to form the first wiring layer of the extraction electrode of the plate electrode with the sixth conductive film (aluminum alloy film or tungsten film) deposited on the fifth conductive film, A configuration is conceivable in which the second wiring layer such as the second word line and the common source line is formed by the seventh conductive film (aluminum alloy film or tungsten film) deposited on the upper layer of the sixth conductive film.

By the way, the DRAM portion in the logic-embedded DRAM is composed of a memory array in which a large number of memory cells are arranged in a matrix and peripheral circuits arranged around the memory array. Therefore, as a peripheral circuit when the memory cell having the COB structure is formed, the gate electrode of the MISFET is formed of the first conductive film on the main surface of the semiconductor substrate, and the first wiring layer is formed of the sixth conductive film. A configuration in which the second wiring layer is formed by using the seventh conductive film may be considered. Further, also in the logic portion, as in the peripheral circuit of the DRAM portion, the gate electrode of the MISFET is formed on the main surface of the semiconductor substrate with the first conductive film, and the first wiring layer is formed with the sixth conductive film. A configuration in which the second wiring layer is formed of the seventh conductive film can be considered.

That is, in the memory cell having the COB structure, since the information storage capacitive element is formed above the bit line, the elevation of the memory array in the DRAM section (the height from the surface of the semiconductor substrate) of the DRAM section is in the DRAM section. It is higher than that of the peripheral circuit and the logic section.

For this reason, through holes formed in the first wiring layer, the second wiring layer, or the interlayer insulating film between these wiring layers are provided with through holes formed in the memory cell array and peripheral circuits having different altitudes.
Alternatively, in the lithography technique for forming the logic portion, it is necessary to allow for a sufficient depth of focus to prevent deterioration of the dimensional accuracy of the photoresist. However, in order to obtain the allowable dimensional accuracy of the photoresist, simply extrapolating from the trend of the lithography technique, for example, a 256 kbit DRAM requires a depth of focus of ± 0.25 μm or less, which is actually a resolution limit. Become.

Further, since it is necessary to connect a random logic circuit in the logic, the multilayer wiring of the four-layer structure has already been adopted in the logic of the 0.6 μm generation. Further, as the number of wiring layers increases, the transistor density can be increased, and the logic performance improves. Therefore, there is an increasing demand for multilayered technology of wiring layers with an increased total number.

However, such a technique of multilayering the wiring layers in the logic is not necessary in the DRAM, and in the logic mixed DRAM, the throughput is lowered due to the increase in the number of steps in the wiring process.

An object of the present invention is to provide a technique capable of improving the processing accuracy in a manufacturing process of a logic embedded DRAM having a memory cell having a stack structure in which an information storage capacitive element is arranged above a memory cell selecting MISFET. To provide.

Another object of the present invention is to provide a technique capable of improving the throughput of the logic embedded DRAM by reducing the number of manufacturing steps.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0017]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. That is, (1) the semiconductor integrated circuit device according to the present invention has a DRAM section including a memory cell array and peripheral circuits and a logic section, and constitutes a storage electrode of an information storage capacitive element of the memory cell of the DRAM section. The first conductive film is disposed in at least one of the peripheral circuit of the DRAM section and the logic section and is used as a wiring layer.

(2) Further, the semiconductor integrated circuit device of the present invention is a DRAM comprising a memory cell array and peripheral circuits.
A second conductive film, which has a portion and a logic portion and constitutes a plate electrode of an information storage capacitive element of a memory cell of the DRAM portion, is arranged in at least one of a peripheral circuit of the DRAM portion or the logic portion. And used as a wiring layer.

(3) Further, the semiconductor integrated circuit device of the present invention is a DRAM comprising a memory cell array and peripheral circuits.
A first conductive film having a storage section and a logic section and forming a storage electrode of an information storage capacitive element of the memory cell of the DRAM section and a plate electrode of the information storage capacitive element of the memory cell of the DRAM section. The constituent second conductive film is arranged in at least one of the peripheral circuit of the DRAM part and the logic part and used as a wiring layer.

(4) The semiconductor integrated circuit device of the present invention is a DRAM including a memory cell array and peripheral circuits.
And a logic part, and a first conductive film forming a storage electrode having a laminated structure sandwiching a dielectric film of an information storage capacitive element of the memory cell of the DRAM part and a second plate forming a plate electrode. The conductive film of at least one of the peripheral circuit of the DRAM section or the logic section,
The second conductive film is used as at least one wiring layer of the peripheral circuit of the DRAM section or the logic section.

According to the above-mentioned means, the first electrode forming the storage electrode of the information storage capacitive element of the memory cell of the DRAM section is formed.
Of the conductive film, the second conductive film forming the plate electrode, or the first conductive film forming the storage electrode and the second conductive film forming the plate electrode are connected to the peripheral circuit of the DRAM section or the logic section. A DRAM after forming an information storage capacitive element by disposing it on at least one side.
Difference between the memory cell array of the above section and the logic section or D
The elevation difference between the memory cell array of the RAM section and the peripheral circuits of the DRAM section can be reduced, and this elevation difference can be kept within a range allowable from the depth of focus of the lithography technique. Further, the wiring layer used in at least one of the peripheral circuit of the DRAM section or the logic section can be formed in the process of manufacturing the information storage capacitive element of the memory cell of the DRAM section.

[0022]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In all the drawings for explaining the embodiments, those having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

The logic part in the logic embedded DRAM is a CMOS (Complementary Metal Oxide Semiconductor).
Since the semiconductor substrate of the peripheral circuit of the logic part and the DRAM part has substantially the same cross-sectional structure, the logic part will be described in this embodiment.
The description of the peripheral circuit of the M section is omitted.

(First Embodiment) The left side of FIG. 1 shows a DR in a logic embedded DRAM which is an embodiment of the present invention.
A cross-sectional view of a main part of a semiconductor substrate showing a memory cell of an AM section, the right side of FIG.
It is a principal part sectional view of a semiconductor substrate which shows ETQs.

In the memory cell of the DRAM portion, the gate electrode 10 of the memory cell selecting MISFET Qt is formed by the first conductive film (tungsten silicide (WSi ₂ ) film 7 and polycrystalline silicon film 6) deposited on the main surface of the semiconductor substrate 1. And the second conductive film (polycrystalline silicon film 19) deposited on the upper layer of the first conductive film constitutes the plug PG of the information storage capacitive element.
And a third conductive film (WSi ₂ film 25 and polycrystalline silicon films 24, 21) deposited on the second conductive film.
To form a bit line BL, and a fourth conductive film (polycrystalline silicon film 35, 33, 31,
30) constitutes the storage electrode SN of the information storage capacitive element,
The fifth conductive film (polycrystalline silicon film 37) deposited on the fourth conductive film is used as the plate electrode P of the information storage capacitive element.
The sixth conductive film (metal film 41) that composes L and is deposited on the upper layer of the fifth conductive film constitutes the first wiring layer MM1, and the seventh conductive film (metal is deposited on the upper layer of the sixth conductive film). The film 43) constitutes the second wiring layer MM2.

On the other hand, in the logic portion, the gate electrode 10 of the p-channel type MISFET Qs and the n-channel type MISFET are formed by the first conductive film (WSi ₂ film 7 and polycrystalline silicon film 6) deposited on the main surface of the semiconductor substrate 1. A third conductive film (WSi ₂ film 25 and polycrystalline silicon films 24, 21) which forms a gate electrode (not shown) and which forms a bit line BL of the memory cell deposited on the first conductive film.
To form a first wiring layer (not shown), and to form a part of the storage electrode SN of the information storage capacitive element of the memory cell deposited on the third conductive film, a fourth 'conductive film (polycrystalline). The second wiring layer LM2 is constituted by the silicon films 33, 31, 30),
The sixth conductive film (metal film 41) deposited on the upper layer of the fourth 'conductive film constitutes the third wiring layer LM3, and the seventh conductive film (metal film 43) deposited on the upper layer of the sixth conductive film. The fourth wiring layer LM4 is configured.

Next, the memory cell of the DRAM section shown in FIG. 1 and the p-channel type MISFET Q of the logic section are shown.
A method for manufacturing s will be described with reference to FIGS.

First, as shown in FIG. 2, p is formed on the main surface of a semiconductor substrate 1 made of p ⁻ type silicon single crystal by a known method.
The type well 2, the n-type well 3, the field insulating film 4, and the gate insulating film 5 are sequentially formed.

Next, as shown in FIG. 3, the polycrystalline silicon film 6 into which phosphorus (P) has been introduced on the semiconductor substrate 1 and WSi.
₂ film 7, silicon oxide film 8 and silicon nitride film 9 are sequentially deposited. Thereafter, by sequentially etching the laminated film of photoresist as a mask the silicon nitride film 9, a silicon oxide film 8, WSi ₂ film 7 and polycrystalline silicon film 6, the WSi ₂ film 7 and polycrystalline silicon film 6 MISFET for selecting memory cell of DRAM part
Gate electrode 10 (first conductive film) of Qt, p-channel type MISFET Qs and n-channel type MIS in the logic section
The gate electrode 10 (first conductive film) of the FET (not shown) is formed.

Next, the semiconductor substrate 1 is subjected to a thermal oxidation process, so that the thin silicon oxide film 1 is formed on the side walls of the WSi ₂ film 7 and the polycrystalline silicon film 6 which form the gate electrode 10.
Form one.

Next, using the photoresist and the laminated film composed of the silicon nitride film 9, the silicon oxide film 8, the WSi ₂ film 7 and the polycrystalline silicon film 6 as a mask, the n-type well 3 in the logic portion is provided with p-type impurities, For example, boron fluoride (BF ₂ ) is ion-implanted, and p-channel type MISFETQ
s p-type semiconductor region (source region, drain region) 12
Are self-aligned with the gate electrode 10.

Although not shown in the figure, like the p-type semiconductor region 12 of the p-channel type MISFETQs, an n-type impurity, for example, P is ion-implanted into the p-type well of the logic portion to form an n-channel type MISFET. The n-type semiconductor region (source region, drain region) is formed in self-alignment with the gate electrode.

After that, the silicon nitride film deposited on the semiconductor substrate 1 is processed by anisotropic etching such as RIE (Reactive Ion Etching) to form sidewall spacers 13 on the side walls of the laminated film. After forming the side wall spacers 13, a p-type impurity having a higher concentration than the p-type impurity, for example, BF ₂ is ion-implanted into the n-type well 3 of the logic portion, so that the source region of the p-channel type MISFET Qs is formed. The drain region may have an LDD (Lightly Doped Drain) structure.

Although not shown in the figure, like the p-channel type MISFETQs, an n-type impurity having a higher concentration than the n-type impurity, for example, arsenic (As) is ion-implanted into the p-type well of the logic portion. Therefore, n-channel type M
The source region and the drain region of the ISFET may have an LDD structure.

Next, as shown in FIG. 4, a silicon oxide film 14 and a BPSG (Boron Phosphor) are formed on the semiconductor substrate 1.
After depositing the ous Silicate Glass) film 15 by the CVD method, the BP is subjected to the reflow treatment at 900 to 950 ° C.
The surface of the SG film 15 is flattened, and then a polycrystalline silicon film 16 into which P is introduced is deposited on the semiconductor substrate 1 by the CVD method.

After that, the polycrystalline silicon film 16, the BPSG film 15, the silicon oxide film 14 and the insulating film in the same layer as the gate insulating film 5 are sequentially etched by using the photoresist as a mask, whereby the MISFET for memory cell selection.
First n-type semiconductor region 17 formed after one of Qt
A first contact hole 18 is formed thereover. Then
An n-type impurity, for example, P is ion-implanted into the memory cell using the photoresist as a mask to select a MIS for memory cell selection.
One first n-type semiconductor region 17 of the FET Qt is formed.

Next, as shown in FIG. 5, a polycrystalline silicon film 19 into which P is introduced is deposited on the semiconductor substrate 1 by the CVD method, and then the polycrystalline silicon film 19 and the polycrystalline silicon film 16 are removed. By sequentially etching back, a plug PG (second conductive film) made of a polycrystalline silicon film 19 is formed in the first contact hole 18.

Next, the silicon oxide film 2 is formed on the semiconductor substrate 1.
CVD of the polycrystalline silicon film 21 in which 0 and P are introduced
Deposited by the method. Then, using the photoresist as a mask, the polycrystalline silicon film 21, the silicon oxide film 20, B
By sequentially etching the PSG film 15, the silicon oxide film 14, and the insulating film in the same layer as the gate insulating film 5,
A second contact hole 23 is formed on the second n-type semiconductor region 22 formed after the other of the memory cell selection MISFETQt.

When forming the second contact hole 23, although not shown in the figure, it is formed on the n-type well 3 of the logic portion, the n-type semiconductor region of the n-channel type MISFET or the gate electrode 10. Alternatively, a contact hole may be formed.

Next, as shown in FIG. 6, the semiconductor substrate 1
Polycrystalline silicon film 24 with P introduced thereon and WSi
_{After the 2} film 25 is sequentially deposited by the CVD method, the WSi ₂ film 25, the polycrystalline silicon film 24, and the polycrystalline silicon film 21 are sequentially etched using the photoresist as a mask, whereby the WSi ₂ film 25 and the polycrystalline silicon film are formed. Two
4. The bit line BL (third conductive film) of the memory cell made of the polycrystalline silicon film 21 is formed.

Further, the second n-type semiconductor region 22 of the memory cell selecting MISFET Qt is formed by diffusion of P introduced into the polycrystalline silicon film 24, and the bit line BL passes through the second contact hole 23. The memory cell selection MISFET Qt is connected to the second n-type semiconductor region 22.

At this time, although not shown in the figure, WSi
The first wiring layer (third conductive film) of the logic portion including the _second film 25, the polycrystalline silicon film 24, and the polycrystalline silicon film 21.
And the first wiring layer may be connected to the n-type well 3 of the logic portion, the n-type semiconductor region of the n-channel type MISFET or the gate electrode 10.

Next, as shown in FIG. 7, a silicon oxide film 26, a silicon nitride film 27 and a BP are formed on the semiconductor substrate 1.
After sequentially depositing the SG film 28 by the CVD method,
The surface of the BPSG film 28 is flattened by a reflow process at ˜950 ° C., and then a silicon oxide film 29 is deposited on the semiconductor substrate 1. After that, the silicon oxide film 29 and the BPSG film 28 deposited in the logic portion are sequentially etched using the photoresist as a mask, and then the polycrystalline silicon film 30 into which P is introduced is deposited on the semiconductor substrate 1 by the CVD method. Next, this polycrystalline silicon film 30 is etched using the photoresist as a mask.

Next, as shown in FIG. 8, after a polycrystalline silicon film 31 into which P is introduced is deposited on the semiconductor substrate 1 by the CVD method, this polycrystalline silicon film 31 is anisotropic by the RIE method or the like. By processing by etching, sidewall spacers are formed on the sidewalls of the polycrystalline silicon film 30. Next, the silicon oxide film 29, the BPSG film 28, the silicon nitride film 27, the silicon oxide film 26, and the silicon oxide film 20 of the memory cell are sequentially etched using the photoresist as a mask to form the first contact hole 18. The third contact hole 32 is formed on the plug PG, and then the polycrystalline silicon film 33 in which P is introduced and the BPSG are formed on the semiconductor substrate 1.
The film 34 is sequentially deposited by the CVD method.

Although not shown in the drawing, when forming the third contact hole 32, on the n-type well 3 in the logic portion, on the n-type semiconductor region of the n-channel type MISFET, on the gate electrode 10 or A contact hole may be formed on the first wiring layer and the polycrystalline silicon film 33 may be connected to the n-type well 3, the n-type semiconductor region of the n-channel type MISFET, the gate electrode 10 or the first wiring layer.

Next, using the photoresist as a mask, the BPSG film 34 and the polycrystalline silicon film 33 of the memory cell,
After sequentially etching 30, the polycrystalline silicon film 35 in which P is introduced on the semiconductor substrate 1 is removed by C as shown in FIG.
The BPSG film 34 and the polycrystalline silicon film 3 are deposited by the VD method, and then the polycrystalline silicon film 35 is processed by anisotropic etching such as the RIE method.
The polycrystalline silicon film 35 is left on the side walls of 3, 30.

Then, the BPSG film 34, the silicon oxide film 29, and the BPSG film 28 are removed by, for example, wet etching using a hydrofluoric acid solution, and the polycrystalline silicon films 35, 33, 31, 30 are formed in the memory cells. Then, a cylindrical storage electrode SN (fourth conductive film) is formed. Then, the polycrystalline silicon film 33 in the logic portion is etched using the photoresist as a mask to form a second wiring layer LM2 (fourth 'conductive film) in the logic portion, which is composed of the polycrystalline silicon films 33, 31, 30. To do.

Next, as shown in FIG. 10, the semiconductor substrate 1
A silicon nitride film is deposited on the silicon oxide film by a CVD method, and then an oxidation treatment is performed to form a silicon oxide film on the surface of the silicon nitride film, thereby forming a dielectric film 36 including the silicon oxide film and the silicon nitride film. It is formed on the surface of the storage electrode SN of the memory cell. After that, a polycrystalline silicon film 37 is deposited on the semiconductor substrate 1 by the CVD method, and then the polycrystalline silicon film 37 is etched using a photoresist as a mask to etch the plate electrode PL (fifth conductive film) of the memory cell. ) Is formed.

Next, as shown in FIG. 11, the semiconductor substrate 1
CVD of a silicon oxide film 38 and a BPSG film 39 on top
Then, the surface of the BPSG film 39 is flattened by a reflow process at 900 to 950 ° C.
Then, using the photoresist as a mask, B of the memory cell is
A fourth contact hole 40 is formed on the plate electrode PL of the memory cell by sequentially etching the PSG film 39 and the silicon oxide film 38. At the same time, the BPSG film 39, the silicon oxide film 38, and the dielectric film 36 in the logic portion are sequentially etched to form the fourth contact hole 40 on the second wiring layer LM2.
The surface of the BPSG film 39 is flattened by CMP (Ch
The emical mechanical polishing method may be used together.

Next, as shown in FIG. 12, the semiconductor substrate 1
On top, for example, a titanium (Ti) film, titanium nitride (TiN)
Film, aluminum (Al) film, and titanium (Ti) film are sequentially deposited to form a laminated metal film 41, and the metal film 41 is etched using a photoresist as a mask to form a first wiring of the memory cell. Layer MM1 (6th
A conductive film) and a third wiring layer LM3 (sixth conductive film) of the logic portion are formed.

Although not shown in the figure, the first wiring layer MM1 of the memory cell may be connected to the bit line BL of the memory cell, and the third wiring layer LM3 of the logic section may be connected.
May be connected to the p-type well, the n-type well 3, the p-type semiconductor region 12 of the p-channel type MISFET Qs, the n-type semiconductor region of the n-channel type MISFET, the gate electrode 10 or the first wiring layer in the logic portion.

The Ti film located at the bottom of the metal film 41 of the laminated structure is reacted with the polycrystalline silicon film or the silicon single crystal constituting the semiconductor substrate 1 which is in contact with the Ti film, and titanium is contacted with the contact portion. silicide (TiSi _X; x
= 1 to 2) film may be formed to reduce the contact resistance of the metal film 41. In this case, for example, a Ti film with a thickness of 30 nm and Ti
After sequentially depositing an N film in a thickness of 50 nm, a lamp anneal process is performed at a temperature of about 650 ° C. for about 1 minute to obtain TiS.
The i _x film is formed. Further, the Al film may be embedded in the fourth contact hole 40 while being heated at 400 to 450 ° C. during its deposition.

Next, on the semiconductor substrate 1, TEOS (Tetra
A silicon oxide film is deposited by a plasma CVD method using Ethyl Ortho Silicate (Si (OC ₂ H ₅ ) ₄ ) as a source, and then SOG (Spin On Glass) is formed on the semiconductor substrate 1.
Apply the film. Thereafter, the SOG film is etched back by the RIE method to perform a flattening process.
An interlayer insulating film 42 having a three-layer structure is provided by depositing a silicon oxide film by a plasma CVD method using EOS as a source. Then, the interlayer insulating film 42 is etched using the photoresist as a mask to form a through hole (not shown).

Next, on the semiconductor substrate 1, for example, Ti
After forming a metal film 43 having a laminated structure in which a film, a TiN film, an Al film and a Ti film are sequentially deposited, the metal film 43 is etched by using a photoresist as a mask.
The second wiring layer MM2 (seventh conductive film) of the memory cell and the fourth wiring layer LM4 (seventh conductive film) of the logic portion are formed.

Finally, by covering the surface of the semiconductor substrate 1 with the passivation film 44, the memory cells of the DRAM section and the p-channel type MISFETQ of the logic section of the logic embedded DRAM of the first embodiment shown in FIG.
s is completed.

As described above, according to the first embodiment, the polycrystalline silicon films 33, 31, 30 forming a part of the storage electrode SN of the information storage capacitive element of the memory cell are arranged in the logic portion. By this, it is possible to reduce the elevation difference between the memory cell array of the DRAM section and the logic section,
Further, the polycrystalline silicon films 33, 31, 30 can be used as the second wiring layer LM2 of the logic section.

(Embodiment 2) The left side of FIG. 13 is a cross-sectional view of an essential part of a semiconductor substrate showing a memory cell of a DRAM portion in a logic embedded DRAM according to another embodiment of the present invention, and the right side of FIG. FIG. 8 is a sectional view of the essential part of the semiconductor substrate, showing the p-channel type MISFET Qs of the logic part.

The structure of the memory cell of the DRAM part is the same as the structure of the memory cell of FIG. 1 shown in the first embodiment, but the structure of the logic part is different from the structure of the logic part of FIG. The polycrystalline silicon film 37 forming the plate electrode PL of the information storage capacitive element of the cell constitutes the second wiring layer LM2 of the logic portion.

That is, in the logic section, the semiconductor substrate 1
The first conductive film (WSi ₂ film 7 and polycrystalline silicon film 6) deposited on the main surface of the gate electrode 10 constitutes the gate electrode 10 of the p-channel type MISFET Qs and the gate electrode (not shown) of the n-channel type MISFET. A third conductive film (WSi ₂ film 25 and polycrystalline silicon films 24, 2) forming the bit line BL of the memory cell deposited on the first conductive film
1) forms a first wiring layer (not shown), and a fifth conductive film (polycrystalline silicon film) that forms a plate electrode PL of the information storage capacitor element of the memory cell deposited on the third conductive film. 37) constitutes the second wiring layer LM2, and the sixth conductive film (metal film 41) deposited on the upper layer of the fifth conductive film constitutes the third wiring layer LM3, which is deposited on the upper layer of the sixth conductive film. The seventh conductive film (metal film 43) thus formed constitutes the fourth wiring layer LM4.

As described above, according to the second embodiment, by disposing the polycrystalline silicon film 37 forming the plate electrode PL of the information storage capacitive element of the memory cell in the logic portion, the memory cell array of the DRAM portion is formed. And the elevation difference between the logic section and the logic section can be relaxed, and the polycrystalline silicon film 37 can be used as the second wiring layer LM2 of the logic section.

(Embodiment 3) The left side of FIG. 14 is a cross-sectional view of an essential part of a semiconductor substrate showing a memory cell of a DRAM part in a logic embedded DRAM according to another embodiment of the present invention, and the right side of FIG. FIG. 8 is a sectional view of the essential part of the semiconductor substrate, showing the p-channel type MISFET Qs of the logic part.

The structure of the memory cell of the DRAM part is the same as the structure of the memory cell of FIG. 1 described in the first embodiment, but the structure of the logic part is different from the structure of the logic part of FIG. The second wiring layer LM2 of the logic portion is formed by the polycrystalline silicon film 37 forming the plate electrode PL of the information storage capacitive element of the cell, and the dielectric film 36 is formed under the polycrystalline silicon film 37 via the dielectric film 36. Polycrystalline silicon films 33, 31, 30 forming a part of the storage electrode SN of the information storage capacitive element are arranged.

That is, in the logic section, the semiconductor substrate 1
The first conductive film (WSi ₂ film 7 and polycrystalline silicon film 6) deposited on the main surface of the gate electrode 10 constitutes the gate electrode 10 of the p-channel type MISFET Qs and the gate electrode (not shown) of the n-channel type MISFET. A third conductive film (WSi ₂ film 25 and polycrystalline silicon films 24, 2) forming the bit line BL of the memory cell deposited on the first conductive film
1) forms a first wiring layer (not shown), and a fourth 'conductive film (a part of the storage electrode SN of the information storage capacitor of the memory cell deposited on the third conductive film is formed on the third conductive film). A fifth conductive film (polycrystalline silicon film 37) is formed by arranging the polycrystalline silicon films 33, 31, 30 and forming the plate electrode PL of the information storage capacitor of the memory cell deposited on the fourth conductive film. ) Constitutes the second wiring layer LM2, the sixth conductive film (metal film 41) deposited on the upper layer of the fifth conductive film constitutes the third wiring layer LM3, which is deposited on the upper layer of the sixth conductive film. The seventh conductive film (metal film 43) constitutes the fourth wiring layer LM4.

As described above, according to the third embodiment, the polycrystalline silicon films 33, 31, 30 and the plate electrode PL forming a part of the storage electrode SN of the information storage capacitive element of the memory cell are formed. By arranging a laminated film made of the polycrystalline silicon film 37 in the logic portion,
The elevation difference between the memory cell array of the above portion and the logic portion can be reduced, and the polycrystalline silicon film 37 forming the plate electrode PL can be used as the second wiring layer LM2 of the logic portion.

(Embodiment 4) The left side of FIG. 15 is a cross-sectional view of a main part of a semiconductor substrate showing a memory cell of a DRAM portion in a logic embedded DRAM according to another embodiment of the present invention, and the right side of FIG. FIG. 8 is a sectional view of the essential part of the semiconductor substrate, showing the p-channel type MISFET Qs of the logic part.

In the memory cell of the DRAM portion, the first conductive film (WSi ₂ film 7 and polycrystalline silicon film 6) deposited on the main surface of the semiconductor substrate 1 is used as a memory cell selection MISFET.
The gate electrode 10 of Qt is formed, and the second conductive film (polycrystalline silicon film 19) deposited on the upper layer of the first conductive film forms the plug PG of the capacitive element for information storage. Third conductive film (tungsten (W) film 4 deposited on the
7, the TiN film 46 and the Ti film 45) form the bit line BL, and the fourth conductive film (W film 49) deposited on the third conductive film forms the storage electrode SN of the information storage capacitive element. , A fifth conductive film (T
The plate electrode PL of the capacitive element for storing information by the iN film 50)
And the sixth conductive film (metal film 41) deposited on the fifth conductive film constitutes the first wiring layer MM1.
The seventh conductive film (metal film 43) deposited on the conductive film constitutes the second wiring layer MM2.

On the other hand, in the logic portion, the gate electrode 10 of the p-channel type MISFET Qs and the n-channel type MISFET are formed by the first conductive film (WSi ₂ film 7 and polycrystalline silicon film 6) deposited on the main surface of the semiconductor substrate 1. The third conductive film (W film 47, TiN film 46, and Ti film 45) forming the gate electrode (not shown) and forming the bit line BL of the memory cell deposited on the first conductive film is formed of the first conductive film. The second wiring layer LM2 is constituted by the fourth conductive film (W film 49) which constitutes the wiring layer LM1 and which constitutes the storage electrode SN of the information storage capacitive element of the memory cell deposited on the third conductive film. , The sixth conductive film (metal film 41) deposited on the upper layer of the fourth conductive film constitutes the third wiring layer LM3, and the seventh conductive film (metal film 43) deposited on the upper layer of the sixth conductive film. By configuring the fourth wiring layer LM4 That.

Next, the memory cell of the DRAM section shown in FIG. 15 and the p-channel type MISFET of the logic section are shown.
A method of manufacturing Qs will be described with reference to FIGS.

First, referring to FIG.
~ Similar to the manufacturing method described with reference to FIG. 5, the gate electrode 10 (first conductive film) and the plug PG (second conductive film) are formed in the memory cell of the DRAM part, and the gate electrode 10 (first conductive film) is formed in the logic part. 1 conductive film) is formed.

Next, as shown in FIG. 16, the semiconductor substrate 1
After the silicon oxide film 20 is deposited on the silicon oxide film by the CVD method, the silicon oxide film 2 is formed using the photoresist as a mask.
0, the BPSG film 15, the silicon oxide film 14, and the insulating film in the same layer as the gate insulating film 5 are sequentially etched, so that the second n-type semiconductor region 22 formed after the other of the memory cell selecting MISFET Qt and P-type semiconductor region 1 of p-channel type MISFETQs in the logic section
A second contact hole 23 is formed on the surface 2.

At the time of forming the second contact hole 23, although not shown in the drawing, on the p-type well of the logic portion, on the n-type well 3, on the n-type semiconductor region of the n-channel type MISFET, or A contact hole may be formed on the gate electrode 10.

Next, for example, P is ion-implanted into the memory cell using the photoresist as a mask to form the other second n-type semiconductor region 22 of the memory cell selecting MISFET Qt, and then, Ti is formed on the semiconductor substrate 1. Film 45, TiN film 4
6 and W film 47 are sequentially deposited. Then, the W film 47, the TiN film 46, and the Ti film 45 are sequentially etched using the photoresist as a mask, whereby the W film 4 is formed.
7, the bit line BL (third conductive film) of the memory cell including the TiN film 46 and the Ti film 45, and the first wiring layer LM1 (third conductive film) of the logic portion are formed.

This first wiring layer LM1 is not shown in the figure, except for the p-type semiconductor region 12 of the p-channel MISFET Qs of the logic section shown in FIG.
Type well, n-type well 3, n-type semiconductor region of n-channel type MISFET, and gate electrode 10.

Next, as shown in FIG. 17, the semiconductor substrate 1
After the silicon oxide film 48 is formed thereon by a method such as a plasma CVD method or an ECR (Electron Cyclotron Resonance) CVD method that can be deposited at a temperature of 500 ° C. or lower, the silicon oxide film 48 of the memory cell is masked with a photoresist. By sequentially etching the silicon oxide film 20 and the silicon oxide film 20, the first contact hole 1
A third contact hole 32 is formed on the plug PG provided in No. 8.

Then, after depositing the W film 49 on the semiconductor substrate 1, the W film 49 is etched by using the photoresist as a mask to etch the storage electrode SN (the fourth conductive film) of the information storage capacitor in the memory cell. ) Is formed, and at the same time, the second wiring layer LM2 (fourth conductive film) of the logic portion is formed.

Although not shown in the drawing, when forming the third contact hole 32, on the p-type well of the logic portion, on the n-type well 3, and on the p-type semiconductor region 12 of the p-channel type MISFET. , N of n-channel type MISFET
Type semiconductor region, gate electrode 10 or first wiring layer L
A contact hole is formed on M1 and the second wiring layer LM2 is formed.
Are the p-type well in the logic part, the n-type well 3, the p-type semiconductor region 12 of the p-channel type MISFET, and the n-channel type M.
It may be connected to the n-type semiconductor region of the ISFET, the gate electrode 10 or the first wiring layer LM1.

Next, as shown in FIG. 18, the semiconductor substrate 1
A tantalum oxide (Ta ₂ O ₅ ) film is deposited thereon by a CVD method, and a dielectric film 36 made of the Ta ₂ O ₅ film is formed on the surface of the storage electrode SN of the memory cell. After that, a TiN film 50 is deposited on the semiconductor substrate 1 by the CVD method, and then the TiN film 50 is etched using a photoresist as a mask to form a plate electrode PL (fifth conductive film) of the memory cell. .

Next, the silicon oxide film 5 is formed on the semiconductor substrate 1.
1 is formed by a method capable of depositing at a temperature of 500 ° C. or lower, such as a plasma CVD method or an ECRCVD method. After that, by etching the silicon oxide film 51 of the memory cell using the photoresist as a mask,
A second contact hole 40 is formed on the plate electrode PL of the memory cell, and at the same time, the silicon oxide film 51 and the dielectric film 36 in the logic portion are sequentially etched to form a second wiring formed of the W film 49 in the logic portion. Layer LM2
A fourth contact hole 40 is formed thereover.

Next, similarly to the manufacturing method described in the first embodiment, the first wiring layer MM1 (sixth conductive film) of the memory cell and the third wiring layer LM3 (sixth conductive film) of the logic portion are formed. Then, the second wiring layer MM2 of the memory cell is formed.
(Seventh conductive film) and fourth wiring layer LM4 of the logic section
By forming the (seventh conductive film), the memory cell and the logic part of the DRAM part of the logic embedded DRAM of the fourth embodiment shown in FIG. 15 are completed.

As described above, according to the fourth embodiment, by arranging the W film 49 forming the storage electrode SN of the information storage capacitor of the memory cell in the logic portion, the DR
The elevation difference between the memory cell array in the AM section and the logic section can be reduced, and the W film 49 can be used as the second wiring layer LM2 in the logic section. Furthermore, the W films 47 and T that form the bit line BL of the memory cell
By using a laminated film composed of the iN film 46 and the Ti film 45 for the wiring layer of the logic portion, this wiring layer can be connected to the well region and the semiconductor region of the MISFET regardless of the conductivity type. It is possible to increase the degree of freedom.

(Embodiment 5) The left side of FIG. 19 is a cross-sectional view of a main part of a semiconductor substrate showing a memory cell of a DRAM portion in a logic embedded DRAM according to another embodiment of the present invention, and the right side of FIG. FIG. 8 is a sectional view of the essential part of the semiconductor substrate, showing the p-channel type MISFET Qs of the logic part.

The structure of the memory cell of the DRAM part is the same as the structure of the memory cell of FIG. 15 shown in the fourth embodiment, but the structure of the logic part is different from the structure of the logic part of FIG. The TiN film 50 forming the plate electrode PL of the information storage capacitive element of the cell constitutes the second wiring layer LM2 of the logic portion.

That is, in the logic section, the semiconductor substrate 1
The first conductive film (WSi ₂ film 7 and polycrystalline silicon film 6) deposited on the main surface of the gate electrode 10 constitutes the gate electrode 10 of the p-channel type MISFET Qs and the gate electrode (not shown) of the n-channel type MISFET. The third conductive film (W film 47, TiN film 46, and Ti film 45) forming the bit line BL of the memory cell deposited on the first conductive film is the first
The plate electrode PL of the information storage capacitive element of the memory cell, which constitutes the wiring layer LM1 and is deposited on the upper layer of the third conductive film.
The fifth conductive film (TiN film 50) forming the second wiring layer L
The sixth conductive film (metal film 41) which constitutes M2 and is deposited on the upper layer of the fifth conductive film constitutes the third wiring layer LM3, and the seventh conductive film (metal which is deposited on the upper layer of the sixth conductive film (metal). Membrane 43)
Constitute a fourth wiring layer LM4.

As described above, according to the fifth embodiment, by arranging the TiN film 50 forming the plate electrode PL of the information storage capacitive element of the memory cell in the logic section, the memory cell array of the DRAM section and the logic section are formed. It is possible to reduce the elevation difference between the TiN film and the TiN film 50.
Can be used as the second wiring layer LM2 of the logic section. Further, W that constitutes the bit line BL of the memory cell
By using the laminated film including the film 47, the TiN film 46, and the Ti film 45 as the wiring layer of the logic portion, the wiring layer can be connected to the well region and the semiconductor region of the MISFET regardless of the conductivity type. It is possible to increase the degree of freedom in circuit design.

(Sixth Embodiment) The left side of FIG. 20 is a cross-sectional view of an essential part of a semiconductor substrate showing a memory cell of a DRAM part in a logic embedded DRAM according to another embodiment of the present invention, and the right side of FIG. FIG. 8 is a sectional view of the essential part of the semiconductor substrate, showing the p-channel type MISFET Qs of the logic part.

The structure of the memory cell of the DRAM part is the same as the structure of the memory cell of FIG. 15 shown in the fourth embodiment, but the structure of the logic part is different from that of the logic part of FIG. The W film 49 forming the storage electrode SN of the information storage capacitive element of the cell constitutes the second wiring layer LM2 of the logic part, and the TiN film 50 forming the plate electrode PL of the information storage capacitive element of the memory cell forms the logic. Part of the third wiring layer LM3.

That is, in the logic section, the semiconductor substrate 1
The first conductive film (WSi ₂ film 7 and polycrystalline silicon film 6) deposited on the main surface of the gate electrode 10 constitutes the gate electrode 10 of the p-channel type MISFET Qs and the gate electrode (not shown) of the n-channel type MISFET. The third conductive film (W film 47, TiN film 46, and Ti film 45) forming the bit line BL of the memory cell deposited on the first conductive film is the first
The second wiring layer LM2 is constituted by the fourth conductive film (W film 49) which constitutes the wiring layer LM1 and which constitutes the storage electrode SN of the information storage capacitive element of the memory cell deposited on the third conductive film. The fifth conductive film (TiN film 50) forming the plate electrode PL of the information storage capacitor of the memory cell deposited on the fourth conductive film constitutes the third wiring layer LM3. The sixth conductive film (metal film 4) deposited on the upper layer of
1) constitutes the fourth wiring layer LM4, and the seventh conductive film (metal film 43) deposited on the sixth conductive film is used as the fifth wiring layer L.
It constitutes M5.

As described above, according to the sixth embodiment, the W film 49 forming the storage electrode SN of the information storage capacitor of the memory cell and the TiN film 50 forming the plate electrode PL are arranged in the logic portion. As a result, the elevation difference between the memory cell array of the DRAM section and the logic section can be reduced, and the W film 49 forming the storage electrode SN can be reduced.
Can be used as the second wiring layer LM2 of the logic part, and the TiN film 50 forming the plate electrode PL can be used as the third wiring layer LM3 of the logic part. Further, by using a laminated film composed of the W film 47, the TiN film 46 and the Ti film 45 forming the bit line BL of the memory cell as the wiring layer of the logic portion, the well region and the semiconductor region of the MISFET are irrespective of the conductivity type. Since this wiring layer can be connected to, the degree of freedom in circuit design can be increased.

(Embodiment 7) The left side of FIG. 21 is a cross-sectional view of a main part of a semiconductor substrate showing a memory cell of a DRAM portion in a logic embedded DRAM according to another embodiment of the present invention, and the right side of FIG. FIG. 8 is a sectional view of the essential part of the semiconductor substrate, showing the p-channel type MISFET Qs of the logic part.

The structure of the memory cell of the DRAM part is the same as the structure of the memory cell of FIG. 15 shown in the fourth embodiment, but the structure of the logic part is different from the structure of the logic part of FIG. The TiN film 50 forming the plate electrode PL of the information storage capacitive element of the cell constitutes the second wiring layer LM2 of the logic portion, and further the TiN film 50 is formed.
A W film 49 forming the storage electrode SN of the information storage capacitive element is disposed as a lower layer via the dielectric film 36.

That is, in the logic section, the semiconductor substrate 1
The first conductive film (WSi ₂ film 7 and polycrystalline silicon film 6) deposited on the main surface of the gate electrode 10 constitutes the gate electrode 10 of the p-channel type MISFET Qs and the gate electrode (not shown) of the n-channel type MISFET. The third conductive film (W film 47, TiN film 46, and Ti film 45) forming the bit line BL of the memory cell deposited on the first conductive film is the first
A fourth conductive film (W film 49) forming the wiring layer LM1 and forming the storage electrode SN of the information storage capacitor of the memory cell deposited on the third conductive film is arranged. The fifth conductive film (TiN film 5) forming the plate electrode PL of the information storage capacitive element of the memory cell deposited on the upper layer.
0) constitutes the second wiring layer LM2, and the sixth conductive film (metal film 41) deposited on the fifth conductive film is used as the third wiring layer L.
The seventh conductive film (the metal film 43) deposited on the upper layer of the sixth conductive film constitutes the fourth wiring layer LM4.

As described above, according to the seventh embodiment, the W film 49 forming the storage electrode SN of the information storage capacitance element of the memory cell and the TiN film 50 forming the plate electrode PL are arranged in the logic portion. As a result, the difference in elevation between the memory cell array of the DRAM section and the logic section can be reduced, and the Ti forming the plate electrode PL can be reduced.
The N film 50 can be used as the second wiring layer LM2 of the logic section. Further, by using a laminated film composed of the W film 47, the TiN film 46 and the Ti film 45 forming the bit line BL of the memory cell as the wiring layer of the logic portion, the well region and the semiconductor region of the MISFET are irrespective of the conductivity type. Since this wiring layer can be connected to, the degree of freedom in circuit design can be increased.

Although the invention made by the present inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments and various modifications can be made without departing from the scope of the invention. It goes without saying that it can be changed.

For example, in the above-described embodiment, the conductive film forming the bit line of the memory cell of the DRAM section is arranged in the logic section and used as the first wiring layer, but it is not necessarily arranged in the logic section and used as the wiring layer. No need to use.

In the above embodiment, the method of manufacturing the memory cell having the COB structure in which the information storage capacitive element is arranged above the bit line has been described. However, the bit line is arranged above the information storage capacitive element. It is also applicable to memory cells.

In the first to third embodiments, the memory cell of the DRAM using the cylindrical storage electrode as the information storage capacitor and the manufacturing method thereof have been described, but the present invention is not limited to the cylindrical type. For example, it is also applicable to a memory cell using a fin type or a simple stacked type storage electrode.

Further, in the above fourth to seventh embodiments, D using a simple stacked type storage electrode as the information storage capacitor element is used.
Although the memory cell of the RAM and the manufacturing method thereof have been described,
The present invention is not limited to the simple stacked type, and can be applied to, for example, a memory cell using a fin type or a cylindrical type storage electrode.

In the first to third embodiments, the two-layer film made of the silicon oxide film and the silicon nitride film is used as the dielectric film of the information storage capacitive element, but the present invention is not limited to this, and the tantalum oxide film is not limited thereto. A film, a high dielectric film such as a PZT (PbZrTiO _x ) film, or a laminated film of these films may be used. In this case, in order to prevent an increase in the leak current of the high dielectric film, the heat treatment performed on the semiconductor substrate after the high dielectric film is deposited needs to be 500 ° C. or lower. For this reason,
For example, when a tantalum oxide film is used for the dielectric film, a titanium nitride film deposited by the CVD method is used for the plate electrode, and a plasma CVD method or ECRCVD is used for the interlayer insulating film deposited above the tantalum oxide film. An insulating film that can be deposited at a low temperature of 500 ° C. or lower, such as a deposition method, is used.

Further, in the above-mentioned embodiment, the memory cells and the logic part of the DRAM part and the manufacturing methods thereof are described. However, the structure and the manufacturing method shown in the description of the logic part are also applied to the peripheral circuits of the DRAM part. It is possible.

[0101]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, in the logic-embedded DRAM, the elevation difference between the memory cell array in the DRAM section and the logic section or the memory cell array in the DRAM section and the DRA.
Since it is possible to set the altitude difference between the peripheral circuit of the M section and the peripheral circuit within the allowable range from the depth of focus of the lithography technique,
It is possible to improve the processing accuracy in the manufacturing process after the information storage capacitive element of the memory cell is formed.

Further, according to the present invention, since the wiring layer used in the peripheral circuit of the logic section or the DRAM section can be formed in the step of manufacturing the information storage capacitor element of the memory cell, the step in the wiring step can be performed. The number can be reduced, and the throughput of the logic embedded DRAM can be improved.

[Brief description of drawings]

FIG. 1 is a logic mixed DR that is an embodiment of the present invention.
It is a principal part sectional view of a semiconductor substrate which shows AM.

FIG. 2 is a logic mixed DR according to an embodiment of the present invention.
FIG. 6 is a main-portion cross-sectional view of the semiconductor substrate, showing the method for manufacturing the AM.

FIG. 3 is a logic mixed DR according to an embodiment of the present invention.
FIG. 6 is a main-portion cross-sectional view of the semiconductor substrate, showing the method for manufacturing the AM.

FIG. 4 is a logic mixed DR that is an embodiment of the present invention.
FIG. 6 is a main-portion cross-sectional view of the semiconductor substrate, showing the method for manufacturing the AM.

FIG. 5 is a logic mixed DR that is an embodiment of the present invention.
FIG. 6 is a main-portion cross-sectional view of the semiconductor substrate, showing the method for manufacturing the AM.

FIG. 6 is a logic mixed DR that is an embodiment of the present invention.
FIG. 6 is a main-portion cross-sectional view of the semiconductor substrate, showing the method for manufacturing the AM.

FIG. 7 is a logic mixed DR according to an embodiment of the present invention.
FIG. 6 is a main-portion cross-sectional view of the semiconductor substrate, showing the method for manufacturing the AM.

FIG. 8 is a logic mixed DR that is an embodiment of the present invention.
FIG. 6 is a main-portion cross-sectional view of the semiconductor substrate, showing the method for manufacturing the AM.

FIG. 9 is a logic mixed DR according to an embodiment of the present invention.
FIG. 6 is a main-portion cross-sectional view of the semiconductor substrate, showing the method for manufacturing the AM.

FIG. 10 is a logic mixed-mounting D according to an embodiment of the present invention.
FIG. 9 is a cross-sectional view of a main portion of a semiconductor substrate showing a method for manufacturing a RAM.

FIG. 11 is a block diagram showing a logic embedded D according to an embodiment of the present invention.
FIG. 9 is a cross-sectional view of a main portion of a semiconductor substrate showing a method for manufacturing a RAM.

FIG. 12 is a logic-embedded D according to an embodiment of the present invention.
FIG. 9 is a cross-sectional view of a main portion of a semiconductor substrate showing a method for manufacturing a RAM.

FIG. 13 is a fragmentary cross-sectional view of a semiconductor substrate showing a logic embedded DRAM according to another embodiment of the present invention.

FIG. 14 is a fragmentary cross-sectional view of a semiconductor substrate showing a logic embedded DRAM according to another embodiment of the present invention.

FIG. 15 is a fragmentary cross-sectional view of a semiconductor substrate showing a logic embedded DRAM according to another embodiment of the present invention.

FIG. 16 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a logic embedded DRAM according to another embodiment of the present invention.

FIG. 17 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a logic embedded DRAM according to another embodiment of the present invention.

FIG. 18 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a logic embedded DRAM according to another embodiment of the present invention.

FIG. 19 is a cross-sectional view of essential parts of a semiconductor substrate showing a logic-embedded DRAM according to another embodiment of the present invention.

FIG. 20 is a fragmentary cross-sectional view of a semiconductor substrate showing a logic embedded DRAM according to another embodiment of the present invention.

FIG. 21 is a fragmentary cross-sectional view of a semiconductor substrate showing a logic-embedded DRAM according to another embodiment of the present invention.

[Explanation of symbols]

1 semiconductor substrate 2 p-type well 3 n-type well 4 field insulating film 5 gate insulating film 6 polycrystalline silicon film 7 tungsten silicide film 8 silicon oxide film 9 silicon nitride film 10 gate electrode 11 silicon oxide film 12 p-type semiconductor region (source Region, drain region) 13 sidewall spacer 14 silicon oxide film 15 BPSG film 16 polycrystalline silicon film 17 first n-type semiconductor region 18 first contact hole 19 polycrystalline silicon film 20 silicon oxide film 21 polycrystalline silicon film 22 Second n-type semiconductor region 23 Second contact hole 24 Polycrystalline silicon film 25 Tungsten silicide film 26 Silicon oxide film 27 Silicon nitride film 28 BPSG film 29 Silicon oxide film 30 Polycrystalline silicon film 31 Polycrystalline silicon film (sidewall Spacer) 32 Third contact hole 33 Polycrystalline silicon film 34 BPSG film 35 Polycrystalline silicon film 36 Dielectric film 37 Polycrystalline silicon film 38 Silicon oxide film 39 BPSG film 40 Fourth contact hole 41 Metal film 42 Interlayer insulation film 43 Metal Film 44 Passivation Film 45 Titanium Film 46 Titanium Nitride Film 47 Tungsten Film 48 Silicon Oxide Film 49 Tungsten Film 50 Titanium Nitride Film 51 Silicon Oxide Film Qt MISFET for memory cell selection (memory cell of DRAM part) Qs p channel type MISFET ( Logic part) PG plug BL bit line SN storage electrode PL plate electrode MM1 first wiring layer (memory cell of DRAM part) MM2 second wiring layer (memory cell of DRAM part) LM1 first wiring layer (logic part) LM2 Second wiring layer (logic unit) LM3 third wiring layer (logic unit) LM4 fourth wiring layer (logic unit) LM5 fifth wiring layer (logic unit)

Claims (9)

[Claims] 1. A semiconductor integrated circuit device having a DRAM section including a memory cell array and peripheral circuits and a logic section, wherein a first conductive film forming a storage electrode of an information storage capacitive element of a memory cell of the DRAM section is formed, A semiconductor integrated circuit device, which is arranged in at least one of a peripheral circuit of the DRAM section and the logic section and is used as a wiring layer. 2. In a semiconductor integrated circuit device having a DRAM section including a memory cell array and peripheral circuits and a logic section, a second conductive film forming a plate electrode of an information storage capacitive element of a memory cell of the DRAM section, A semiconductor integrated circuit device, which is arranged in at least one of a peripheral circuit of the DRAM section and the logic section and is used as a wiring layer. 3. A semiconductor integrated circuit device having a DRAM section including a memory cell array and a peripheral circuit, and a logic section, wherein a first conductive film forming a storage electrode of an information storage capacitive element of a memory cell of the DRAM section and the first conductive film are provided. A second conductive film forming a plate electrode of an information storage capacitive element of a memory cell of the DRAM section is arranged in at least one of a peripheral circuit of the DRAM section and the logic section and used as a wiring layer. Semiconductor integrated circuit device. 4. A semiconductor integrated circuit device having a DRAM section including a memory cell array and a peripheral circuit and a logic section, wherein a storage electrode having a laminated structure is formed with a dielectric film of an information storage capacitive element of a memory cell of the DRAM section sandwiched therebetween. The first conductive film forming the second conductive film and the second plate forming the plate electrode
Is disposed in at least one of the peripheral circuit of the DRAM part and the logic part, and the second conductive film is used as a wiring layer of at least one of the peripheral circuit of the DRAM part and the logic part. A characteristic semiconductor integrated circuit device. 5. In a semiconductor integrated circuit device having a DRAM section including a memory cell array and peripheral circuits and a logic section, a first conductive film forming a storage electrode of an information storage capacitive element of a memory cell of the DRAM section, and the first conductive film. Third configuration of bit line of memory cell of DRAM part
2. The semiconductor integrated circuit device according to claim 1, wherein the conductive film is disposed in at least one of the peripheral circuit of the DRAM section and the logic section and is used as a wiring layer. 6. A semiconductor integrated circuit device having a DRAM section including a memory cell array and peripheral circuits and a logic section, a second conductive film forming a plate electrode of an information storage capacitive element of a memory cell of the DRAM section, and the semiconductor device. A semiconductor integrated circuit device characterized in that a third conductive film forming a bit line of a memory cell of a DRAM section is arranged in at least one of a peripheral circuit of the DRAM section and the logic section and used as a wiring layer. 7. A semiconductor integrated circuit device having a DRAM section including a memory cell array and a peripheral circuit and a logic section, a first conductive film forming a storage electrode of an information storage capacitive element of a memory cell of the DRAM section, The second conductive film forming the plate electrode of the information storage capacitor of the memory cell of the DRAM section and the third conductive film forming the bit line of the memory cell of the DRAM section are connected to the peripheral circuit of the DRAM section or A semiconductor integrated circuit device, which is arranged in at least one of the logic parts and is used as a wiring layer. 8. In a semiconductor integrated circuit device having a DRAM section including a memory cell array and peripheral circuits and a logic section, a storage electrode having a laminated structure sandwiching a dielectric film of an information storage capacitive element of a memory cell of the DRAM section is provided. The first conductive film forming the second conductive film and the second plate forming the plate electrode
And a third conductive film forming a bit line of a memory cell of the DRAM section are arranged in at least one of a peripheral circuit of the DRAM section and the logic section, and the second conductive film and the third conductive film are provided. The conductive film of the DRAM
A semiconductor integrated circuit device, which is used as a peripheral circuit of at least one part or a wiring layer of at least one of the logic parts. 9. The semiconductor integrated circuit device according to claim 5, wherein the third conductive film is a stacked film or a tungsten film formed of a tungsten silicide film and a polycrystalline silicon film, A semiconductor integrated circuit device comprising a laminated film including a titanium nitride film and a titanium film.