KR100322888B1 - Method for fabricating a bipolar junction transistor within merged memory logic device - Google Patents
Method for fabricating a bipolar junction transistor within merged memory logic device Download PDFInfo
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- KR100322888B1 KR100322888B1 KR1019990065201A KR19990065201A KR100322888B1 KR 100322888 B1 KR100322888 B1 KR 100322888B1 KR 1019990065201 A KR1019990065201 A KR 1019990065201A KR 19990065201 A KR19990065201 A KR 19990065201A KR 100322888 B1 KR100322888 B1 KR 100322888B1
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Abstract
본 발명은 메모리 로직 복합 반도체 소자의 바이폴라 접합 트랜지스터 제조방법에 관한 것으로서, 특히, 메모리 소자, 주변회로 및 바이폴라 접합 트랜지스터를 포함하는 메모리 로직 복합 반도체 소자의 바이폴라 접합 트랜지스터 형성방법을 보여 준다. 반도체소자의 주변회로 영역의 소오스/드레인 영역 형성과 함께 바이폴라 접합 트랜지스터의 베이스 영역 및 에미터 영역을 형성한다. 그리고, 바이폴라 접합 트랜지스터의 컬렉터 영역을 형성한 후에, 메모리 소자, 주변회로 및 바이폴라 접합 트랜지스터의 전극들을 형성하므로 신롸성이 있고 다양한 MML소자를 개발하도록 하는 매우 유용하고 효과적인 발명에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a bipolar junction transistor of a memory logic composite semiconductor device, and more particularly, to a method of forming a bipolar junction transistor of a memory logic composite semiconductor device including a memory device, a peripheral circuit, and a bipolar junction transistor. The source region and the drain region of the peripheral circuit region of the semiconductor device are formed together with the base region and the emitter region of the bipolar junction transistor. Further, after forming the collector region of the bipolar junction transistor, the electrodes of the memory device, the peripheral circuit and the bipolar junction transistor are formed so that the invention relates to a very useful and effective invention for developing various MML devices.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로서, 특히 바이폴라 접합 트랜지스터의 컬렉터 영역을 형성한 후에, 메모리 소자, 주변회로 및 바이폴라 접합 트랜지스터의 전극들을 형성하므로 신롸성이 있고 다양한 MML소자를 개발하도록 하는 메모리 로직 복합 반도체 소자의 바이폴라 접합 트랜지스터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, after forming a collector region of a bipolar junction transistor, a memory device, a peripheral circuit, and electrodes of a bipolar junction transistor are formed, thereby making it possible to develop a reliable and diverse MML device. The present invention relates to a bipolar junction transistor manufacturing method of a logic composite semiconductor device.
일반적으로, 메모리 논리 복합 반도체 소자는, 반도체 소자를 이용하는 시스템의 경박단소, 고성능화 및 저전력화를 달성하기 위하여 디램(DRAM)과 같은 메모리 소자와 이 메모리 소자에 맞는 로직을 하나의 칩에 구현한 것을 말한다. 이와 같은 메모리 논리 복합 반도체 소자에서 로직에만 사용되는 회로가 있는데, 그 중의 하나가 바이폴라 접합 트랜지스터이다.In general, a memory logic composite semiconductor device includes a memory device such as a DRAM and a logic suitable for the memory device in one chip in order to achieve a thin, small, high performance, and low power system of a system using the semiconductor device. Say. In such a memory logic composite semiconductor device, there is a circuit used only for logic, and one of them is a bipolar junction transistor.
상기한 바이폴라 접합 트랜지스터는 모스(MOS) 전계효과 트랜지스터에 비하여 좋은 스위칭 특성 및 증폭 특성을 갖고 있지만, 집적도가 떨어지고 제조 공정이 디램과 다르므로 디램에서는 거의 사용하지 않는다.The bipolar junction transistor has better switching characteristics and amplification characteristics than the MOS field effect transistor. However, the bipolar junction transistor is rarely used in DRAM because of its low integration degree and manufacturing process.
그러나, 메모리 로직 복합 반도체 소자에서는 온도를 조절하는 기능 등을 이용하는 회로내에 바이폴라 접합 트랜지스터를 사용하는 경우가 있으므로, 메모리 로직 복합 반도체 소자내에 바이폴라 접합 트랜지스터를 형성시켜야 하는 경우도 있다.However, in a memory logic composite semiconductor element, a bipolar junction transistor is sometimes used in a circuit using a temperature control function, etc., so that a bipolar junction transistor may be formed in the memory logic composite semiconductor element.
통상적으로, 메모리 로직 복합 반도체 소자내에 형성되는 바이폴라 접합 트랜지스터가 N형 웰 영역, P형 웰 영역 및 N형 웰 영역내의 P형 웰 영역을 이용한 PNP 구조로 형성되는 경우에, 웰에 형성되는 기생적인 바이폴라 접합 트랜지스터를 사용한다.In general, when a bipolar junction transistor formed in a memory logic complex semiconductor device is formed of a PNP structure using an N type well region, a P type well region, and a P type well region in an N type well region, a parasitic formed in the well Bipolar junction transistors are used.
그런데, 이와 같은 경우 웰의 디자인 룰(design rule)에 의해 바이폴라 접합 트랜지스터의 크기가 결정된다. 따라서, 메모리 로직 복합 메모리 소자에서의 각단위 소자내의 다른 부분에 비하여 웰의 디자인 룰이 상대적으로 크기 때문에 바이폴라 접합 트랜지스터가 크게 형성되며, 이로 인하여 전체 회로의 크기를 줄이는데 한계를 나타낸다는 문제점이 있었다.In this case, however, the size of the bipolar junction transistor is determined by a design rule of the well. Therefore, the bipolar junction transistor is large because the design rules of the wells are relatively large compared to other parts of each unit in the memory logic composite memory device, which causes a problem in that the size of the entire circuit is limited.
본 발명은 이러한 점을 감안하여 안출한 것으로서, 바이폴라 접합 트랜지스터의 컬렉터 영역을 형성한 후에, 메모리 소자, 주변회로 및 바이폴라 접합 트랜지스터의 전극들을 형성하므로 신롸성이 있고 다양한 MML소자를 개발하도록 하는 것이 목적이다.SUMMARY OF THE INVENTION The present invention has been made in view of this point, and after forming the collector region of the bipolar junction transistor, the electrodes of the memory device, the peripheral circuit, and the bipolar junction transistor are formed so that the purpose of developing a reliable and diverse MML device is provided. to be.
도 1 및 도 2는 본 발명에 따른 메모리 로직 복합 반도체 소자의 바이폴라 접합 트랜지스터의 베이스 형성공정을 설명하기 위한 단면도이고,1 and 2 are cross-sectional views for explaining a base forming process of a bipolar junction transistor of a memory logic composite semiconductor device according to the present invention;
도 3 및 도 4는 본 발명에 따른 메모리 로직 복합 반도체 소자의 바이폴라 접합 트랜지스터의 에미터 형성공정을 설명하기 위한 단면도이며,3 and 4 are cross-sectional views illustrating an emitter forming process of a bipolar junction transistor of a memory logic composite semiconductor device according to the present invention;
도 5는 본 발명에 따른 메모리 로직 복합 반도체 소자의 디램에서의 게이트 스페이서 형성을 위한 제2 산화막 형성을 설명하기 위한 단면도이고,5 is a cross-sectional view illustrating a second oxide film for forming a gate spacer in a DRAM of a memory logic composite semiconductor device according to the present invention;
도 6 및 도 7은 본 발명에 따른 메모리 로직 복합 반도체 소자의 바이폴라 접합 트랜지스터의 컬렉터 형성공정을 설명하기 위한 단면도이며,6 and 7 are cross-sectional views illustrating a collector forming process of a bipolar junction transistor of a memory logic composite semiconductor device according to the present invention;
도 8은 본 발명에 따른 메모리 로직 복합 반도체 소자의 플러그 형성공정을 설명하기 위한 단면도이고,8 is a cross-sectional view illustrating a plug forming process of a memory logic composite semiconductor device according to the present invention;
도 9는 본 발명에 따른 메모리 로직 복합 반도체 소자의 바이폴라 접합 트랜지스터의 플러그 패턴 형성공정을 설명하기 위한 단면도이며,9 is a cross-sectional view for describing a plug pattern forming process of a bipolar junction transistor of a memory logic composite semiconductor device according to the present invention;
도 10은 본 발명에 따른 메모리 로직 복합 반도체 소자의 전극 형성공정을설명하기 위한 단면도이고,10 is a cross-sectional view illustrating an electrode forming process of a memory logic composite semiconductor device according to the present invention;
도 11은 본 발명에 따른 메모리 로직 복합 반도체 소자의 디램영역을 노출시키는 포토레지스트 패턴 형성공정을 설명하기 위한 단면도이며,11 is a cross-sectional view for describing a photoresist pattern forming process of exposing a DRAM region of a memory logic composite semiconductor device according to the present invention;
도 12는 본 발명에 따른 메모리 로직 복합 반도체 소자의 디램 영역에서의 스페이서 형성공정을 설명하기 위한 단면도이고,12 is a cross-sectional view illustrating a spacer forming process in a DRAM region of a memory logic composite semiconductor device according to the present invention;
도 13은 본 발명에 따른 메모리 로직 복합 반도체 소자의 제1 층간 절연막 형성공정을 설명하기 위한 단면도이며,13 is a cross-sectional view illustrating a process of forming a first interlayer insulating film of a memory logic composite semiconductor device according to the present invention;
도 14는 본 발명에 따른 메모리 로직 복합 반도체 소자의 플러그 패턴 형성공정을 설명하기 위한 단면도이고,14 is a cross-sectional view illustrating a plug pattern forming process of a memory logic composite semiconductor device according to the present invention;
도 15는 본 발명에 따른 메모리 로직 복합 반도체 소자의 바이폴라 접합 트랜지스터의 컬렉터 컨택 형성공정을 설명하기 위한 단면도이며,15 is a cross-sectional view illustrating a collector contact forming process of a bipolar junction transistor of a memory logic complex semiconductor device according to the present invention;
도 16의 본 발명에 따른 메모리 로직 복합 반도체 소자의 전극 형성공정을 설명하기 위한 단면도이다.16 is a cross-sectional view for describing an electrode forming process of the memory logic composite semiconductor device of FIG. 16.
이러한 목적은, 메모리 소자, 주변 회로 및 바이폴라 접합 트랜지스터를 포함하는 메모리 로직 복합 반도체 소자의 바이폴라 접합 트랜지스터 제조방법에 있어서, 반도체기판 상에 메모리 소자 및 주변 회로내의 게이트 스페이서 형성을 위한 제1 산화막을 형성하는 단계와, 제1 마스크막 패턴을 사용하여 제1 산화막을 패터닝하여 주변회로의 PMOS 영역의 게이트 스페이서를 형성하는 동시에 바이폴라 접합 트랜지스터의 베이스가 형성될 영역을 노출시키는 단계와, P형 불순물 이온을 주변회로 및 바이폴라 접합 트랜지스터의 노출 부분에 주입하여 주변회로의 PMOS의 소오스/드레인 영역과 바이폴라 접합 트랜지스터의 베이스를 형성하는 단계와, 제2 마스크막 패턴을 사용하여 패터닝된 제1 산화막을 다시 패터닝하여 주변회로의NMOS 영역의 게이트 스페이서를 형성하는 동시에 바이폴라 접합 트랜지스터의 에미터가 형성될 영역을 노출시키는 단계와, N형 불순물 이온을 주변회로 및 바이폴라 접합 트랜지스터의 노출부분에 주입하여 주변회로의 NMOS의 소오스/드레인 영역과 바이폴라 접합 트랜지스터의 에미터를 형성하는 단계와, 전면에 제2 산화막을 형성하는 단계와, 제2 산화막을 패터닝하여 메모리 소자 영역에 워드라인 게이트 스페이서를 형성하는 동시에 바이폴라 접합 트랜지스터의 컬렉터 영역이 형성될 부분을 노출시키는 단계와, N형 불순물 이온을 바이폴라 접합 트랜지스터의 노출부분에 주입하여 바이폴라 접합 트랜지스터의 컬렉터를 형성하는 단계와, 메모리 소자 영역 및 바이폴라 접합 트랜지스터 영역에 각각 플러그 패턴을 형성하는 단계,및 메모리 소자 영역 및 주변회로 영역에 전극들을 형성하는 동시에 바이폴라 접합 트랜지스터의 에미터 전극, 컬렉터 전극 및 베이스 전극을 형성하는 단계를 포함하여 이루어진 메모리 로직 복합 반도체 소자의 바이폴라 접합 트랜지스터 제조방법을 제공함으로써 달성된다.This object is to provide a bipolar junction transistor of a memory logic composite semiconductor device including a memory device, a peripheral circuit, and a bipolar junction transistor, wherein a first oxide film is formed on the semiconductor substrate for formation of a gate spacer in the memory device and the peripheral circuit. Patterning the first oxide film using the first mask film pattern to form a gate spacer of the PMOS region of the peripheral circuit, and exposing a region where the base of the bipolar junction transistor is to be formed; Implanting the exposed portion of the peripheral circuit and the bipolar junction transistor to form a source / drain region of the PMOS of the peripheral circuit and the base of the bipolar junction transistor; patterning the first oxide film patterned again using the second mask layer pattern Gate sparing in the NMOS region of the peripheral circuit Exposing the region where the emitter of the bipolar junction transistor is to be formed, and simultaneously implanting N-type impurity ions into the exposed portion of the peripheral circuit and the bipolar junction transistor, thereby forming a source / drain region and a bipolar junction transistor of the NMOS of the peripheral circuit. Forming an emitter of the; forming a second oxide film over the entire surface; patterning the second oxide film to form a word line gate spacer in the memory device region; and exposing a portion where the collector region of the bipolar junction transistor is to be formed. Forming a collector of the bipolar junction transistor by implanting N-type impurity ions into an exposed portion of the bipolar junction transistor, forming a plug pattern in each of the memory element region and the bipolar junction transistor region, and the memory element region. And in the peripheral circuit area Including the step of simultaneously forming the emitter electrode, the collector electrode and the base electrode of the bipolar junction transistor form is achieved by providing a bipolar junction transistor production method of a compound semiconductor device comprising a logic memory.
이하, 첨부 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
먼저, 도 1에 도시된 바와 같이, 메모리 로직 복합 반도체 소자는 동일한 기판을 사용하여 디램 영역(Ⅰ), 주변회로 영역(Ⅱ) 및 바이폴라 접합 트랜지스터 영역(Ⅲ)이 형성된다. 실제로 각 영역들은 상호 이격되어 형성되는 경우가 더 많지만, 설명의 편의를 위하여 도면에서 각 영역들은 서로 연결되어 형성되는 것으로 도시하였다.First, as shown in FIG. 1, in the memory logic complex semiconductor device, a DRAM region I, a peripheral circuit region II, and a bipolar junction transistor region III are formed using the same substrate. In fact, although each of the regions are more often formed to be spaced apart from each other, for convenience of description, the regions are shown as being connected to each other in the drawings.
상기 디램 영역(Ⅰ), 주변회로 영역(Ⅱ) 및 바이폴라 접합 트랜지스터 영역(Ⅲ)에서, 디램 셀이 형성되는 반도체기판(1), 주변회로가 형성되는 반도체기판(2) 및 바이폴라 접합 트랜지스터가 형성되는 반도체기판(3) 상에 각각 필드산화막(4)에 의해 활성영역들이 한정된다.In the DRAM region I, the peripheral circuit region II, and the bipolar junction transistor region III, a semiconductor substrate 1 on which a DRAM cell is formed, a semiconductor substrate 2 on which a peripheral circuit is formed, and a bipolar junction transistor are formed. The active regions are defined by the field oxide film 4 on the semiconductor substrate 3, respectively.
한편, 디램 셀이 형성되는 반도체기판(1) 위에는 워드 라인 도전막(11)들이 상호 이격되어 형성되며, 주변회로가 형성되는 반도체기판(2) 위에는 PMOS의 게이트 도전막(21)과 NMOS의 게이트 도전막(22)이 상호 이격되어 형성된다.On the other hand, word line conductive layers 11 are formed on the semiconductor substrate 1 on which the DRAM cells are formed, and the word line conductive layers 11 are spaced apart from each other. The gate conductive layer 21 of the PMOS gate and the NMOS gate are formed on the semiconductor substrate 2 on which the peripheral circuits are formed. The conductive films 22 are formed to be spaced apart from each other.
그리고, 상기 결과물 전면에 스페이서 형성을 위한 제1 산화막(5)을 형성한다. 그리고, 제1 산화막(5) 위에는 포토레지스트 패턴(PR)을 형성한다. 이 포토레지스트 패턴(PR)은 주변회로 영역(Ⅱ)의 PMOS의 게이트 스페이서 형성과 소오스/드레인 영역이 형성될 부분을 노출시키기 위한 식각 마스크로 사용되는 동시에, 바이폴라 접합 트랜지스터의 베이스가 형성될 부분을 노출시키기 위한 식각 마스크로 사용된다.Then, the first oxide film 5 for forming a spacer is formed on the entire surface of the resultant. The photoresist pattern PR is formed on the first oxide film 5. The photoresist pattern PR is used as an etching mask for exposing the gate spacer formation of the PMOS of the peripheral circuit region II and the portion where the source / drain region is to be formed, and at the same time, the portion where the base of the bipolar junction transistor is to be formed. Used as an etch mask to expose.
도 2에 도시된 바와같이, 상기 단계 후에 포토레지스트막 패턴(PR)을 식각 마스크로 한 식각공정을 진행한다. 이 때, 상기 식각공정은 이방성 식각을 수행하여 주변회로 영역(Ⅱ)의 PMOS의 게이트 도전막(21) 측벽에 스페이서(5')가 형성되도록 한다. 이와 함께 주변회로 영역(Ⅱ)의 PMOS의 소오스/드레인 영역이 형성될 반도체기판(2)을 노출시키는 것과 동시에, 바이폴라 접합 트랜지스터(Ⅲ)의 베이스가 형성될 반도체기판(3)이 노출되도록 한다.As shown in FIG. 2, an etching process using the photoresist pattern PR as an etching mask is performed after the step. At this time, the etching process is performed by performing anisotropic etching so that the spacer 5 'is formed on the sidewall of the gate conductive film 21 of the PMOS in the peripheral circuit region II. At the same time, the semiconductor substrate 2 on which the source / drain regions of the PMOS of the peripheral circuit region II are to be formed is exposed, and the semiconductor substrate 3 on which the base of the bipolar junction transistor III is to be exposed is exposed.
그리고, 붕소(B) 등과 같은 P형의 불순물 이온을 주입하여 주변회로 영역(Ⅱ)의 PMOS의 소오스/드레인 영역(6,7)을 형성시키는 동시에, 바이폴라 접합 트랜지스터(Ⅲ)의 베이스(8)를 형성시킨다.P-type impurity ions such as boron (B) and the like are implanted to form source / drain regions 6 and 7 of the PMOS in the peripheral circuit region II, and at the same time the base 8 of the bipolar junction transistor III. To form.
도 3에 도시된 바와 같이, 상기 결가물 전면에 포토레지스트 패턴(PR)을 다시 형성한다. 이 포토레지스트 패턴(PR)은 주변회로 영역(Ⅱ)의 NMOS의 게이트 스페이서 형성과 소오스/드레인 영역이 형성될 부분을 노출시키기 위한 식각 마스크로 사용되는 동시에, 바이폴라 접합 트랜지스터의 에미터가 형성될 부분을 노출시키기 위한 식각 마스크로 사용된다.As shown in FIG. 3, the photoresist pattern PR is formed on the entire surface of the binder. The photoresist pattern PR is used as an etch mask for exposing the gate spacer formation of the NMOS and the portion where the source / drain regions are to be formed in the peripheral circuit region II, and the emitter of the bipolar junction transistor is formed. Used as an etch mask to expose the
이어서, 도 4에 도시된 바와 같이, 상기 결과물 전면에 포토레지스트 패턴(PR)을 식각 마스크로 한 식각공정을 진행한다. 이 때, 식각은 이방성 식각을 수행하여 주변회로 영역(Ⅱ)의 NMOS의 게이트 도전막(22) 측벽에 스페이서(5')가 형성되도록 한다. 이와 함께 주변회로 영역(Ⅱ)의 NMOS의 소오스/드레인 영역이 형성될 반도체기판(2)을 노출시키는 것과 동시에, 바이폴라 접합 트랜지스터(Ⅲ)의 에미터가 형성될 반도체기판(3)이 노출되도록 한다. 그리고, 비소(As) 등과 같은 N형 불순물이온을 주입하여 주변회로 영역(Ⅱ)의 NMOS의 소오스/드레인 영역(6',7')을 형성시키는 동시에, 바이폴라 접합 트랜지스터(Ⅲ)의 에미터(8')를 형성시킨다.Subsequently, as shown in FIG. 4, an etching process using the photoresist pattern PR as an etching mask is performed on the entire surface of the resultant. At this time, the etching is performed by performing anisotropic etching so that the spacer 5 'is formed on the sidewall of the gate conductive film 22 of the NMOS in the peripheral circuit region II. At the same time, the semiconductor substrate 2 on which the source / drain regions of the NMOS of the peripheral circuit region II are to be formed is exposed, and the semiconductor substrate 3 on which the emitter of the bipolar junction transistor III is to be formed is exposed. . N-type impurity ions such as arsenic (As) are implanted to form source / drain regions 6 'and 7' of the NMOS in the peripheral circuit region II, and emitters of the bipolar junction transistor III 8 ').
도 5에 도시된 바와같이, 상기 결과물의 전면에 제2 산화막(9)을 형성한다. 이 제2 산화막(9)은 디램 셀에 형성되어 있는 워드라인 게이트 도전막(11)의 측벽에 스페이서를 형성시키기 위한 것으로서, 바이폴라 접합 트랜지스터 영역(Ⅲ)에서는 반도체기판(3) 위에도 형성된다.As shown in FIG. 5, a second oxide film 9 is formed on the entire surface of the resultant product. The second oxide film 9 is formed on the sidewalls of the word line gate conductive film 11 formed in the DRAM cell. The second oxide film 9 is also formed on the semiconductor substrate 3 in the bipolar junction transistor region III.
그리고, 도 6에 도시된 바와 같이, 상기 결과물 전면에 포토레지스트패턴(PR)을 다시 형성한다. 이 포토레지스트 패턴(PR)은 디램영역(Ⅰ)을 노출시키는 동시에 바이폴라 접합 트랜지스터의 컬렉터가 형성될 부분을 노출시키기 위한 식각 마스크로 사용된다.As shown in FIG. 6, the photoresist pattern PR is formed on the entire surface of the resultant product. The photoresist pattern PR is used as an etch mask for exposing the DRAM region I and at the same time exposing a portion where the collector of the bipolar junction transistor is to be formed.
이어서, 도 7에 도시된 바와 같이, 상기 포토레지스트 패턴(PR)을 식각 마스크로 한 식각 공정을 진행한다. 이 때, 식각은 이방성 식각을 수행하여 디램 영역(Ⅰ)의 워드라인 도전막(11) 측벽에 스페이서(51)가 형성되도록 한다. 이와 함께, 바이폴라 접합 트랜지스터(Ⅲ)의 컬렉터가 형성될 반도체기판(3)이 노출되도록 한다. 그리고, 비소(As) 등과 같은 N형 불순물이온을 주입하여 바이폴라 접합 트랜지스터(Ⅲ)의 컬렉터(8')를 형성시킨다.Subsequently, as shown in FIG. 7, an etching process using the photoresist pattern PR as an etching mask is performed. At this time, the etching is performed by performing anisotropic etching so that the spacer 51 is formed on the sidewall of the word line conductive layer 11 of the DRAM region I. In addition, the semiconductor substrate 3 on which the collector of the bipolar junction transistor III is to be formed is exposed. Then, an N-type impurity ion such as arsenic (As) or the like is implanted to form the collector 8 'of the bipolar junction transistor III.
도 8에 도시된 바와 같이, 상기 결과물의 전면에 플러그용 폴리실리콘막(30)을 형성한다. 이 플러그용 폴리실리콘막(30)은 N형의 불순물 이온들로 도핑된 폴리실리콘막을 증착함으로써 형성시킬 수 있다.As shown in FIG. 8, a polysilicon film 30 for plug is formed on the entire surface of the resultant product. This plug polysilicon film 30 can be formed by depositing a polysilicon film doped with N-type impurity ions.
도 9에 도시된 바와 같이, 상기 플러그(30)용 폴리실리콘막 상에, 예를 들어 포토레지스트를 이용하여 상기 플러그용 폴리실리콘막(도 8의 30)의 소정 부분을 노출시키는 마스크 패턴(도시되지 않음)을 형성한다. 다음에, 이 마스크 패턴(미도시)을 식각 마스크로 하여 상기 플러그용 폴리실리콘막(도 8의 30)의 노출 부분을 제거한다. 그러면, 도시된 바와 같은 플러그 패턴(31, 33)이 형성된다. 이 플러그 패턴(31,33)은 디램 영역(Ⅰ) 및 바이폴라 접합 트랜지스터 영역(Ⅲ)에 각각 형성된다.As shown in FIG. 9, a mask pattern exposing a predetermined portion of the plug polysilicon film 30 in FIG. 8 by using a photoresist, for example, on the polysilicon film for the plug 30. Not formed). Next, using this mask pattern (not shown) as an etching mask, the exposed portion of the plug polysilicon film (30 in FIG. 8) is removed. Then, plug patterns 31 and 33 as shown are formed. The plug patterns 31 and 33 are formed in the DRAM region I and the bipolar junction transistor region III, respectively.
도 10은 메모리 로직 복합 반도체 소자의 전극 형성공정을 설명하기 위한 단면도로서, 상기 디램 영역(Ⅰ)의 플러그 패턴(31) 위에 스토리지 노드(41)와 비트 라인(42)을 형성한 후에 층간절연막(50)을 형성한다. 이어서, 소정의 마스크 패턴(미도시)을 이용하여 층간절연막(50)의 일부를 제거한 후에 금속막 형성공정을 진행하여 디램 영역(Ⅰ)내의 금속막(61), 주변회로 영역(Ⅱ)내의 소오스/드레인 전극 (62) 및 바이폴라 접합 트랜지스터 영역(Ⅲ)내의 에미터 전극(631), 베이스 전극 (632) 및 컬렉터 전극(633)이 형성되도록 하면, 본 발명에 따른 메모리 로직 복합 반도체 소자의 바이폴라 접합 트랜지스터가 완성된다.FIG. 10 is a cross-sectional view illustrating an electrode forming process of a memory logic composite semiconductor device, and after forming a storage node 41 and a bit line 42 on a plug pattern 31 of the DRAM region I, an interlayer insulating film ( 50). Subsequently, a portion of the interlayer insulating film 50 is removed using a predetermined mask pattern (not shown), and then a metal film forming process is performed to obtain a source in the metal film 61 in the DRAM region I and the peripheral circuit region II. When the emitter electrode 631, the base electrode 632, and the collector electrode 633 are formed in the drain / drain electrode 62 and the bipolar junction transistor region III, the bipolar junction of the memory logic composite semiconductor device according to the present invention is formed. The transistor is complete.
그리고, 계속하여 본 발명의 다른 실시예에 따른 메모리 로직 복합 반도체 소자의 바이폴라 접합 트랜지스터 제조방법을 도 11 내지 도 16을 참조하여 설명하기로 한다. 도 1 내지 도 5와 동일한 공정은 본 실시예에서도 동일하게 적용하므로, 설명은 생략하기로 한다.Subsequently, a method of manufacturing a bipolar junction transistor of a memory logic composite semiconductor device according to another exemplary embodiment of the present invention will be described with reference to FIGS. 11 to 16. 1 to 5 are the same as in the present embodiment, so description thereof will be omitted.
도 11에 도시된 바와 같이, 도 5에 도시된 상기 결과물의 전면에 포토레지스트 패턴(PR)을 형성한다. 이 포토레지스트 패턴(PR)은 디램영역(Ⅰ)을 완전히 노출시키는 동시에, 주변회로 영역(Ⅱ) 및 바이폴라 접합 트랜지스터 영역(Ⅲ)은 완전히 덮는다.As shown in FIG. 11, the photoresist pattern PR is formed on the entire surface of the resultant illustrated in FIG. 5. The photoresist pattern PR completely exposes the DRAM region I, and completely covers the peripheral circuit region II and the bipolar junction transistor region III.
그리고, 도 12에 도시된 바와 같이, 상기 포토레지스트 패턴(PR)을 식각 마스크로 하여 이방성 식각을 실시하여 디램영역(Ⅰ) 내의 워드 라인 도전막(11) 측벽에 스페이서(51)를 형성된다. 이어서, 상기 포토레지스트 패턴(도 11의 PR)을 제거한다.As shown in FIG. 12, anisotropic etching is performed using the photoresist pattern PR as an etching mask to form spacers 51 on sidewalls of the word line conductive layer 11 in the DRAM region I. Referring to FIG. Next, the photoresist pattern (PR of FIG. 11) is removed.
그리고, 도 13에 도시된 바와 같이, 상기 결과물 전면에 플러그용 폴리실리콘막(30)을 형성한다. 이 플러그 폴리실리콘막(30)은 N형의 불순물 이온들로 도핑된 폴리실리콘막을 증착함으로써 형성시킬 수 있다.And, as shown in Figure 13, the polysilicon film 30 for the plug is formed on the entire surface of the resultant. This plug polysilicon film 30 can be formed by depositing a polysilicon film doped with N-type impurity ions.
도 14에 도시된 바와 같이, 전면에 예를 들어 포토레지스트를 이용하여 상기 플러그용 폴리실리콘막(도 13의 30)의 소정 부분을 노출시키는 마스크 패턴(도시되지 않음)을 형성한다. 그런 후에, 이 마스크 패턴을 식각 마스크로 하여 상기 플러그용 폴리실리콘막(도 13의 30)의 노출부분을 제거한다. 그러면, 도시된 바와 같은 플러그 패턴(31, 33)이 형성된다. 이 플러그 패턴(31, 33)은, 앞서 설명한 본 발명의 일 실시예와는 다르게, 디램영역(Ⅰ)에만 형성된다.As shown in Fig. 14, a mask pattern (not shown) is formed over the entire surface by using a photoresist, for example, to expose a predetermined portion of the plug polysilicon film (30 in Fig. 13). Thereafter, the exposed portion of the plug polysilicon film (30 in FIG. 13) is removed using this mask pattern as an etching mask. Then, plug patterns 31 and 33 as shown are formed. The plug patterns 31 and 33 are formed only in the DRAM region I, unlike the embodiment of the present invention described above.
도 15에 도시된 바와 같이, 상기 결과물의 전면에 제1 층간절연막(50')을 형성한다. 그리고, 이 층간절연막(50')을 패터닝하여 디램영역(Ⅰ)에서 비트라인이 형성될 부분을 노출시키는 동시에, 바이폴라 접합 트랜지스터 영역(Ⅲ)에서 컬렉터(8')를 노출시킨다. 이어서, 디램 영역(Ⅰ)에 비트라인(42)을 형성하는 동시에 바이폴라 접합 트랜지스터 영역(Ⅲ)의 컬렉터 컨택(700)을 형성한다.As shown in FIG. 15, a first interlayer insulating film 50 ′ is formed on the entire surface of the resultant product. The interlayer insulating film 50 'is patterned to expose the portion where the bit line is to be formed in the DRAM region I, and to expose the collector 8' in the bipolar junction transistor region III. Next, the bit line 42 is formed in the DRAM region I, and the collector contact 700 of the bipolar junction transistor region III is formed.
도 16에 도시된 바와 같이, 제1 층간절연막(50') 상에 제2 층간절연막(미도시)을 형성하여, 제1 및 제2 층간절연막을 포함하는 층간절연막(50)을 형성한다. 이어서, 소정의 마스크 패턴(미도시)을 이용하여 층간절연막(50)의 일부를 제거한 후에 금속막 형성공정을 진행하여 디램영역(Ⅰ)내의 금속막(61), 주변회로 영역(Ⅱ) 내의 소오스/드레인 전극(62) 및 바이폴라 접합 트랜지스터 영역(Ⅲ)내의 에미터 전극(631), 베이스 전극(632) 및 컬렉터 전극(633)이 형성되도록 하면, 본 발명에 따른 메모리 로직 복합 반도체 소자의 바이폴라 접합 트랜지스터가 완성된다.As shown in FIG. 16, a second interlayer insulating film (not shown) is formed on the first interlayer insulating film 50 ′ to form an interlayer insulating film 50 including the first and second interlayer insulating films. Subsequently, a portion of the interlayer insulating film 50 is removed by using a predetermined mask pattern (not shown), and then a metal film forming process is performed to obtain a source in the metal film 61 in the DRAM region I and the peripheral circuit region II. When the emitter electrode 631, the base electrode 632, and the collector electrode 633 in the drain electrode 62 and the bipolar junction transistor region III are formed, the bipolar junction of the memory logic composite semiconductor device according to the present invention is formed. The transistor is complete.
따라서, 상기한 바와 같이, 본 발명에 따른 메모리 로직 복합 반도체 소자의 바이폴라 접합 트랜지스터 제조방법을 이용하게 되면, 주변회로 영역에서의 PMOS 및 NMOS에서의 소오스/드레인 영역 형성을 위한 이온주입 공정을 이용하여 바이폴라 접합 트랜지스터의 베이스 및 에미터를 형성하므로, 주입된 이온들의 확산거리가 종래의 경우보다 작아지며, 바이폴라 접합 트랜지스터의 컬렉터에 도핑된 플러그 패턴을 사용함으로써 크기가 작은 바이폴라 접합 트랜지스터를 형성시킬 수 있는 매우 유용하고 효과적인 발명이다.Therefore, as described above, when the bipolar junction transistor manufacturing method of the memory logic composite semiconductor device according to the present invention is used, an ion implantation process for forming a source / drain region in a PMOS and an NMOS in a peripheral circuit region is used. Since the base and emitter of the bipolar junction transistor are formed, the diffusion distance of the implanted ions becomes smaller than in the conventional case, and by using the plug pattern doped in the collector of the bipolar junction transistor, a small bipolar junction transistor can be formed. It is a very useful and effective invention.
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| US8133783B2 (en) * | 2007-10-26 | 2012-03-13 | Hvvi Semiconductors, Inc. | Semiconductor device having different structures formed simultaneously |
| US8125044B2 (en) | 2007-10-26 | 2012-02-28 | Hvvi Semiconductors, Inc. | Semiconductor structure having a unidirectional and a bidirectional device and method of manufacture |
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| US5321650A (en) * | 1991-06-10 | 1994-06-14 | Hitachi, Ltd. | BiCMOS semiconductor memory device using load transistors formed on an insulating film |
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| KR870009474A (en) * | 1986-03-24 | 1987-10-27 | 미쓰다 가쓰시게 | Semiconductor integrated circuit device |
| US5321650A (en) * | 1991-06-10 | 1994-06-14 | Hitachi, Ltd. | BiCMOS semiconductor memory device using load transistors formed on an insulating film |
| US5547893A (en) * | 1995-12-27 | 1996-08-20 | Vanguard International Semiconductor Corp. | method for fabricating an embedded vertical bipolar transistor and a memory cell |
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