KR20030050791A - Method for Fabricating of Semiconductor Device - Google Patents
Method for Fabricating of Semiconductor Device Download PDFInfo
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- KR20030050791A KR20030050791A KR1020010081313A KR20010081313A KR20030050791A KR 20030050791 A KR20030050791 A KR 20030050791A KR 1020010081313 A KR1020010081313 A KR 1020010081313A KR 20010081313 A KR20010081313 A KR 20010081313A KR 20030050791 A KR20030050791 A KR 20030050791A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000000034 method Methods 0.000 title claims abstract description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 15
- 229920005591 polysilicon Polymers 0.000 claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 11
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 12
- 150000002500 ions Chemical class 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 238000005530 etching Methods 0.000 abstract description 8
- 238000000059 patterning Methods 0.000 abstract description 6
- 125000006850 spacer group Chemical group 0.000 abstract description 6
- 239000002019 doping agent Substances 0.000 abstract 1
- 150000004767 nitrides Chemical class 0.000 description 15
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000002955 isolation Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- -1 Phosphorus ions Chemical class 0.000 description 1
- 238000005054 agglomeration Methods 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
본 발명은 반도체 소자에 관한 것으로 특히, 엔모스 게이트와 피모스 게이트간의 임계치수(CD : Critical Dimension) 차이 및 액티브 영역의 오버-에치(Over-etch)를 방지하기 위한 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device for preventing over-etching of active regions and critical dimension (CD) differences between an NMOS gate and a PMOS gate. will be.
고집적 씨모스(CMOS : Complementary Metal Oxide Semiconductor) 반도체 소자 제조시 게이트의 도핑 효율을 높이기 위해 게이트 패터닝전에 게이트 폴리(Gate poly)에 도핑을 실시하고 있다.Complementary Metal Oxide Semiconductor (CMOS) In the manufacture of semiconductor devices, gate poly is doped before gate patterning to increase the gate doping efficiency.
통상적으로, 게이트 패터닝전에 엔모스 게이트 폴리(Gate-poly)에만 인(Phosphorus) 이온을 프리-도핑(Pre-doping)한다.Typically, Phosphorus ions are pre-doped only in the NMOS gate poly-poly before gate patterning.
이러한 엔모스(NMOS) 게이트 폴리의 프리-도핑(Pre-doping) 공정으로 인하여 엔모스 게이트 폴리의 식각율이 피모스 게이트 폴리의 식각율보다 커지게 되며, 이러한 식각율 차이는 게이트 패터닝 공정 이후에 엔모스(NMOS) 게이트와 피모스(PMOS) 게이트간의 임계치수(CD : Critical Dimension)가 달라지게 되는 원인이 된다.Due to the pre-doping process of the NMOS gate poly, the etch rate of the NMOS gate poly becomes larger than that of the PMOS gate poly, and the difference in the etch rate after the gate patterning process The critical dimension (CD) between the NMOS gate and the PMOS gate is changed.
또한, 엔모스 게이트 폴리의 식각율(Etch Rate) 증가로 인하여 엔모스 액티브(Active) 영역에 오버 에치(Over-etch)가 발생되기도 한다.In addition, over-etch occurs in the NMOS active region due to an increase in the etching rate of the NMOS gate poly.
따라서, 상기와 같은 종래의 반도체 소자의 제조방법은 다음과 같은 문제점이 있다.Therefore, the conventional method of manufacturing a semiconductor device as described above has the following problems.
첫째, 엔모스 게이트와 피모스 게이트의 임계치수가 서로 상이하므로 NP 바이어스 문제가 발생된다.First, since the critical dimensions of the NMOS gate and the PMOS gate are different from each other, an NP bias problem occurs.
둘째, 엔모스 게이트 폴리의 식각율 증가로 인하여 게이트 패터닝시 엔모스의 액티브 영역이 손상되게 된다.Second, due to the increased etch rate of the NMOS gate poly, the active area of the NMOS is damaged during gate patterning.
본 발명은 상기와 같은 문제점을 해결하기 위하여 안출한 것으로 NP 바이어스 문제 및 액티브 영역의 오버-에치 문제를 방지하기에 적합한 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, and an object thereof is to provide a method of manufacturing a semiconductor device suitable for preventing the NP bias problem and the over-etching problem of the active region.
도 1a 내지 도 1h는 본 발명의 실시예에 따른 반도체 소자의 제조 공정 단면도1A to 1H are cross-sectional views illustrating a process of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
도면의 주요 부분에 대한 부호 설명Explanation of symbols for the main parts of drawings
11 : 반도체 기판 12 : 소자분리 영역11 semiconductor substrate 12 device isolation region
13 : 게이트 전극 14 : LDD 영역13 gate electrode 14 LDD region
15 : TEOS막 16 : 질화막15 TEOS film 16 nitride film
17 : 포토레지스트 18 : 폴리 실리콘막17 photoresist 18 polysilicon film
19 : 스페이서 20/21 : 소오스/드레인 영역19 spacer 20/21 source / drain region
22 : 살리사이드막22: salicide film
상기와 같은 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 제조방법은 엔모스 영역과 피모스 영역이 정의된 반도체 기판상에 게이트를 형성하고 전면에 상기 게이트보다 두꺼운 두께의 절연막을 형성하는 단계와, 상기 게이트의 상면이 노출되도록 상기 절연막을 평탄 제거하는 단계와, 상기 엔모스 영역 또는 피모스 영역 중 어느 한 영역에 형성된 게이트에만 게이트 이온을 주입하는 단계와, 상기 노출된 게이트 및 이에 인접한 절연막상에 폴리 실리콘막을 형성하는 단계와, 상기 폴리 실리콘막을 마스크로 상기 절연막을 제거하여 상기 게이트 양측면에 절연막 측벽을 형성하는 단계를 포함하여 형성함을 특징으로 한다.The method of manufacturing a semiconductor device according to the present invention for achieving the above object comprises the steps of forming a gate on a semiconductor substrate in which the NMOS region and the PMOS region are defined, and forming an insulating film thicker than the gate on the front surface; Removing the insulating layer so that the top surface of the gate is exposed, implanting gate ions only into a gate formed in one of the NMOS region and the PMOS region, and forming the exposed gate and the insulating layer adjacent thereto. And forming an insulating film sidewall on both sides of the gate by removing the insulating film using the polysilicon film as a mask.
이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체 소자의 제조방법을 설명하면 다음과 같다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described with reference to the accompanying drawings.
도 1a 내지 도 1h는 본 발명의 실시예에 따른 반도체 소자의 제조공정 단면도이다.1A to 1H are cross-sectional views illustrating a process of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
본 발명에 따른 반도체 소자의 제조방법은 우선, 도 1a에 도시된 바와 같이, 소자분리 영역(12)이 형성된 반도체 기판(11)상에 게이트 절연막(도면에는 도시하지 않았음)을 개재하여 복수개의 게이트 전극(13)을 형성한다.In the method of manufacturing a semiconductor device according to the present invention, first, as shown in FIG. 1A, a plurality of semiconductor devices are formed on a semiconductor substrate 11 on which the device isolation region 12 is formed through a gate insulating film (not shown). The gate electrode 13 is formed.
상기 게이트 전극(13)은 통상의 게이트 전극 재료인 폴리 실리콘(Poly-Si)을 이용하여 형성한다.The gate electrode 13 is formed using poly-silicon (Poly-Si) which is a common gate electrode material.
이어, 상기 게이트 전극(13)을 마스크로 상기 반도체 기판(11)의 전면에 저농도의 불순물 이온을 주입하여 상기 게이트 전극(13) 양측의 반도체 기판(11)내에 LDD 영역(14)을 형성한다.Subsequently, a low concentration of impurity ions are implanted into the entire surface of the semiconductor substrate 11 using the gate electrode 13 as a mask to form the LDD region 14 in the semiconductor substrate 11 on both sides of the gate electrode 13.
이어, 도 1b에 도시된 바와 같이 상기 게이트 전극(13)을 포함한 반도체 기판(11)의 표면상에 TEOS막(15)을 증착하고 상기 게이트 전극(13)의 두께보다 500∼2000Å 두꺼운 두께로 질화막(16)을 증착한다.Subsequently, as illustrated in FIG. 1B, a TEOS film 15 is deposited on the surface of the semiconductor substrate 11 including the gate electrode 13, and the nitride film is 500 to 2000 Å thicker than the thickness of the gate electrode 13. (16) is deposited.
여기서, 상기 TEOS막(15)은 후속으로 증착되는 상기 질화막(16)의 스트레스(Stress)를 해소시켜주는 버퍼층으로, 100∼400Å의 두께로 증착한다.Here, the TEOS film 15 is a buffer layer that relieves stress of the nitride film 16 that is subsequently deposited, and is deposited to have a thickness of 100 to 400 kPa.
또한, 상기 TEOS막(15) 대신에 통상적인 CVD(Chemical Mechanical Polishing), PVD(Physical Vapor Deposition)로 제조되는 옥사이드(Oxide)계 물질을 사용하여도 무방하며, TEOS막(15)의 증착 공정 없이 질화막(16)을 증착하여도 무방하다.In addition, instead of the TEOS film 15, an oxide-based material made of conventional chemical mechanical polishing (CVD) or physical vapor deposition (PVD) may be used, and without depositing the TEOS film 15. The nitride film 16 may be deposited.
이어, 도 1c에 도시된 바와 같이 상기 게이트 전극(13)이 노출되도록 상기 질화막(16)과 TEOS막(15)을 선택적으로 제거한다.Next, as illustrated in FIG. 1C, the nitride layer 16 and the TEOS layer 15 are selectively removed to expose the gate electrode 13.
상기 질화막(16)과 TEOS막(15)의 제거 방법으로는 상기 게이트 전극(13) 상부가 노출되도록 CMP(Chemical Mechanical Polishing) 공정을 실시하는 방법 또는 상기 게이트 전극(13) 상부에 상기 질화막(16)과 TEOS막(15)이 200∼500Å의 두께로 잔류하도록 CMP 공정을 실시한 후에, 습식 식각 공정으로 상기 게이트 전극(13)이 노출되도록 상기 질화막(16)과 TEOS막(15)을 제거하는 방법 중 어느 하나를 이용하여 실시한다.As a method of removing the nitride layer 16 and the TEOS layer 15, a chemical mechanical polishing (CMP) process is performed to expose the upper portion of the gate electrode 13, or the nitride layer 16 is disposed on the gate electrode 13. ) And the TEOS film 15 are removed to a thickness of 200 to 500 kPa, and then the nitride film 16 and the TEOS film 15 are removed to expose the gate electrode 13 by a wet etching process. It is carried out using either.
이어, 도 1d에 도시된 바와 같이 상기 게이트 전극(13) 및 질화막(16)상에포토레지스트(17)를 도포하고, 노광 및 현상 공정으로 상기 게이트 전극(13) 및 그에 인접한 질화막(16)이 노출되도록 상기 포토레지스트(17)를 선택적으로 패터닝한다.Subsequently, as shown in FIG. 1D, the photoresist 17 is coated on the gate electrode 13 and the nitride film 16, and the gate electrode 13 and the nitride film 16 adjacent thereto are exposed by an exposure and development process. The photoresist 17 is selectively patterned to be exposed.
이때, 상기 포토레지스트(17)는 상기 엔모스 게이트 전극을 포함하는 영역만이 노출되도록 패터닝하거나, 피모스 게이트 전극을 포함하는 영역만이 노출되도록 패터닝한다.In this case, the photoresist 17 is patterned to expose only the region including the NMOS gate electrode, or is patterned to expose only the region including the PMOS gate electrode.
그리고, 상기 패터닝된 포토레지스트(17)를 마스크로 상기 노출된 엔모스 또는 피모스 게이트 전극(13)에 엔모스 또는 피모스 게이트용 이온을 주입한다.Then, the patterned photoresist 17 is implanted with the NMOS or PMOS gate ions into the exposed NMOS or PMOS gate electrode 13.
이때, 상기 LDD 영역(14)은 상기 질화막(16)에 의해 마스킹(Masking)되므로 게이트 전극(13)에만 선택적으로 이온이 주입되게 된다.In this case, since the LDD region 14 is masked by the nitride layer 16, ions are selectively implanted into the gate electrode 13.
이어, 상기 포토레지스트(17)를 제거하고 도 1e에 도시된 바와 같이 500∼1000℃의 DCS, SiH4, Si2H2Cl, Si2H6의 혼합가스 분위기에서 선택적 에피택셜 성장(SEG : Selective Epixital Growth) 공정을 실시하여 상기 노출된 게이트 전극(13) 상부에 폴리 실리콘막(18)을 성장시킨다.Subsequently, the photoresist 17 is removed and selective epitaxial growth (SEG) is performed in a mixed gas atmosphere of DCS, SiH 4 , Si 2 H 2 Cl, and Si 2 H 6 at 500 to 1000 ° C. as shown in FIG. 1E. A selective silicon growth process is performed to grow the polysilicon layer 18 on the exposed gate electrode 13.
이때, 선택적 에피택셜 성장 공정의 공정 조건을 수평 방향(Lateral)의 성장 속도가 수직 방향의 성장 속도보다 빠르도록 설정하여, 상기 폴리 실리콘막(18)을 노출된 게이트 전극(13) 상부뿐만 아니라, 게이트 전극(13) 양측의 질화막(16) 상부에도 형성한다.In this case, the process conditions of the selective epitaxial growth process are set such that the growth rate in the horizontal direction is faster than the growth rate in the vertical direction, so that the polysilicon film 18 is not only exposed to the upper portion of the gate electrode 13. It is also formed on the nitride film 16 on both sides of the gate electrode 13.
여기서, 상기 질화막(16) 상부에 형성되는 폴리 실리콘막(18)은 차후에 상기게이트 전극(13) 측면의 형성되는 스페이서(Spacer)의 두께에 대응된다.Here, the polysilicon film 18 formed on the nitride film 16 corresponds to a thickness of a spacer formed laterally on the gate electrode 13 side.
이어, 도 1f에 도시된 바와 같이 상기 폴리 실리콘막(18)을 마스크로 상기 질화막(16)과 TEOS막(15)을 선택적으로 식각하여 상기 게이트 전극(13) 양측의 상기 폴리 실리콘막(18) 하부에 잔류하는 상기 질화막(16)과 TEOS막(15)으로 스페이서(19)를 형성한다.Subsequently, as illustrated in FIG. 1F, the nitride film 16 and the TEOS film 15 are selectively etched using the polysilicon film 18 as a mask to form the polysilicon film 18 on both sides of the gate electrode 13. The spacer 19 is formed of the nitride film 16 and the TEOS film 15 remaining below.
여기서, 상기 식각 공정의 식각 가스로는 HCl, Cl의 혼합가스를 이용하며, 식각 공정시 압력은 100∼600Torr이 되도록 한다.Here, a mixed gas of HCl and Cl is used as an etching gas of the etching process, and the pressure is 100 to 600 Torr during the etching process.
이어, 도 1g에 도시된 바와 같이 상기 폴리 실리콘막(18), 스페이서(19) 및 소자분리 영역(12)을 마스크로 상기 반도체 기판(11)에 고농도 불순물 이온을 주입하여 상기 스페이서(19) 양측 반도체 기판(11)에 소오스/드레인 영역(20/21)을 형성한다.Subsequently, as shown in FIG. 1G, a high concentration of impurity ions are implanted into the semiconductor substrate 11 using the polysilicon layer 18, the spacer 19, and the device isolation region 12 as a mask to both sides of the spacer 19. The source / drain regions 20/21 are formed in the semiconductor substrate 11.
이어, 도 1h에 도시된 바와 같이 살리사이드(Salicide) 공정으로 상기 폴리 실리콘막(18)의 상부 표면 및 측면 그리고, 상기 소오스/드레인 영역(20/21)의 표면에 살리사이드막(22)을 형성하여 본 발명에 따른 반도체 소자를 완성한다.Subsequently, as shown in FIG. 1H, the salicide layer 22 is formed on the upper and side surfaces of the polysilicon layer 18 and the surface of the source / drain regions 20/21 by a salicide process. To complete the semiconductor device according to the present invention.
상기와 같은 본 발명의 반도체 소자의 제조방법은 다음과 같은 효과가 있다.The method of manufacturing a semiconductor device of the present invention as described above has the following effects.
첫째, 게이트 패터닝전에 실시하였던 엔모스 게이트 폴리에 대한 프리 도핑 공정을 실시하지 않아 엔모스 게이트 폴리 식각율 증가를 방지할 수 있으므로 게이트 폴리간 식각율 차이로 인한 NP 바이어스 문제를 해결할 수 있다.First, since the pre-doping process for the NMOS gate poly, which was performed before the gate patterning, is not performed, the NMOS gate poly etch rate can be prevented from increasing, thereby solving the NP bias problem due to the difference in the etch rate between the gate polys.
둘째, 엔모스 게이트 폴리의 식각율 증가를 방지할 수 있으므로 엔모스 게이트 폴리의 오버-에치로 인한 액티브 영역의 데미지를 방지할 수 있다.Second, since the etch rate of the NMOS gate poly can be prevented from being increased, damage to the active region due to over-etching of the NMOS gate poly can be prevented.
셋째, NP 바이어스 문제 및 액티브 영역의 데미지 발생 문제를 방지할 수 있으므로 소자의 성능 및 신뢰성을 향상시킬 수 있다.Third, NP bias and active area damage can be prevented, thereby improving device performance and reliability.
넷째, 게이트 전극의 상부를 T자형으로 넓혀줌으로써 Salicide 형성시 저항을 감소시키며 후속 열공정에 의한 뭉침(agglomeration)현상을 억제할 수 있다.Fourth, by widening the upper portion of the gate electrode in a T-shape, it is possible to reduce resistance in forming a salicide and to suppress agglomeration due to subsequent thermal processes.
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