KR20020049350A - Method of manufacturing a semiconductor device - Google Patents
Method of manufacturing a semiconductor device Download PDFInfo
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- KR20020049350A KR20020049350A KR1020000078504A KR20000078504A KR20020049350A KR 20020049350 A KR20020049350 A KR 20020049350A KR 1020000078504 A KR1020000078504 A KR 1020000078504A KR 20000078504 A KR20000078504 A KR 20000078504A KR 20020049350 A KR20020049350 A KR 20020049350A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로서, 특히 다마신 제조공정에 SEG 공정을 도입하여 NMOS 영역에는 n+ 다결정실리콘과 금속층의 적층구조의 게이트전극이 형성되고 PMOS 영역에는 PMOS용 금속층의 단일 게이트전극이 형성되는 듀얼 게이트전극을 형성함으로써, 게이트전극에서 발생하는 게이트 공핍화 및 보론침투 현상으로 인한 소자의 특성저하를 방지할 수 있는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, a SEG process is introduced into a damascene manufacturing process, whereby a gate electrode having a lamination structure of n + polysilicon and a metal layer is formed in an NMOS region, and a single gate electrode of a metal layer for PMOS in a PMOS region. The present invention relates to a method of manufacturing a semiconductor device capable of preventing the deterioration of device characteristics due to gate depletion and boron penetration caused by the formation of the dual gate electrode.
본 발명은 고집적 CMOSFET 소자의 듀얼 게이트를 다마신 공정을 적용하여 제조하는 공정기술에 관한 것으로, 특히 통상적인 다마신 제조공정에서 SEG(Selective Epitaxial Growth) 공정을 통하여 PMOS 영역의 실리콘 기판상에 에피실리콘층(Epi-Silicon Layer)을 형성함으로써 NMOS 영역에 대하여 그 두께만큼의 단차를 부여하는 것을 그 주요특징으로 한다. 그 결과 NMOS 영역에는 n+폴리실리콘/금속 게이트, PMOS 영역에는 PMOS용 금속 게이트로 이루어지는 듀얼 게이트를 제조함으로써 고집적, 고성능의 반도체 소자를 구현하는 기술적 기반을 제공한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a process technology for manufacturing a dual gate of a highly integrated CMOSFET device by applying a damascene process, and in particular, episilicon on a silicon substrate in a PMOS region through a selective epitaxial growth (SEG) process in a conventional damascene manufacturing process. It is a main feature to form a layer (Epi-Silicon Layer) to impart a step by the thickness to the NMOS region. As a result, a dual gate consisting of n + polysilicon / metal gates in the NMOS region and a metal gate for PMOS in the PMOS region is provided to provide a technical basis for implementing highly integrated and high performance semiconductor devices.
통상, MOSFET 소자의 게이트전극으로는 다결정실리콘 물질이 널리 사용된다.이는 다결정실리콘이 고융점, 박막형성의 용이성, 선 패턴(Line Pattern)의 용이성, 산화분위기에 대한 안정성, 평탄화 표면안정성등의 우수한 특성을 지니고 있기 때문이다.In general, polysilicon materials are widely used as gate electrodes of MOSFET devices. The polysilicon has excellent melting point, ease of thin film formation, ease of line pattern, stability to oxidation atmosphere, and planarization surface stability. Because it has characteristics.
이러한, 다결정실리콘의 게이트전극을 CMOSFET 소자에 적용함에 있어서, 초기에는 NMOS 및 PMOS 영역에서 모두 n+ 다결정실리콘을 사용하는 것이 일반적인 추세였다. 그러나, PMOS 영역에서는 카운트 도핑(Count Doping)에 의한 매몰채널(Buried Channel)이 형성되어 단채널 효과(Short Channel Effect) 및 누설전류(Leakage Current)가 증대되는 치명적인 문제점이 발생하게 된다.In applying the gate electrode of polysilicon to a CMOSFET device, it was generally a general trend to use n + polysilicon in both the NMOS and PMOS regions. However, in the PMOS region, a buried channel is formed by count doping, which causes a fatal problem of short channel effect and leakage current.
이에 따라, 근래에는 NMOS 영역에는 n+ 다결정실리콘을 사용하고, PMOS 영역에는 P+ 다결정실리콘을 사용하는 듀얼-다결정실리콘(Dual Polysilcon) 게이트전극 제조 방법이 널리 사용되고 있다.Accordingly, a method of manufacturing a dual polysilicon gate electrode using n + polycrystalline silicon in an NMOS region and P + polycrystalline silicon in a PMOS region is widely used.
듀얼-다결정실리콘 게이트전극 제조 방법은 NMOS 및 PMOS 영역에서 표면채널(Surface Channel)을 형성시킴으로써 전술한 PMOS 영역에서의 매몰채널로 인한 문제점을 해결하게 된다. 그러나 이 경우에도 PMOS 영역의 p+ 다결정실리콘 게이트전극에서 게이트 공핍효과(Gate Depletion Effect) 및 보론 침투현상(Boron Penetration)이 발생하기 때문에 소자특성이 현저히 저하되는 문제점이 여전히 존재하게 된다.The dual-polysilicon gate electrode manufacturing method solves the problem caused by the buried channel in the PMOS region by forming a surface channel in the NMOS and PMOS regions. However, even in this case, since the gate depletion effect and boron penetration occur in the p + polysilicon gate electrode in the PMOS region, there is still a problem in that device characteristics are significantly reduced.
그래서 이러한 문제점을 해결하기 위한 다양한 연구가 활발히 진행되고 있다. 특히, p+ 다결정실리콘내에 질소이온을 주입하는 방법과, 게이트절연막으로 질산화막을 사용하는 방법과, In-situ 보론 도핑하는 방법과, 게이트전극으로 SiGe를사용하는 방법등이 활발히 진행되고 있다.Therefore, various researches are actively being conducted to solve these problems. Particularly, a method of injecting nitrogen ions into p + polysilicon, a method of using a nitric oxide film as a gate insulating film, an in-situ boron doping method, and a method of using SiGe as a gate electrode have been actively progressed.
또한, 최근 CMOSFET 소자의 고집적화에 따라 이에 대응하는 게이트전극의 요구선폭 및 그 저항값이 급격히 감소하고 있기 때문에 실제 소자에는 다결정실리콘과 금속층의 적층구조의 게이트전극을 적용하고 있다. 이러한 적층구조 게이트전극의 하부 듀얼-다결정실리콘은 NMOS 및 PMOS 영역에서 표면채널을 형성하는 역할을 하고, 상부의 금속층은 미세선폭상의 저저항 게이트를 구현하게 된다.In addition, since the required line width and the resistance value of the corresponding gate electrode are rapidly decreasing with the recent high integration of the CMOSFET device, a gate electrode having a lamination structure of polycrystalline silicon and a metal layer is applied to the actual device. The lower dual-polysilicon of the stacked gate electrode forms a surface channel in the NMOS and PMOS regions, and the upper metal layer implements a low resistance gate having a fine line width.
이를 도 1(a) 내지 도 1(f)를 결부하여 상세히 설명하면 다음과 같다.This will be described in detail with reference to FIGS. 1 (a) to 1 (f) as follows.
도 1(a)를 참조하면, 우선 소정의 구조가 형성된 반도체 기판(1)에 필드영역과 접합영역을 분리하기 위한 필드산화막(2)이 형성된다. 이후, 소정의 마스크를 이용한 이온 주입공정(n 또는 p-type 도펀트)을 행하여 반도체 기판(1)의 소정 영역에 N-Well 및 P-Well이 각각 형성된다.Referring to FIG. 1A, first, a field oxide film 2 for separating a field region and a junction region is formed on a semiconductor substrate 1 having a predetermined structure. Thereafter, an ion implantation process (n or p-type dopant) using a predetermined mask is performed to form N-Well and P-Well in predetermined regions of the semiconductor substrate 1, respectively.
도 1(b)를 참조하면, 이후, 전체 구조 상부에 소정의 두께로 스크린산화막(3)이 형성된다. 이후, 소정의 포토마스크를 이용하여 P-Well 영역 및 N-Well 영역에 대하여 각각 문턱전압(Vth) 조정 이온주입공정이 행해진다.Referring to FIG. 1B, a screen oxide film 3 is formed on the entire structure at a predetermined thickness. Thereafter, a threshold voltage Vth adjusting ion implantation process is performed on the P-Well region and the N-Well region, respectively, using a predetermined photomask.
도 1(c)를 참조하면, 이후, 스크린산화막(3)은 식각되어 제거된다. 이후, 전체 구조 상부에 게이트산화막(4)이 형성된 후, 그 상부에 도핑되지 않은 다결정실리콘(5)이 LPCVD에 의해 증착된다.Referring to FIG. 1C, afterwards, the screen oxide layer 3 is etched and removed. Thereafter, after the gate oxide film 4 is formed over the entire structure, the undoped polysilicon 5 is deposited by LPCVD.
도 1(d)를 참조하면, 이후, 도핑되지 않은 다결정실리콘(5)은 도펀트의 이온주입 공정 또는 도펀트 가스의 In-situ 증착법에 의해 P-Well 상에는 As 또는 P가주입되어 n+ 다결정실리콘(6)이 형성되고, N-Well 상에는 보론 또는 BF2가 주입되어 p+ 다결정실리콘(7)이 형성된다.Referring to FIG. 1 (d), the undoped polysilicon 5 is injected with As or P onto the P-Well by an ion implantation process of a dopant or an in-situ deposition method of a dopant gas, thereby allowing n + polysilicon 6. ) Is formed and boron or BF 2 is injected onto the N-Well to form p + polysilicon 7.
도 1(e)를 참조하면, 이후, 전체 구조 상부에 물리적 또는 화학적증착법에 의해 저저항을 가지는 금속층(8)이 형성된다. 이후, 소정의 마스크를 이용한 식각공정에 의해 금속층(8), 다결정실리콘(6,7) 및 게이트산화막(4)이 순차적으로 식각되어 게이트전극(9)이 형성된다.Referring to FIG. 1E, a metal layer 8 having low resistance is formed on the entire structure by physical or chemical vapor deposition. Thereafter, the metal layer 8, the polysilicons 6 and 7, and the gate oxide film 4 are sequentially etched by an etching process using a predetermined mask to form the gate electrode 9.
도 1(f)를 참조하면, 이후, 게이트전극(9)을 포함한 전체 구조 상부에 스페이서막이 증착된 후, 소정의 식각공정에 의해 식각되어 게이트전극(9)의 양측면에만 스페이서(10)가 형성된다.Referring to FIG. 1F, a spacer film is deposited on the entire structure including the gate electrode 9 and then etched by a predetermined etching process to form spacers 10 only on both sides of the gate electrode 9. do.
이후, 반도체 기판(1)의 소정 부위에 접합영역(11)을 형성하기 위한 소정의 이온 주입공정이 행해진다.Thereafter, a predetermined ion implantation step for forming the junction region 11 in a predetermined portion of the semiconductor substrate 1 is performed.
여기서, P-Well 영역에 n+ 이온 주입공정을 실시하는 경우, 도펀트로서 도펀트로서 As 또는 P 또는 이들의 혼합물이 사용되거나, N-Well 영역에 p+ 이온 주입공정 실시하는 경우,보론 또는 BF2또는 이들의 혼합물이 사용된다.Here, when the n + ion implantation process is performed in the P-Well region, As or P or a mixture thereof is used as the dopant as the dopant, or when the p + ion implantation process is performed in the N-Well region, boron or BF 2 or these Mixtures are used.
전술한 바와 같이, 종래 기술은 후속 열공정 진행시 p+ 다결정실리콘에 존재하는 보론이 게이트산화막을 통과하여 반도체 기판의 채널영역으로 확산하는 보론 침투현상과 게이트산화막 근처에 존재하는 보론의 활성화가 충분히 이루어지지 않는 게이트 공핍화가 여전히 발생하게 된다.As described above, in the prior art, in the subsequent thermal process, boron in the p + polysilicon passes through the gate oxide film and diffuses into the channel region of the semiconductor substrate, and boron in the vicinity of the gate oxide film is sufficiently activated. Undesired gate depletion still occurs.
여기서 보론 침투현상은 플랫-밴드전압(Flat-Band Voltage) 및 문턱전압(Threshold Votage)의 변화를 초래하고, GOI(Gate Oxide Intergrity)특성을 저하시키게 된다. 또한, 게이트 공핍화는 인버젼 캐패시턴스(Inversion Capacitance)를 감소시키고 문턱전압을 증가시키는 문제점을 초래한다.Here, boron penetration causes changes in the flat-band voltage and threshold voltage, and degrades the gate oxide intergrity (GOI) characteristics. In addition, gate depletion causes a problem of reducing the inversion capacitance and increasing the threshold voltage.
그래서 상기 p+ 다결정실리콘을 대체할 수 있는 새로운 게이트전극 물질 및 제조공정에 대한 연구가 활발히 진행되고 있는데, 그 중에서 듀얼-금속(Dual Metal) 게이트 제조법이 가장 최근에 보고되고 있다. 이 경우, 일단 금속 게이트에서는 도펀트를 사용하지 않기 때문에 보론침투 현상 및 게이트 공핍화가 근본적으로 존재하지 않는다는 장점을 활용하면서, 더 나아가 서로 다른 일함수값을 가지는 이종의 금속 게이트를 각각 NMOS 및 PMOS 영역에 사용하여 모두 표면채널을 형성하는 것을 그 특징으로 하고 있다. 여기에서 PMOS용 금속 게이트란 그 값이 실리콘의 가전자대(Valence Band) 근처에 존재하는 금속물질을 총칭한다. 그러나 아직까지는 상기 듀얼-금속 게이트전극을 실제로 제조하는데 있어서, 그 듀얼-금속물질 선정, 제조공정 및 소자특성에 대한 충분한 평가가 이루어지지 않은 상태이다.Therefore, researches on new gate electrode materials and manufacturing processes that can replace the p + polysilicon are being actively conducted, and among them, a dual metal gate manufacturing method has been recently reported. In this case, taking advantage of the fact that boron penetration and gate depletion do not exist fundamentally because dopants are not used in the metal gate, and further, heterogeneous metal gates having different work function values are respectively applied to the NMOS and PMOS regions, respectively. It is characterized by forming both surface channels by use. Here, the metal gate for PMOS refers to a metal material whose value is present near the valence band of silicon. However, in the actual manufacture of the dual-metal gate electrode, the evaluation of the dual-metal material selection, manufacturing process and device characteristics have not been made yet.
그러므로 현재로서는 NMOS 영역에서는 n+ 다결정실리콘과 금속층의 적층구조의 게이트전극을 그대로 유지하면서, PMOS 영역에서 사용하는 기존의 p+ 다결정실리콘과 금속층의 적층구조의 게이트전극만을 새로운 물질 및 새로운 구조의 게이트전극으로 대체할 수 있는 제조공정 기술의 개발이 요구된다.Therefore, in the NMOS region, only the gate electrode of the conventional p + polysilicon and the metal layer stacked structure used in the PMOS region is maintained as the gate material of the new material and the new structure while maintaining the gate electrode of the laminated structure of the n + polysilicon and the metal layer. There is a need for development of alternative manufacturing process technologies.
따라서, 본 발명은 듀얼-다결정실리콘 게이트전극에서 다마신 공정을 적용하여 p+ 다결정실리콘 게이트전극 대신에 PMOS용 금속 게이트전극을 형성하여 우수한 특성의 듀얼 게이트전극을 제조할 수 있는 반도체 소자의 제조 방법을 제공함에 있다.Accordingly, the present invention provides a method for fabricating a semiconductor device capable of producing a dual gate electrode having excellent characteristics by forming a metal gate electrode for PMOS instead of a p + polysilicon gate electrode by applying a damascene process in a dual-polysilicon gate electrode. In providing.
도 1(a) 내지 도 1(f)는 종래 기술에 따른 반도체 소자의 제조 방법을 설명하기 위해 순서적으로 도시한 반도체 소자의 단면도.1 (a) to 1 (f) are cross-sectional views of a semiconductor device sequentially shown to explain a method for manufacturing a semiconductor device according to the prior art.
도 2(a) 내지 도 2(i)는 본 발명의 일 실시예에 따른 반도체 소자의 제조 방법을 설명하기 위해 순서적으로 도시한 반도체 소자의 단면도.2 (a) to 2 (i) are cross-sectional views of semiconductor devices sequentially shown to explain a method of manufacturing a semiconductor device according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
1,21 : 반도체 기판 2,22 : 필드산화막1,21 semiconductor substrate 2,22 field oxide film
3,23 : 스크린산화막 4 : 게이트산화막3,23 screen oxide film 4: gate oxide film
5,26 : 다결정실리콘 6,27 : n+ 다결정실리콘5,26 polysilicon 6,27 n + polysilicon
7,28 : p+ 다결정실리콘 8 : 금속층7,28: p + polysilicon 8: metal layer
9,34 : 게이트전극 10,30 : 스페이서9,34 gate electrode 10,30 spacer
11,31 : 접합영역 24 : 성장층11,31 junction area 24 growth layer
25 : 게이트절연막 32 : 층간절연막25 gate insulating film 32 interlayer insulating film
33 : PMOS용 금속층33: PMOS metal layer
본 발명은 소정의 반도체 기판내에 필드산화막을 형성한후, 소정의 이온을 주입하여 P웰 영역과 N웰 영역을 형성하는 단계와; 상기 N웰 영역의 상부에 성장층을 형성하는 단계와; 상기 P웰 영역과 N웰 영역 상부에 게이트절연막 및 다결정실리콘을 도핑한 후, 상기 다결정실리콘을 이온 주입하고 패터닝하여 게이트패턴을 형성하는 단계와; 상기 게이트패턴을 마스크로 하여 P웰 영역과 N웰 영역에 접합영역을 형성하는 단계와; 상기 반도체 기판 전면에 층간절연막을 증착한 후, 상기 P웰 영역의 n+ 다결정실리콘의 표면이 노출될 때까지 CMP 공정을 실시하는 단계와; 상기 다결정실리콘을 제거한 후, 그 자리에 PMOS용 금속층을 형성하는 단계를 포함한다.The present invention provides a method comprising forming a P well region and an N well region by forming a field oxide film in a predetermined semiconductor substrate and implanting predetermined ions; Forming a growth layer on the N well region; Doping a gate insulating film and polysilicon over the P well region and the N well region, and ion implanting and patterning the polysilicon to form a gate pattern; Forming a junction region in the P well region and the N well region using the gate pattern as a mask; Depositing an interlayer insulating film on the entire surface of the semiconductor substrate, and then performing a CMP process until the surface of n + polysilicon in the P well region is exposed; After removing the polysilicon, forming a PMOS metal layer in place.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 2(a) 내지 도 2(i)는 본 발명의 일 실시예에 따른 반도체 소자의 제조 방법을 설명하기 위해 순서적으로 도시한 반도체 소자의 단면도이다.2 (a) to 2 (i) are cross-sectional views of semiconductor devices sequentially shown to explain a method of manufacturing a semiconductor device according to an embodiment of the present invention.
도 2(a)를 참조하면, 우선 소정의 구조가 형성된 반도체 기판(21)에 필드영역과 접합영역을 분리하기 위한 필드산화막(22)이 형성된다. 이후, 소정의 마스크를 이용한 이온 주입공정(n 또는 p-type 도펀트)을 행하여 반도체 기판(21)의 소정 영역에 N-Well 및 P-Well이 각각 형성된다.Referring to FIG. 2A, first, a field oxide film 22 for separating a field region and a junction region is formed on a semiconductor substrate 21 having a predetermined structure. Thereafter, an ion implantation process (n or p-type dopant) using a predetermined mask is performed to form N-Well and P-Well in predetermined regions of the semiconductor substrate 21, respectively.
도 2(b)를 참조하면, 이후, 전체 구조 상부에 소정의 두께로 스크린산화막(23)이 형성된다. 이후, 소정의 마스크를 이용하여 N-Well 영역에 대하여 문턱전압(Vth) 조정 이온주입공정이 행해진다.Referring to FIG. 2B, a screen oxide film 23 is formed on the entire structure at a predetermined thickness. Thereafter, a threshold voltage Vth adjusting ion implantation process is performed on the N-Well region using a predetermined mask.
도 2(c)를 참조하면, 이후, 전체 구조 상부에 감광막이 코팅된 후, 노광 및 현상을 통해 N-Well 영역상에 형성된 스크린산화막(23) 상부에 감광막패턴(100)이 형성된다.Referring to FIG. 2C, after the photoresist film is coated on the entire structure, the photoresist pattern 100 is formed on the screen oxide film 23 formed on the N-Well region through exposure and development.
이후, 감광막패턴(100)을 마스크로 이용한 소정의 식각공정에 의해 N-Well 영역상에 형성된 스크린산화막(23)이 제거된다.Thereafter, the screen oxide layer 23 formed on the N-Well region is removed by a predetermined etching process using the photoresist pattern 100 as a mask.
도 2(d)를 참조하면, 이후, 감광막패턴(100)이 소정의 스트립공정에 의해 제거된 후, P-Well 영역상의 스크린산화막(23)을 마스크로 이용함과 아울러 LPCVD 또는 UHV CVD법을 이용한 SEG 공정에 의해 N-Well 영역상에만 에피실리콘층(24)이 200∼500Å의 두께로 성장되어 형성된다.Referring to FIG. 2 (d), after the photoresist pattern 100 is removed by a predetermined stripping process, the screen oxide film 23 on the P-Well region is used as a mask, and the LPCVD or UHV CVD method is used. By the SEG process, the episilicon layer 24 is grown and formed on the N-Well region only to a thickness of 200 to 500 kHz.
LPCVD를 이용할 경우, 전세정 공정으로 HF 또는 BOE와 같은 산화물 식각용액을 포함하는 습식식각 공정을 진행한 후, 습식식각공정에 의해 손상된 부위를 보상하기 위한 H2경화(Bake) 공정이 800∼900℃에서 1∼5분 동안 진행된다. 이후, 각각의 유량이 10∼500sccm인 SiH2Cl2및 HCl의 반응가스가 10∼500Torr 정도의 작동압력에서 200∼500Å의 두께로 성장되어 에피실리콘층(24)이 형성된다.In case of using LPCVD, the wet etching process including an oxide etching solution such as HF or BOE is performed as a pre-cleaning process, and then the H 2 bake process for compensating for the damaged part by the wet etching process is 800 to 900. Proceed for 1-5 minutes at < RTI ID = 0.0 > Thereafter, the reaction gases of SiH 2 Cl 2 and HCl, each having a flow rate of 10 to 500 sccm, are grown to a thickness of 200 to 500 Pa at an operating pressure of about 10 to 500 Torr to form an episilicon layer 24.
UHV CVD를 이용할 경우, 각각의 유량이 1∼50sccm인 Si2H6와 Cl2가스가 400∼800℃의 온도범위와 1mTorr∼ 10Torr의 작동압력에서 200∼500Å의 두께로 성장되어 에피실리콘층(24)이 형성된다.When UHV CVD is used, the Si 2 H 6 and Cl 2 gases having a flow rate of 1 to 50 sccm are grown to a thickness of 200 to 500 kPa over a temperature range of 400 to 800 ° C. and an operating pressure of 1 mTorr to 10 Torr. 24) is formed.
도핑된 에피실리콘(24)을 이용하는 경우, N-Well 영역의 도핑농도와 비슷한 도핑농도를 갖는 에피실리콘(24)을 성장시키기 위하여 도핑가스로서 PH3또는 AsH3가스를 사용하고, 그 유량은 50∼400sccm 정도로 하며 성장속도는 50∼300Å/min정도로 실시함으로써 최종 에피실리콘층(24)의 도핑농도가 1E17~1e18 정도가 되도록 한다.When doped episilicon 24 is used, PH 3 or AsH 3 gas is used as a doping gas to grow episilicon 24 having a doping concentration similar to that of the N-Well region, and the flow rate is 50 The doping concentration of the final episilicon layer 24 is about 1E17 to 1e18 by performing the growth rate about 50-300 kW / min.
도 2(e)를 참조하면, 이후, 전체 구조 상부에 실리콘산화막 또는 질산화막 또는 고유전율막등이 성장법 또는 증착법에 의해 30∼100Å의 두께로 게이트절연막(25)이 형성된다.Referring to FIG. 2 (e), a gate insulating film 25 is formed on the entire structure in a thickness of 30 to 100 GPa by a silicon oxide film, a nitride oxide film or a high dielectric constant film by a growth method or a deposition method.
이후, 게이트절연막(25) 상부에 1000∼3000Å의 두께로 도핑되지 않은 다결정실리콘(26)이 형성된다.Thereafter, the undoped polysilicon 26 is formed on the gate insulating film 25 to a thickness of 1000 to 3000 Å.
도 2(f)를 참조하면, 이후, 도핑되지 않은 다결정실리콘(26)은 도펀트의 이온주입 공정 또는 도펀트 가스의 In-situ 증착법에 의해 As 또는 P가 도핑된 n+ 다결정실리콘(27)이 형성된다.Referring to FIG. 2 (f), n + polysilicon 27 doped with As or P is formed by the dopant ion implantation process or the in-situ deposition method of the dopant gas. .
이후, 소정의 마스크를 이용한 식각공정에 의해 n+ 다결정실리콘(27) 및 게이트절연막(25)이 순차적으로 식각되어 게이트전극 패턴이 형성된다.Thereafter, the n + polysilicon 27 and the gate insulating layer 25 are sequentially etched by an etching process using a predetermined mask to form a gate electrode pattern.
도 2(g)를 참조하면, 이후, 전체 구조 상부에 스페이서막이 증착된 후, 소정의 식각공정에 의해 식각되어 게이트전극 패턴의 양측면에만 스페이서(30)가 형성된다.Referring to FIG. 2 (g), after the spacer layer is deposited on the entire structure, the spacer layer 30 is formed only on both sides of the gate electrode pattern by etching by a predetermined etching process.
이후, 반도체 기판(21)의 소정 부위에 접합영역(31)을 형성하기 위한 소정의 이온 주입공정이 행해진다.Thereafter, a predetermined ion implantation step for forming the junction region 31 in a predetermined portion of the semiconductor substrate 21 is performed.
여기서, P-Well 영역에 n+ 이온 주입공정을 실시하는 경우, 도펀트로서 As 또는 P 또는 이들의 혼합물이 사용되거나, N-Well 영역에 p+ 이온 주입공정 실시하는 경우,보론 또는 BF2또는 이들의 혼합물이 사용된다.Here, when the n + ion implantation process is performed in the P-Well region, As or P or a mixture thereof is used as the dopant, or when the p + ion implantation process is performed in the N-Well region, boron or BF 2 or a mixture thereof This is used.
이후, 전체 구조 상부에 4000∼6000Å의 두께로 층간절연막(32)이 증착된 후, CMP공정에 의해 N-Well 영역의 n+ 다결정실리콘(27)이 노출되도록 패터닝된다.Thereafter, an interlayer insulating film 32 is deposited on the entire structure to a thickness of 4000 to 6000 GPa, and then patterned to expose the n + polysilicon 27 in the N-Well region by a CMP process.
도 2(h)를 참조하면, 이후, 소정의 식각공정에 의해 N-Well 상의 n+ 다결정실리콘(27)이 완전히 식각되어 에피실리콘층(24)이 노출됨과 아울러 P-Well 상의 n+ 다결정실리콘(27)은 에피실리콘층(24) 두께정도에 해당하는 두께만큼이 남도록 식각공정 조건이 설정된다. 여기서 식각공정은 습식 또는 건식식각으로 행해진다.Referring to FIG. 2 (h), the n + polysilicon 27 on the N-Well is completely etched by a predetermined etching process to expose the episilicon layer 24 and the n + polysilicon 27 on the P-Well. ), The etching process conditions are set such that the thickness corresponding to the thickness of the episilicon layer 24 remains. The etching process is performed by wet or dry etching.
도 2(i)를 참조하면, 이후, 전체 구조 상부에 물리적 또는 화학적 증착법에 의해 PMOS용 금속층(33)이 증착된 후, CMP 처리되어 층간절연막(32) 상부에 증착된 PMOS용 금속층(33)이 모두 제거된다.Referring to FIG. 2 (i), after the PMOS metal layer 33 is deposited on the entire structure by physical or chemical vapor deposition, the PMOS metal layer 33 deposited on the interlayer insulating layer 32 by CMP treatment is deposited. All of this is removed.
전술한 바와 같이, 본 발명은 통상적인 다마신 제조공정을 기본으로 하고 여기에 SEG 공정을 추가 실시하여 N-Well 영역의 반도체 기판 상부에 에피실리콘층을 형성함으로써 그 두께만큼의 단차를 부여하게 된다. 그 결과 후속 다결정실리콘을 제거하기 위한 소정의 식각공정시 P-Well 영역에는 n+ 다결정실리콘이 소정의 높이로 남게 된다. 그리고 나서 금속층을 증착한 후, CMP 처리하여 P-Well 영역에는 n+ 다결정실리콘과 금속층의 적층구조의 게이트전극이 형성되고, N-Well 영역에는 PMOS용 금속층의 단일 게이트전극이 형성되어 새로운 듀얼 게이트전극을 제조할 수 있다.As described above, the present invention is based on a conventional damascene manufacturing process, and an SEG process is further added thereto to form an episilicon layer on the semiconductor substrate in the N-Well region, thereby providing a step corresponding to the thickness thereof. . As a result, n + polysilicon remains at a predetermined height in the P-Well region during a predetermined etching process for removing subsequent polycrystalline silicon. Then, after depositing the metal layer, a gate electrode having a stacked structure of n + polysilicon and a metal layer is formed in the P-Well region by CMP treatment, and a single gate electrode of the metal layer for PMOS is formed in the N-Well region, thereby forming a new dual gate electrode. Can be prepared.
상술한 바와 같이, 본 발명은 통상적인 다마신 제조공정에 SEG 공정을 도입하여 P-Well 영역에는 n+ 다결정실리콘과 금속층의 적층구조의 게이트전극이 형성되고 N-Well 영역에는 PMOS용 금속층의 단일 게이트전극이 형성되는 듀얼 게이트전극을 형성함으로써, 게이트전극에서 발생하는 게이트 공핍화 및 보론침투 현상으로 인한 소자의 특성저하를 방지할 수 있다.As described above, the present invention introduces a SEG process into a conventional damascene manufacturing process, so that a gate electrode having a stacked structure of n + polysilicon and a metal layer is formed in a P-Well region, and a single gate of a PMOS metal layer is formed in an N-Well region. By forming the dual gate electrode on which the electrode is formed, it is possible to prevent the deterioration of the device characteristics due to the gate depletion and boron penetration phenomenon occurring in the gate electrode.
더 나아가, 다마신 공정 및 에피채널의 장점을 도입함으로써, 고집적 및 고성능의 반도체 소자를 제조할 수 있다.Furthermore, by introducing the advantages of the damascene process and the epichannel, it is possible to manufacture highly integrated and high performance semiconductor devices.
Claims (10)
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