KR20030003379A - Method of manufacturing of MOSFET - Google Patents
Method of manufacturing of MOSFET Download PDFInfo
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- KR20030003379A KR20030003379A KR1020010039116A KR20010039116A KR20030003379A KR 20030003379 A KR20030003379 A KR 20030003379A KR 1020010039116 A KR1020010039116 A KR 1020010039116A KR 20010039116 A KR20010039116 A KR 20010039116A KR 20030003379 A KR20030003379 A KR 20030003379A
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- insulating film
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- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 238000000034 method Methods 0.000 claims abstract description 38
- 125000006850 spacer group Chemical group 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 239000004065 semiconductor Substances 0.000 claims abstract description 10
- 238000000151 deposition Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 7
- -1 LDD nitride Chemical class 0.000 claims description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 2
- 229910021332 silicide Inorganic materials 0.000 claims description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 7
- 239000010703 silicon Substances 0.000 abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 230000001052 transient effect Effects 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000007792 addition Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 MOSFET 제조방법에 관한 것으로, 보다 상세하게는 HLD(high temperature low pressure deposition) 배리어를 이용하여 폴리실리콘 양측의 일부분을 스페이서의 형태의 절연막으로 덮은 후, 이 스페이서를 SEG(selective expitaxial growth)공정시에 게이트 전극에서의 에피실리콘막 성장장벽으로 이용하여 게이트 상부에 형성되는 폴리실리콘의 폭을 상부뿐만 아니라 양측면까지 연장되도록 형성하여, 저저항의 게이트 샐리사이드를 형성하는 방법에 관한 것이다.The present invention relates to a method for manufacturing a MOSFET, and more particularly, by covering a portion of both sides of a polysilicon with an insulating film in the form of a spacer using a high temperature low pressure deposition (HLD) barrier, the spacer is then subjected to selective expitaxial growth (SEG). A method of forming a low-resistance gate salicide by forming the low-resistance gate salicide by using the epi-silicon film growth barrier in the gate electrode to extend the width of the polysilicon formed on the gate to both sides as well as the upper side during the process.
CMOS 논리소자의 집적도가 증가함에 따라 단채널 효과를 억제하기 위한 접합면을 극도로 얇게 형성하기 위한 많은 시도가 이루어지고 있다. 또한, 게이트 폴리실리콘의 선폭이 줄어듬에 따라 게이트 폴리실리콘 위의 샐리사이드 저항이 높아져 소자의 게이트 지연시간을 높일 뿐 아니라, 샐리사이드의 열안정성까지 떨어져 소자의 신뢰성에도 큰 문제가 된다.As the degree of integration of CMOS logic devices increases, many attempts have been made to form extremely thin junctions to suppress short channel effects. In addition, as the line width of the gate polysilicon decreases, the salicide resistance on the gate polysilicon is increased, thereby increasing the gate delay time of the device, and reducing the thermal stability of the salicide.
종래의 게이트전극의 샐리사이드 형성방법은 게이트 전극의 상부에만 샐리사이드를 형성하므로, 0.15㎛ 이하의 설계룰에서는 샐리사이드의 폭이 좁게 형성이 되어 게이트의 저항이 높아서, 소자의 게이트 지연시간이 길어지는 문제점뿐만 아니라, 소스/드레인 영역에서의 극히 얇은 접합면을 구현하기 어렵다는 문제점이 있다.In the conventional method of forming the salicide of the gate electrode, the salicide is formed only on the upper portion of the gate electrode. In the design rule of 0.15 µm or less, the width of the salicide is formed to be narrow, so that the gate resistance is high and the gate delay time of the device is long. In addition to losing, there is a problem that it is difficult to realize an extremely thin bonding surface in the source / drain region.
본 발명은 상기의 문제점을 해결하기 위한 것으로서, 폭이 넓은 게이트 샐리사이드 형성방법을 제공하여, 게이트 저항을 감소시켜 게이트 지연시간을 감소시키고 소스/드레인 영역에서의 극히 얇은 접합면을 구현하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a method for forming a wide gate salicide to reduce the gate resistance to reduce the gate delay time and to realize an extremely thin junction in the source / drain region. There is this.
도 1a 내지 도 1f는 본 발명의 실시례에 따른 MOSFET 제조공정을 도시하는 단면도.1A to 1F are cross-sectional views illustrating a MOSFET manufacturing process according to an embodiment of the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
10 : 게이트 전극22 : 제1 절연막 스페이서10 gate electrode 22 first insulating film spacer
32 : 제1 에피실리콘막34 : 제2 에피실리콘막32: first episilicon film 34: second episilicon film
42 : 제2 절연막 스페이서52 : 제1 샐리사이드42 second insulating film spacer 52 first salicide
54 : 제2 샐리사이드54: second salicide
상기한 목적을 달성하기 위하여, 본 발명에 의한 MOSFET 제조방법은 반도체 기판상에 게이트 산화막이 개재되어있는 게이트전극을 형성하는 제1 단계, 상기 게이트전극의 측벽에 제1 절연막 스페이서를 형성하되 상기 게이트전극의 측벽의 상부는 노출되도록 형성하는 제2 단계, 상기 노출되어 있는 반도체기판과 게이트 전극의 표면에 에피실리콘막을 형성하는 제3 단계, 상기 제1 절연막 스페이서의 표면에 제2 절연막 스페이서를 형성하는 제4 단계, 및 상기 반도체기판과 상기 게이트전극의 표면의 에피실리콘층상에 실리사이드막을 형성하는 제5 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, the MOSFET manufacturing method according to the present invention is a first step of forming a gate electrode interposed a gate oxide film on a semiconductor substrate, forming a first insulating film spacer on the sidewall of the gate electrode, the gate A second step of forming an upper portion of the sidewall of the electrode to be exposed, a third step of forming an episilicon film on the exposed semiconductor substrate and the gate electrode, and forming a second insulating film spacer on the surface of the first insulating film spacer And a fifth step of forming a silicide film on the episilicon layer on the surfaces of the semiconductor substrate and the gate electrode.
상술한 목적 및 기타의 목적과 본 발명의 특징 및 이점은 첨부된 도면과 관련한 다음의 상세한 설명을 통하여 보다 분명해 질 것이다. 이하, 첨부된 도면을 참조하여 본 발명의 실시예를 상세히 설명하면 다음과 같다.The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1f는 본 발명의 실시례에 따른 게이트 샐리사이드 형성공정의 단면도이다.1A to 1F are cross-sectional views of a gate salicide forming process according to an exemplary embodiment of the present invention.
먼저, 도 1a 및 도 1b에 도시된 바와 같이, 게이트 산화막과 게이트 폴리에피실리콘막의 적층구조로 형성된 게이트전극(10)과 소스/드레인이 형성될 영역을 포함하는 반도체 기판 상에 게이트전극(10)의 양측에 제1 절연막 스페이서(22)를 형성하되 제1 절연막 스페이서(22)의 높이는 게이트전극(10)의 높이보다 낮도록 형성하고, 반도체 기판에 LDD 이온을 주입하여 소스/드레인 영역을 형성하는 단계를 거친다.First, as shown in FIGS. 1A and 1B, the gate electrode 10 is formed on a semiconductor substrate including a gate electrode 10 formed in a stacked structure of a gate oxide film and a gate poly epi silicon film and a region in which a source / drain is to be formed. Forming first insulating film spacers 22 on both sides of the first insulating film spacers 22 so that the height of the first insulating film spacers 22 is lower than that of the gate electrode 10, and implanting LDD ions into the semiconductor substrate to form source / drain regions. Go through the steps
바람직하게는, 제1 절연막 스페이서(22)는 HLD를 이용하여 제1 절연막(20)을 증착하고(도 1a 참조) 건식각으로 과도식각하여 형성할 수 있다(도 1b 참조). 더욱 바람직하게는, 증착되는 제1 절연막(20)의 두께는 100Å으로 할 수 있다.Preferably, the first insulating film spacer 22 may be formed by depositing the first insulating film 20 using HLD (see FIG. 1A) and over-etching dry etching (see FIG. 1B). More preferably, the thickness of the first insulating film 20 to be deposited may be 100 kPa.
제1 절연막 스페이서(22)의 높이는 게이트전극(10)의 높이보다 낮도록 과도식각하여 형성하는 이유는, 후속 공정에서 게이트전극(10)의 상부에 에피실리콘막(32)을 형성하는 경우에, 에피실리콘막(32)의 형성장벽으로 사용하기위해서이다. 따라서, 제1 절연막 스페이서(22)의 높이가 낮을수록, 즉 제1 과도식각 두께(24)가 클수록 후속 공정에서 형성되는 게이트 샐리사이드막(52)의 폭이 게이트전극(10)의 측면으로 연장되어 증가하므로 게이트 저항이 감소하게 된다. 바람직하게는, 제1 절연막(20) 스페이서(22)가 형성되지 않은 게이트전극(10)의 측면의 두께는 100Å 내지 500Å으로 할 수 있다.The reason why the height of the first insulating layer spacer 22 is overetched to be lower than the height of the gate electrode 10 is that the episilicon film 32 is formed on the gate electrode 10 in a subsequent process. This is for use as a barrier to the formation of the episilicon film 32. Therefore, the lower the height of the first insulating layer spacer 22, that is, the larger the first transient etching thickness 24, the width of the gate salicide layer 52 formed in a subsequent process extends to the side of the gate electrode 10. The gate resistance decreases as the gate resistance increases. Preferably, the thickness of the side surface of the gate electrode 10 on which the first insulating film 20 spacer 22 is not formed may be 100 kPa to 500 kPa.
다음으로, 도 1c에 도시된 바와 같이, 게이트전극(10)의 상부 및 제1 절연막 스페이서(22)가 형성되지 않은 게이트전극(10)의 양측을 둘러싸도록 제1 에피실리콘막(32)을 형성하며, 제1 에피실리콘막(32)과 분리하여 소스/드레인이 형성될 영역의 상부 및 제1 절연막 스페이서(22)의 측면에 제2 에피실리콘막(34)을 형성하는 단계를 거친다.Next, as shown in FIG. 1C, the first episilicon layer 32 is formed to surround both sides of the gate electrode 10 and the gate electrode 10 on which the first insulating layer spacer 22 is not formed. The second episilicon layer 34 is formed on the side of the first insulating layer spacer 22 and the upper portion of the region where the source / drain is to be formed, separated from the first episilicon layer 32.
바람직하게는, 제1 에피실리콘막(32) 및 제2 에피실리콘막(34)은 SEG 방법으로 형성할 수 있다. 따라서, 절연막인 제1 절연막 스페이서(22)에는 실리콘층이 형성되지 않고, 게이트전극(10)의 상부 및 제1 절연막 스페이스(22)를 양쪽 경계로 하여 노출된 양측면에 도시된 바와 같이 제1 에피실리콘막(32)이 형성되고, 소스/드레인 영역에는 제2 에피실리콘막(34)이 각각 분리되어 형성된다.Preferably, the first episilicon film 32 and the second episilicon film 34 may be formed by the SEG method. Therefore, a silicon layer is not formed in the first insulating film spacer 22, which is an insulating film, and the first epi, as shown on both sides of the gate electrode 10 and the first insulating film space 22, are exposed at both boundaries. The silicon film 32 is formed, and the second episilicon film 34 is separately formed in the source / drain regions.
바람직하게는 상기 에피실리콘막(32,34)은 Si 또는 SiGe으로 형성될 수 있고, 에피실리콘막(32,34)의 형성두께는 400Å으로 할 수 있다. 더욱, 바람직하게는 상기 에피실리콘막(32,34)을 SEG로 형성할 때 조건은, 성장온도는 700℃ 내지 900℃, 성장압력은 1Torr 내지 50Torr, 성장가스는 DCS, Si2H6, SiCl2H2, 식각가스는HCl로 할 수 있다.Preferably, the episilicon films 32 and 34 may be formed of Si or SiGe, and the epitaxial films 32 and 34 may have a thickness of 400 kPa. More preferably, when the episilicon films 32 and 34 are formed of SEG, the growth temperature is 700 ° C. to 900 ° C., the growth pressure is 1 Torr to 50 Torr, and the growth gas is DCS, Si 2 H 6 , SiCl. 2 H 2 , etching gas can be HCl.
다음으로, 도 1d 및 도 1e에 도시된 바와 같이, 제1 에피실리콘막(32)과 제2 에피실리콘막(34) 사이의 노출될 제1 절연막 스페이서(22)의 사면에 적층구조로 제2 절연막 스페이서(42)를 형성하는 단계를 거친다.Next, as shown in FIGS. 1D and 1E, the second structure is laminated on the slope of the first insulating film spacer 22 to be exposed between the first episilicon film 32 and the second episilicon film 34. The insulating film spacer 42 is formed.
제2 절연막 스페이서(42)의 형성방법은 도 1d에 도시된 바와 같이, 게이트전극(10)을 포함한 반도체 전면에 제2 절연막(40)을 증착하고 도 1e에 도시된 바와 같이 건식각으로 과도식각을 하여 형성한다. 제1 절연막 스페이서(22)와 마찬가지로 과도식각을 많이 하여 제2 과도식각 두께(44)가 클수록 게이트 저항을 감소시킬 수 있다.In the method of forming the second insulating film spacer 42, as shown in FIG. 1D, the second insulating film 40 is deposited on the entire surface of the semiconductor including the gate electrode 10 and transiently etched by dry etching as shown in FIG. 1E. To form. As with the first insulating layer spacer 22, the gate resistance can be reduced by increasing the transient etching to increase the second transient etching thickness 44.
바람직하게는, 제2 절연막(40)은 LDD 질화막으로 할 수 있다. 더욱 바람직하게는 제2 절연막(40)의 증착두께는 200Å 내지 700Å으로 할 수 있으며, 제2 과도식각 두께(44)는 100Å 내지 500Å으로 할 수 있다.Preferably, the second insulating film 40 may be an LDD nitride film. More preferably, the deposition thickness of the second insulating film 40 may be 200 kPa to 700 kPa, and the second transient etching thickness 44 may be 100 kPa to 500 kPa.
다음으로, 도 1f에 도시된 바와 같이, 제1 에피실리콘막(32)과 제2 에피실리콘막(34)의 상부에 각각 제1 샐리사이드막(52), 제2 샐리사이드막(54)을 형성하는 단계를 거친다. 샐리사이드막(52,54)을 형성하는 방법은 종래의 방법과 동일하게 할 수 있다. 즉, 금속막을 증착한 후 열처리를 하여 샐리사이드(52,54)를 형성하지 않은 금속막부분을 제거함으로써 샐리사이드막(52,54)를 형성한다.Next, as shown in FIG. 1F, the first salicide layer 52 and the second salicide layer 54 are respectively disposed on the first episilicon layer 32 and the second episilicon layer 34. Go through the steps of forming. The method of forming the salicide films 52 and 54 can be the same as the conventional method. In other words, the salicide films 52 and 54 are formed by removing the metal film portion where the salicide 52 and 54 are not formed by performing heat treatment after depositing the metal film.
게이트전극(10)의 상부의 제1 샐리사이드막(52)은, 게이트전극(10)의 상부에만 형성되는 종래의 샐리사이드막과 달리 양측면과 아래방향으로 확장되어 그 선폭이 확장되는 효과로 인해 게이트저항은 감소하게 되는 것이다.Unlike the conventional salicide layer formed only on the gate electrode 10, the first salicide layer 52 formed on the upper portion of the gate electrode 10 extends in both sides and downwards, and thus the line width thereof is expanded. The gate resistance is to be reduced.
이상에서 설명한 바와 같이 본 발명에 따른 게이트 샐리사이드 형성방법에 의하면, 0.15㎛이하의 기술에 의한 로직 CMOS 제조시 게이트 샐리사이드의 형성면적을 증가시킴으로써, 게이트 저항을 감소시켜, 게이트 지연시간을 단축할 수 있으며, 소스/드레인 영역에서의 극히 얕은 접합면을 형성할 수 있는 현저한 효과가 있다.As described above, according to the method for forming a gate salicide according to the present invention, by increasing the formation area of the gate salicide in a logic CMOS fabrication process using a technique of 0.15 μm or less, the gate resistance can be reduced and the gate delay time can be shortened. And has the significant effect of forming an extremely shallow junction in the source / drain region.
아울러 본 발명의 바람직한 실시예들은 예시의 목적을 위해 개시된 것이며, 당업자라면 본 발명의 사상과 범위 안에서 다양한 수정, 변경, 부가 등이 가능할 것이며, 이러한 수정 변경 등은 이하의 특허청구의 범위에 속하는 것으로 보아야 할 것이다.In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to make various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and modifications belong to the scope of the claims You will have to look.
Claims (15)
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07202184A (en) * | 1993-12-28 | 1995-08-04 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
| JPH08241988A (en) * | 1995-03-03 | 1996-09-17 | Hitachi Ltd | Semiconductor integrated circuit device and fabrication thereof |
| JPH0974199A (en) * | 1995-01-12 | 1997-03-18 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacture |
| KR19990084304A (en) * | 1998-05-04 | 1999-12-06 | 김영환 | Semiconductor device and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07202184A (en) * | 1993-12-28 | 1995-08-04 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
| JPH0974199A (en) * | 1995-01-12 | 1997-03-18 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacture |
| JPH08241988A (en) * | 1995-03-03 | 1996-09-17 | Hitachi Ltd | Semiconductor integrated circuit device and fabrication thereof |
| KR19990084304A (en) * | 1998-05-04 | 1999-12-06 | 김영환 | Semiconductor device and manufacturing method thereof |
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