KR100464271B1 - Method for manufacturing mosfet of the semiconductor device - Google Patents

Abstract

The present invention relates to a method of manufacturing a MOS field effect transistor of a semiconductor device, and more particularly, to a method of manufacturing the present invention, a gate insulating film, an undoped polysilicon film, and a hard mask film are sequentially stacked on an active region of a semiconductor substrate, Patterning these films by an etching process, forming source / drain regions in the substrate, depositing an interlayer insulating film over the entire surface of the resultant, and planarizing the surface of the hard mask film, selectively removing only the hard mask film Forming a trench, implanting a dopant into the polysilicon film by performing a dopant ion implantation process on the entire surface of the structure, depositing a metal film to fill the trench, and removing the metal film at the interlayer insulating layer to remove the doped polysilicon and the metal Forming the stacked gate electrodes Include. Accordingly, in the present invention, the surface resistance of the gate electrode is kept low by the metal film, so that the driving of the transistor depends on the polysilicon film in contact with the gate insulating film.

Description

METHODS FOR MANUFACTURING MOSFET OF THE SEMICONDUCTOR DEVICE

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a MOS field effect transistor of a semiconductor device capable of improving a driving speed of a transistor by reducing a gate resistance value at a gate electrode of a highly integrated semiconductor device.

As the development of semiconductor device manufacturing technology and its application field have been expanded, research and development on the increase in the degree of integration of semiconductor devices have been steadily developing. As the degree of integration of semiconductor devices increases, researches based on the technology for miniaturization of devices are being promoted.

Accordingly, as semiconductor devices are highly integrated with the miniaturization of semiconductor devices, wiring line widths of gate electrodes or bit lines of metal oxide semiconductor field effect transistors are also decreasing.

1 is a view showing a vertical structure of a MOS field effect transistor of a semiconductor device according to the prior art. Referring to Figure 1, the transistor manufacturing process according to the prior art is as follows.

First, as the semiconductor substrate 10, an isolation process is performed on a silicon substrate to form an isolation layer 12 that divides an active region and an isolation region of a device. A thermal oxide film is formed as the gate insulating film 14 over the substrate 10, and a doped polysilicon 16 and a silicide layer 18 are deposited thereon as a gate conductive film. A photolithography process is performed on the silicide layer 18 to form a photoresist pattern defining a gate electrode region, and a dry etching process using the photoresist pattern is performed to pattern the silicide layer 18 and doped polysilicon thereunder. The gate insulating film 14 is patterned after the gate electrode is formed by patterning the film 16. And the photoresist pattern is removed.

Impurity dopant ion implantation, such as n-ion implantation, is then performed to form lightly doped drain (LDD) regions 20 spaced apart from each other with the gate electrodes 16 and 18 interposed therebetween in the substrate, and as silicon as an insulating film on the entire surface of the substrate. A nitride film is deposited and dry etched to form spacers 22 on sidewalls of the gate electrodes 16 and 18. Impurity dopant ion implantation, such as n + ion implantation, using the gate electrodes 16 and 18 and the spacer 22 as a mask, is performed so as to be spaced apart from each other with the gate electrodes 16 and 18 and the spacer 22 interposed in the substrate. / Drain region 24 is formed.

In addition, a silicide metal layer such as titanium (Ti) is deposited on the entire surface of the substrate, and then annealed, leaving only the metal that has been silicide-reacted with the lower silicon, and removing the remaining unreacted metal. The film 26 is formed to lower the contact resistance of the region.

Subsequently, a thin silicon nitride film is deposited as an etch stop layer 28 on the entire surface of the substrate, and at least one or more interlayer insulating films (PMDs) 30 and 32 as BoroPhospho Silicate Glass are formed thereon. Or PSG (Phospho Silicate Glass) is deposited and annealed. The surface of the interlayer insulating film 32 is then planarized by chemical mechanical polishing. Although not shown in the drawings, a buffer layer may be further formed on the interlayer insulating layer 32 to compensate for the scratches generated during the chemical mechanical polishing process.

Then, a photoresist pattern (not shown) for defining a contact hole region is formed on the interlayer insulating layer 32 and a dry etching process using the interlayer insulating layer 32 is performed to form the interlayer insulating layers 32 and 30 and the etch stop layer 28. Etching forms a contact hole in which the silicide layer 18 as the gate electrode of the MOS field effect transistor and the silicide layer 26 in the source / drain region 24 are exposed. After the photoresist pattern is removed, a wiring process is performed to deposit doped polysilicon or metal as a conductive film on the interlayer insulating films 30 and 32 and to pattern the doped polysilicon or metal to be connected to the gate electrode and the source / drain region of the MOS field effect transistor. The contact 34 and the wiring 36 are formed.

However, in recent years, the line width (CD) of the gate electrode is reduced due to the high integration of the semiconductor device. As the line width of the gate electrode decreases, the surface resistance of the gate electrode increases. Thus, although the gate electrode is composed of a polyside in which a polysilicon film and silicide are laminated, there is a limit in lowering the resistance of the gate electrode. Therefore, if the resistance of the gate electrode is increased, the word line driving speed of the MOS field effect transistor is slowed down, resulting in a decrease in the performance of the transistor.

An object of the present invention is to solve the problems of the prior art as described above to configure a low resistance gate electrode in which a metal layer is laminated on the polysilicon layer, the gate electrode is lowered by manufacturing the gate electrode without affecting the lower structure The present invention provides a method of manufacturing a MOS field effect transistor of a semiconductor device capable of rapidly improving a driving speed of a transistor by a resistance value.

In order to achieve the above object, the present invention provides a method for manufacturing a MOS field effect transistor having a gate electrode, a source / drain, and sequentially laminating a gate insulating film, an undoped polysilicon film, and a hard mask film on an active region of a semiconductor substrate. Patterning these films by an etching process using a gate mask, forming a source / drain region in the substrate, depositing an interlayer insulating film on the entire surface of the resultant, and planarizing the surface of the hard mask film; Selectively removing the trench to form a trench; dopant ion implantation into the entire surface of the structure to inject the dopant into the polysilicon layer; depositing a metal film to fill the trench; Polysilicon and metal laminated gates A includes forming.

1 is a view showing a vertical structure of a MOS field effect transistor of a semiconductor device according to the prior art,

2 is a view showing a vertical structure of a MOS field effect transistor of a semiconductor device manufactured according to the present invention;

3A to 3H are flowcharts sequentially illustrating a method of manufacturing a MOS field effect transistor according to an embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

2 is a view showing a vertical structure of a MOS field effect transistor of a semiconductor device manufactured according to the present invention. Referring to FIG. 2, since the gate electrode of the MOS field effect transistor according to the present invention has a stacked structure in which a doped polysilicon film 106 and a metal film 126a are stacked, the gate electrode is formed by the metal film 126a. The resistance will be lowered. In particular, when the metal film 126a of the gate electrode of the present invention is patterned in a wider Tn group than the lower polysilicon film 106, the surface resistance of the electrode is lowered by the wide metal film 126a on the upper side, and thus the driving capability of the transistor is reduced. Is controlled by the lower polysilicon film 106, so that the driving capability of the transistor is increased.

3A to 3H are flowcharts sequentially illustrating a method of manufacturing a MOS field effect transistor according to an exemplary embodiment of the present invention. Referring to these drawings, a transistor having a gate electrode of the polysilicon film / metal film shown in FIG. The manufacturing process of this is demonstrated.

As shown in FIG. 3A, a device isolation process is performed on a silicon substrate as a semiconductor substrate 100 to form a device isolation layer 102 that separates an active region and a device isolation region of the device. After forming a thermal oxide film as the gate insulating film 104 on the entire surface of the substrate 100 and depositing an undoped polysilicon 106 as the gate conductive film thereon, a hard mask layer 108 is formed. A silicon nitride film (Si3N4) is deposited. At this time, the undoped polysilicon film 106 is deposited at about 500 kPa to 1000 kPa. If the thickness is too thick, the thickness of the metal film for gate electrodes is reduced, so that the undoped polysilicon film 106 cannot be lowered to a desired resistance value.

Then, a photolithography process is performed on the hard mask layer 108 to form a photoresist pattern defining a gate electrode region, and a dry etching process using the photoresist pattern is performed to pattern the hard mask layer 108 and below it. After the undoped polysilicon film 106 is patterned, the gate insulating film 104 is patterned. And the photoresist pattern is removed.

Next, as shown in FIG. 3B, impurity dopant ion implantation, such as n-ion implantation, is performed to form the LDD regions 110 spaced apart from each other with the undoped polysilicon film 106 interposed therebetween in the substrate and on the front surface of the substrate. A silicon nitride film is deposited as an insulating film and dry-etched to form a spacer 112 on the sidewall of the undoped polysilicon film 106. Impurity dopant ion implantation, such as n + ion implantation, is performed using the undoped polysilicon film 106 and the spacer 112 as a mask to form a source / drain region 114 in the substrate.

In addition, a silicide metal layer such as titanium (Ti) is deposited on the entire surface of the substrate, and then annealed, leaving only the metal that has been silicide-reacted with the lower silicon, and removing the remaining unreacted metal to the silicide surface of the source / drain region 114. The film 116 is formed to lower the contact resistance of the region.

Subsequently, as shown in FIG. 3C, a thin silicon nitride film is deposited as an etch stop film 118 on the entire surface of the resultant, and a BPSG or PSG is deposited and annealed on the first interlayer insulating film 120 thereon. Then, the surface of the first interlayer insulating film 120 is planarized by chemical mechanical polishing, and the planarization is performed until the surface of the hard mask film 108 is exposed.

Subsequently, as shown in FIG. 3D, only the hard mask film 108 is selectively removed to form the trench 122 through which the undoped polysilicon film 106 of the gate electrode region is exposed. The n- or p- dopant is implanted into the polysilicon film 106 by performing a dopant ion implantation, for example, an n- or p- ion implantation process on the entire surface of the substrate.

Subsequently, as shown in FIG. 3E, a barrier metal film 124, such as tantalum (Ta) or tantalum nitride (TaN), is deposited and annealed on the entire surface of the structure to form a lower doped polysilicon film 106 and the barrier metal. A thin silicide film (not shown) is formed between the films 124.

Then, as shown in FIGS. 3F and 3G, tungsten (W) is deposited as the metal film 126 to fill the trench of the structure, and the metal film 126 of the trench region is formed on the first interlayer insulating film 120. And patterning 126a and 124a so that only the barrier metal film 124 remains. Alternatively, the surface of the first interlayer insulating layer 120 may be flattened by a chemical mechanical polishing process until the surface of the first interlayer insulating layer 120 is exposed, leaving only the metal layer 126a and the barrier metal layer 124a in the trench region of the gate electrode. Both film 126 and barrier metal film 124 are to be removed. Accordingly, the gate electrode of the present invention has a stack structure in which the doped polysilicon film 106 and the metal film 126a are stacked, thereby lowering the surface resistance of the gate electrode surface. In addition, the present invention provides a resistance value of the gate electrode by forming a gate electrode having a multilayer structure in which a silicide film (not shown) and a barrier metal film 124a are added between the doped polysilicon film 106 and the metal film 126a. Can be lowered further.

Meanwhile, during the gate electrode patterning process of the trench region, the metal layer 126 and the barrier metal layer 124 are patterned to have a wider width than the doped polysilicon layer 106 to manufacture a gate electrode having a T structure. can do. Alternatively, the self-aligned gate electrode may be manufactured by patterning the metal layer 126 to have the same width as the doped polysilicon layer 106 under the barrier metal layer 124.

Then, as shown in FIG. 3H, an Undoped Silicate Glass (USG) or High Doped Plasma (HDP) oxide film is deposited as a second interlayer insulating film 128 on the entire surface of the substrate and planarized by a chemical mechanical polishing process. In this case, a buffer layer may be further formed on the second interlayer insulating layer 128 to compensate for scratches generated during the chemical mechanical polishing process. Thereafter, the second and first interlayer insulating layers 128 and 120 and the etch stop layer 28 are etched by dry etching using a contact mask to form the silicide layer of the metal layer 126a of the gate electrode and the source / drain region 114. A contact hole through which the 116 is exposed is formed and a wiring process is performed to form a contact 130 in which a doped polysilicon or metal is embedded and a wiring 132 connected to the contact as a conductive layer in the contact hole.

As described above, according to the present invention, after fabricating a MOS field effect transistor as usual, only a hard mask film is removed in the interlayer insulating film to form a trench in which a polysilicon film is exposed, and a barrier metal film and a metal film are embedded in the trench to form polysilicon. A gate electrode having a stacked structure in which a film and a metal film are stacked is manufactured, but the gate electrode is manufactured without affecting the underlying structure.

Therefore, the present invention has an effect that a high-performance transistor can be implemented to increase the driving speed of the transistor because the surface resistance of the gate electrode is kept low by the metal film, so that the driving of the transistor depends on the polysilicon film in contact with the gate insulating film.

On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.

Claims (11)

In the method of manufacturing a MOS field effect transistor having a gate electrode, a source / drain, Sequentially stacking a gate insulating film, an undoped polysilicon film, and a hard mask film over an active region of the semiconductor substrate and patterning the films by an etching process using a gate mask; Forming a source / drain region in the substrate; Depositing an interlayer insulating film on the entire surface of the resultant and planarizing the surface of the hard mask layer; Selectively removing only the hard mask layer to form a trench; Implanting a dopant into the polysilicon layer by performing a dopant ion implantation process on the entire surface of the structure; And And forming a gate electrode on which the doped polysilicon and the metal are stacked by depositing a metal film to fill the trench and removing the metal film of the interlayer insulating layer. Way. The semiconductor of claim 1, further comprising forming spacers of an insulating material on sidewalls of the patterned gate insulating film, the undoped polysilicon film, and the hard mask film before forming the source / drain regions. A method of manufacturing a MOS field effect transistor of an element. The method of claim 1, wherein the source / drain region has an LDD structure. The method of claim 1, further comprising forming a silicide film on a surface of the source / drain region after the source / drain region is formed. The method of claim 1, further comprising forming a barrier metal film on the entire surface of the structure having the trench after implanting the dopant into the polysilicon film. The method of claim 5, further comprising the step of annealing after forming the barrier metal film to form a thin silicide film between the doped polysilicon film and the barrier metal film, manufacturing a MOS field effect transistor of a semiconductor device. Way. The method of claim 1, further comprising forming an etch stop layer before depositing the interlayer insulating layer. The method of claim 1, wherein the forming of the gate electrode comprises depositing a metal film to fill the trench, and then patterning the metal film in the interlayer insulating layer to remove the metal film. . The method of claim 1, wherein the forming of the gate electrode is performed by depositing a metal film to fill the trench, and then planarizing the metal film in the interlayer insulating layer to remove the metal film. . The method of manufacturing a MOS field effect transistor of a semiconductor device according to claim 1, wherein the metal film of the gate electrode has a T structure. The method of claim 1, further comprising, after forming the gate electrode, depositing an upper interlayer insulating film on an entire surface of the structure including the gate electrode, forming a contact hole in the interlayer insulating film, and filling the conductive film to form a contact. A method for producing a MOS field effect transistor of a semiconductor device.