JP2005311058A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To simply improve the driving capacity of these MISFETs (metal insulator semiconductor field effect transistor) by controlling lattice strain in the channel regions of n-channel and p-channel MISFETs. <P>SOLUTION: The n-channel MISFET of an active region 3, obtained by defining a silicon substrate 1 by an element separating region 2, is provided with a structure having a first side wall spacer 7 which gives a compressive stress to an Si gate electrode 6, and which is provided itself with a tensile stress; and a first silicide layer 9 which gives a compressive stress to an n-conductive type source drain diffusion layer 8, and which is provided itself with a tensile stress. The p-channel MISFET of an active region 4 is provided with a structure having a second side wall spacer 10 which gives a tensile stress to an Si gate electrode 6, and which is provided itself with a compressive stress; and a second silicide layer 12 which gives a tensile stress to a p-conductive type source drain diffusion layer 11, and which is provided itself with a compressive stress. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, a semiconductor device that improves the driving capability of n-channel and p-channel insulated gate field effect transistors (MISFETs) by applying lattice strain to the channel region, and the manufacture thereof. Regarding the method.

  In order to increase the speed of operation of a semiconductor device, miniaturization of the element structure of the MISFET is the most effective conventional means, and the dimensional standard is being energetically advanced from 65 nm to 45 nm. In particular, in semiconductor devices mounted on Si substrates, high speed is achieved by generating lattice distortion in the channel region of MISFET and reducing the effective mass of charges (electrons and holes) to improve their mobility. Various attempts have been made.

  In the so-called strained Si channel technique for generating lattice strain in the channel region of the MISFET, as a first method, two kinds of materials having different lattice constants or thermal expansion coefficients are stacked, so that a wide area of the Si layer can be obtained. A method of generating a lattice distortion and producing a semiconductor element in the distorted region, and a second method of generating a local strain in a channel region using a stress caused by a device structure of a semiconductor device or a manufacturing process. There is.

  For example, in a typical technique of the first method, a Si layer is epitaxially grown on a single crystal SiGe alloy layer, and a MISFET is manufactured on the Si layer (see, for example, Patent Document 1). In this case, elongation (tensile) strain is generated in the Si layer, and the electron mobility is improved, but the hole mobility is decreased. Therefore, in order to improve the drive capability of both n-channel and p-channel MISFETs (hereinafter also referred to as CMOS), the SiGe alloy layer in the region where the p-channel MISFET is formed is selectively removed, or the p-channel MISFET is removed. Studies such as laminating a material that selectively generates shrinkage (compression) strain on the Si layer in the region to be manufactured have been made.

  In the technique related to the second method, for example, stress applied to the channel region from an insulator filled in an element isolation region such as STI (Shallow Trench Isolation) is used to improve the on-current of the CMOS (for example, , See Patent Document 2). In order to clarify the difference between the second method and the present invention, a specific description will be added with reference to FIG. FIGS. 7A and 7B are cross-sectional views of an n-channel MISFET and a p-channel MISFET, respectively.

  As shown in FIG. 7A, the n-channel MISFET is formed in an active region in which a p-well layer 101a is formed on a silicon substrate 101 and separated by an STI type element isolation film 102. Here, the element isolation film 102 has a three-layer structure of a silicon oxide film 102a, a silicon nitride film 102b, and a silicon oxide film 102c. The silicon oxide films 102a and 102c give compressive stress to the silicon substrate. However, since the silicon nitride film 102b exerts a strong tensile stress on the silicon substrate, the silicon oxide films 102a and 102c are large in the channel direction and gate width direction of the MISFET as a whole. Tensile strain is generated, and the on-current of the n-channel MISFET is improved. Since the tensile strain amount varies depending on the film thickness of the silicon nitride film 102b, the structure of the element isolation film 102 and the film thickness of the silicon nitride film 102b are selected according to the strain amount to be introduced. In addition to the element isolation film 102 having a cross section horizontal to the paper surface shown in the drawing, a silicon nitride film may be inserted into an element isolation film (not shown) having a cross section perpendicular to the paper surface.

  On the other hand, as shown in FIG. 7B, the p-channel MISFET is formed in an active region in which an n-well layer 101b is formed on the same silicon substrate 101 and separated by an STI type element isolation film 102. The Here, the element isolation film 102 is filled only with a silicon oxide film. This silicon oxide film applies a compressive stress to the silicon substrate 101, generates a large compressive strain in the channel direction of the p-channel MISFET, and improves the on-current of the p-channel MISFET. Further, when the above-described silicon nitride film is inserted into an element isolation film (not shown) having a cross section perpendicular to the drawing sheet, tensile stress is generated in the gate width direction as in the case of the n-channel MISFET, and the p-channel MISFET The on-current is further improved.

In FIG. 7, the n and p channel MISFETs have a normal structure, and a gate electrode 104 made of polysilicon formed on each p (n) well layer 101 a (101 b) via a gate insulating film 103, The structure includes a side wall spacer 105, a source / drain diffusion layer 106, and a cobalt silicide layer 107 formed on the surfaces of the gate electrode 104 and the source / drain diffusion layer 106. Then, a contact hole is formed in a predetermined region of the interlayer insulating film 108 covering the whole, and a contact plug 109 is embedded in connection with the cobalt silicide layer 107 on the surface of the source / drain diffusion layer 106.
Japanese Patent Laid-Open No. 10-270685 JP 2003-179157 A

  However, the first method has a problem that it is difficult to control the reduction of crystal defects in the strained Si or SiGe alloy layer, and the leakage current of the diffusion layer of the semiconductor device becomes conspicuous with the miniaturization of the semiconductor element structure. doing. Further, the surface flatness of Si grown on the SiGe alloy layer is poor, and there is still a problem in improving it, and industrial practical use is still in a poor state. This method has a problem that the manufacturing cost including the production of the SiGe alloy is significantly higher than that of a conventional semiconductor device on a silicon substrate. In addition, as a first method, an SOI (Silicon on Insulator) structure and similar techniques are well known, but sufficient lattice distortion is not yet obtained, and the improvement in charge mobility is small.

  The second method uses a local stress generated in the device structure or manufacturing process of the semiconductor device as described above. The stress increases with the miniaturization of the semiconductor device structure. For this reason, if the stress can be controlled with high accuracy, the second method can be an effective means having high consistency with the current manufacturing process of a semiconductor device. In the conventional example shown in FIG. 7, an on-current increase of about 10% can be easily obtained.

  However, in the conventional example, in the formation of an element isolation film such as the STI type, different types of insulating films, for example, a silicon oxide film and a silicon nitride film, must be selectively formed in a predetermined recess region for STI. Therefore, there has been a problem that it is difficult to apply the mass production of the semiconductor device with the miniaturization of the STI structure and the element structure. Thus, the above conventional example is a stress control method that is incompatible with the miniaturization of semiconductor elements.

  The present invention has been made in view of the above-described circumstances, and is adapted to miniaturization of a semiconductor device structure, and controls the lattice distortion of the channel region by a method having a very high consistency with the manufacturing process. It is an object of the present invention to provide a simple technique that can improve the drive capability of channel and p-channel MISFETs.

  In order to solve the above-described problems, a first invention according to a semiconductor device includes a semiconductor device having an n-channel MISFET and a p-channel MISFET formed on a semiconductor substrate, wherein the sidewall of the gate electrode of the n-channel MISFET A first sidewall spacer having a tensile stress is formed, and a second sidewall spacer having a compressive stress is formed on the side wall of the gate electrode of the p-channel MISFET.

  In the above invention, it is preferable that the first sidewall spacer is a silicon nitride film and the second sidewall spacer is a silicon oxide film.

  According to a second aspect of the present invention, in the semiconductor device having an n-channel MISFET and a p-channel MISFET formed on a semiconductor substrate, a surface of the source / drain diffusion layer of the n-channel MISFET has a first silicide having a tensile stress. A layer is formed, and a second silicide layer having a compressive stress is formed on the surface of the source / drain diffusion layer of the p-channel MISFET.

  In the above invention, it is preferable that the first silicide layer is made of cobalt disilicide and the second silicide layer is made of nickel silicide.

  In the above invention, the gate length of the gate electrode is preferably 100 nm or less. Further, a silicon nitride film having a tensile stress is preferably formed on the semiconductor substrate so as to cover the n-channel MISFET and the p-channel MISFET.

  The invention according to the method for manufacturing a semiconductor device is a method for manufacturing a semiconductor device in which an n-channel MISFET and a p-channel MISFET are formed on a semiconductor substrate, wherein the polycrystalline silicon is formed on the semiconductor substrate via a gate insulating film. Forming a film; processing the polycrystalline silicon film to form a gate electrode structure; forming a first sidewall spacer having a tensile stress on a sidewall of the gate electrode structure of the n-channel MISFET; forming a second sidewall spacer having compressive stress on the sidewall of the gate electrode structure of the p-channel MISFET.

  The invention according to the method for manufacturing a semiconductor device is a method for manufacturing a semiconductor device in which an n-channel MISFET and a p-channel MISFET are formed on a semiconductor substrate, the source including one conductivity type impurity of the n-channel MISFET. A step of sequentially forming a drain diffusion layer and a source / drain diffusion layer containing a reverse conductivity type impurity of the p-channel MISFET, and after forming both the source / drain diffusion layers, the source / drain diffusion layer of the n-channel MISFET Forming a first silicide layer having a tensile stress on the surface, and then forming a second silicide layer having a compressive stress on the surface of the source / drain diffusion layer of the p-channel MISFET. Yes.

  In the above invention, the first silicide layer is formed by covering the p-channel MISFET with an insulating film and depositing the first refractory metal film on the entire surface including the surface of the source / drain diffusion layer of the n-channel MISFET. The surface of the source / drain diffusion layer of the n-channel MISFET is silicided with the first refractory metal film by performing a first heat treatment, and the second silicide layer includes the first silicide layer and the first silicide layer. A second refractory metal film is deposited on the entire surface including the surface of the source / drain diffusion layer of the p-channel MISFET, and then a second heat treatment at a temperature lower than the temperature of the first heat treatment is performed, whereby the p-channel MISFET. The surface of the source / drain diffusion layer is formed by silicidation with the second refractory metal film.

  According to the configuration of the present invention, the lattice distortion of the channel region is controlled by a method that is suitable for miniaturization of the element structure of the conventional semiconductor device and has a very high consistency with the manufacturing process of the conventional semiconductor device. In addition, the driving capability of the n-channel and p-channel MISFETs can be easily improved.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view of an n-channel MISFET and a p-channel MISFET according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line XX in FIG. FIG. 3 is a schematic perspective view of the MISFET for explaining the effects in the present embodiment. In FIG. 1, hatched lines are provided to facilitate understanding of the configuration of the present invention.

  An n-channel MISFET and a p-channel MISFET constituting the semiconductor device of the present invention will be described. As shown in FIGS. 1 and 2, a p-well layer 1a and an n-well layer 1b are formed on a silicon substrate 1, and active regions 3 and 4 defined by an STI type element isolation region 2 are provided on the surface thereof. An n-channel MISFET is formed in the active region 3 and a p-channel MISFET is formed in the active region 4.

  As shown in FIG. 2, the n-channel MISFET gives compressive stress to the Si gate electrode 6 made of polysilicon formed on the p-well layer 1a via the gate insulating film 5 and the Si gate electrode 6 itself. The first sidewall spacer 7 having tensile stress, the n-conducting type source / drain diffusion layer 8, the Si gate electrode 6 and the source / drain diffusion layer 8 are formed on the surface, and compressive stress is applied to the source / drain diffusion layer 8. The structure itself has a first silicide layer 9 having a tensile stress.

  Here, the first sidewall spacer 7 is a silicon nitride film deposited by a chemical vapor deposition (CVD) method using a silane-based source gas and an ammonia-based source gas. Thus, when deposited on a silicon substrate, a tensile stress is generated in the silicon nitride film. Note that a silicon nitride film deposited by plasma-excited CVD (PECVD) is a film that causes compressive stress on the silicon nitride film when it is deposited on a silicon substrate, so this film is not used.

  The first silicide layer 9 is a silicide layer in which tensile stress is generated in a silicide layer formed on a silicon substrate, such as cobalt silicide and titanium silicide.

  Next, as shown in FIG. 2, the p-channel MISFET applies tensile stress to the Si gate electrode 6 and Si gate electrode 6 made of polysilicon formed on the n-well layer 1 b via the gate insulating film 5. The first sidewall spacer 10 having compressive stress, the p conductivity type source / drain diffusion layer 11, the Si gate electrode 6 and the source / drain diffusion layer 11 are formed on the surface of the source / drain diffusion layer 11. It has a structure having the second silicide layer 12 which gives stress and itself has compressive stress.

  Here, the second sidewall spacer 10 is a silicon oxide film deposited by a CVD method using a silane-based source gas and an oxygen-based source gas. This silicon oxide film is a film in which compressive stress is generated in the silicon oxide film when deposited on the silicon substrate. There are various methods for depositing a silicon oxide film. Among these, a silicon oxide film formed by an HTO (High Temperature Oxidation) method is preferable. In this method, silane gas and nitrous oxide gas are usually used, and the film formation temperature is relatively high at about 700 ° C., and a large compressive stress is generated in the silicon oxide film. A silicon oxide film formed by another method is easily densified by a subsequent thermal process for manufacturing a semiconductor device, and eventually the compressive stress is generated in the film.

  The second silicide layer 12 is a silicide layer in which compressive stress is generated in a silicide layer formed on a silicon substrate, such as nickel silicide.

  As shown in FIGS. 1 and 2, a cap film 13 covering the n-channel MISFET and the p-channel MISFET having the above structure is formed. Here, the cap film 13 is preferably made of the same material as that of the first sidewall spacer 7, for example, a silicon nitride film in which a tensile stress is generated in the film formed as described above.

  Next, the function and effect produced by the MISFET structure of the above embodiment will be described with reference to FIG. In FIG. 3, the same reference numerals are assigned to the same parts as in FIGS.

  First, the case of the sidewall spacer described above will be described. When the element structure of the semiconductor device is miniaturized and the design dimension standard is, for example, 65 nm to 45 nm, the dimension of the Si gate electrode 6 in the channel direction is 65 nm to 45 nm and the height is 100 nm as can be seen from FIG. The aspect ratio of the pattern of the Si gate electrode 6 is as very large as 2-3. Then, as shown in FIG. 1, a first sidewall spacer 7 whose thickness is approximately the same as the thickness of the Si gate electrode 6 is formed on the periphery of the Si gate electrode 6 of the n-channel MISFET. Similarly, the second sidewall spacer 10 is formed on the periphery of the Si gate electrode 6 of the p-channel MISFET.

  In the above structure, the stress caused by the first sidewall spacer 7 and the second sidewall spacer 10 and the distortion caused thereby are as follows. That is, in the case of the n-channel MISFET, the first sidewall spacer 7 gives a large compressive stress to the Si gate electrode 6 as described above. Further, as shown in FIG. 3, a compressive stress is also applied in the vertical (z) direction to the surface of the p-well layer 1a of the silicon substrate, that is, the channel region of the n-channel MISFET. A compressive strain −εz is generated in the direction. This compressive strain -εz reduces the effective mass of electrons. Then, the mobility of electrons increases by several percent, and the driving capability of the n-channel MISFET is improved. In the case of the p-channel MISFET, the second sidewall spacer 10 applies a large tensile stress to the Si gate electrode 6 as described above, and further, as shown in FIG. 3, the surface of the n-well layer 1b of the silicon substrate, that is, p A tensile stress is applied in the z direction to the channel region of the channel MISFET, and accordingly, a tensile strain εz is generated in the z direction. This tensile strain εz reduces the effective mass of holes and increases the mobility of holes by several percent, resulting in an improvement in the driving capability of the p-channel MISFET.

  The strain εz in the channel region due to the stress from the sidewall spacer structure described above increases as the device structure becomes finer and the aspect ratio of the Si gate electrode 6 pattern increases to 2 to 3 as described above. The improvement in the driving capability of the MISFET of the embodiment becomes even more remarkable. When the aspect ratio increases in this way, as will be described later, the stress caused by the first and second silicide layers 9 and 12 on the surface of the Si gate electrode 6 can be almost ignored.

  In this way, in the semiconductor device including the fine n-channel and p-channel MISFETs having the sidewall spacer structure of the present embodiment, the drive capability is improved, and the semiconductor device Can be achieved by a simple method.

  Next, the above-described silicide layer will be described. As the element structure of the semiconductor device is miniaturized, as can be seen from FIG. 1, the relative area occupied by the source / drain diffusion layers 8 and 11 with respect to the dimension of the Si gate electrode 6 in the channel direction increases. At the same time, the area occupied by the first silicide layer 9 and the second silicide layer 12 formed on the surface is relatively increased.

  In the above structure, the stress caused by the first silicide layer 9 and the second silicide layer 11 and the distortion caused thereby are as follows. That is, in the case of the n-channel MISFET, the two first silicide layers 9 formed on the source side and the drain side sandwich the channel region and give a large compressive stress to the source / drain diffusion layer 8. As shown in FIG. 3, this compressive stress generates a tensile strain εx in the channel direction (x direction) with respect to the surface of the p-well layer 1a of the silicon substrate, that is, the channel region of the n-channel MISFET. This tensile strain εx reduces the effective mass of electrons. In this case, the electron mobility is increased by about 10%, and the driving capability of the n-channel MISFET is improved. On the other hand, in the case of a p-channel MISFET, the second silicide layer 12 similarly applies a tensile stress to the source / drain diffusion layer 11 with the channel region interposed therebetween. Then, as shown in FIG. 3, this tensile stress generates a compressive strain −εx in the channel direction (x direction) with respect to the surface of the n-well layer 1b of the silicon substrate, that is, the channel region of the p-channel MISFET. This compressive strain -εx reduces the effective mass of holes. Also in this case, the hole mobility is increased, and the driving capability of the p-channel MISFET is improved.

  As described above, in the semiconductor device including the fine n-channel and p-channel MISFET having the silicide layer structure according to the present embodiment, the drive capability thereof is improved. High speed or high performance can be achieved by a simple method.

  Next, the manufacturing method of the semiconductor device of this invention is demonstrated with reference to FIGS. 4 to 6 are cross-sectional element sectional views of n-channel and p-channel MISFETs showing a method of manufacturing a semiconductor device. 1 and 2 are denoted by the same reference numerals.

  For example, the STI type element isolation region 2 is formed on the surface of the p-conductivity type silicon substrate 1 by a known method. Then, well-known ion implantation and heat treatment are performed to form a p-well layer 1a that becomes a region for forming an n-channel MISFET and an n-well layer 1b that becomes a region for forming a p-channel MISFET. The gate insulating film 5 is formed of an oxynitride film or hafnium silicate film having a thickness of about 2 nm, and the width dimension is about 65 nm by forming a polysilicon film and performing fine processing using a photolithography technique and a dry etching technique. A Si gate electrode 6 having a height of about 150 nm is formed (FIG. 4A).

  Next, an n-conductivity type impurity such as arsenic is introduced into the surface of the p-well layer 1a and the Si gate electrode 6 by ion implantation, thereby forming an extreme layer 8a on the surface of the p-well layer 1a. Similarly, p-conductivity type impurities such as boron are introduced into the surface of the n-well layer 1b and the Si gate electrode 6 by another ion implantation and heat treatment, thereby forming an extreme layer 11a on the surface of the n-well layer 1b (FIG. 4). (B)).

  Next, a silicon oxide film having a thickness of about 80 nm is deposited on the entire surface by the HTO method and etched back by anisotropic dry etching to form a second sidewall spacer 10 on the sidewall of the Si gate electrode 6. Here, the thickness of the second sidewall spacer 10 is 60 nm to 70 nm (FIG. 4C).

  Subsequently, the second side wall spacer 10 on the side wall of the Si gate electrode 6 of the n-channel MISFET is selectively removed with a hydrofluoric acid chemical solution using a resist mask formed by a known photolithography technique as an etching mask. . In this way, the second sidewall spacer 10 is formed only on the sidewall of the Si gate electrode 6 of the p-channel MISFET (FIG. 5A).

  Next, a silicon nitride film having a film thickness of about 70 nm is deposited on the entire surface by the known thermal CVD method or catalytic CVD method as described above, and then etched back by anisotropic dry etching, so that Si of n channel MISFET is formed. A first sidewall spacer 7 is formed on the side wall of the gate electrode 6. Here, the thickness of the first sidewall spacer 7 is about 60 nm (FIG. 5B). In this case, the etch back removes all the silicon nitride film deposited on the surface of the second sidewall spacer 10 of the p-channel MISFET.

  After doing so, well-known ion implantation and heat treatment are performed, and the source / drain diffusion layers 8 and 11 that are self-aligned with the Si gate electrode 6, the first sidewall spacer 7, and the second sidewall spacer 10. Is formed (FIG. 5C). In the ion implantation, impurities of n conductivity type or p conductivity type are introduced into the Si gate electrode 6 together with the surface of the p well layer 1a and the surface of the n well layer 1b. Here, in the heat treatment, rapid thermal annealing (RTA) is performed at 1000 ° C. for about 10 seconds by so-called rapid heat treatment. By this heat treatment, the impurities introduced by ion implantation are activated and the first sidewall spacer 7 and the second sidewall spacer 10 are densified.

  Next, an oxide film mask 14 for protecting the p-channel MISFET region is formed by depositing the entire surface of a silicon oxide film having a thickness of about 10 nm and wet etching using a known resist mask as an etching mask. This oxide film mask 14 completely covers the Si gate electrode 6, the source / drain diffusion layer 11, and the second sidewall spacer 10 (FIG. 6A).

After this, a first silicide layer 9 is formed of cobalt silicide on the surface of the Si gate electrode 6 and the source / drain diffusion layer 8 of the n-channel MISFET by a so-called salicide technique. In this salicide technique, cobalt having a film thickness of about 10 nm is first formed on the entire surface by sputtering, and RTA is performed at 500 ° C. for about 30 seconds. Then, after removing unreacted cobalt with a hydrochloric acid chemical solution, heat treatment is again performed by RTA at 800 ° C. for about 30 seconds to form low-resistance cobalt disilicide (CoSi ₂ ) (FIG. 6B). ).

  Next, the oxide film mask 14 covering the p-channel MISFET is removed by dry etching or the like. Next, the second silicide layer 12 of nickel silicide is selectively formed in the p channel MISFET region. In the salicide technique in this case, first, a nickel film having a film thickness of about 15 nm is formed on the entire surface by sputtering, and RTA is performed at 450 ° C. for about 30 seconds. Then, unreacted nickel is removed with a hydrochloric acid chemical solution. In this way, the second silicide layer 12 made of nickel silicide is formed on the surface of the Si gate electrode 6 and the surface of the source / drain diffusion layer 11 of the p-channel MISFET (FIG. 6C). In the formation of nickel silicide, since the heat treatment is 500 ° C. or less, the nickel does not thermally react with the first silicide layer 9 such as cobalt silicide, and a nickel silicide layer is formed on the surface of the first silicide layer 9. It will never be done.

  Then, a silicon nitride film having a film thickness of about 100 nm is deposited on the entire surface by a known thermal CVD method or catalytic CVD method to form a cap film 13, and the element structure shown in the element cross-sectional view shown in FIG. 2 is obtained. Thereafter, although not shown, an interlayer insulating film is formed on the entire surface as described in the prior art to form a wiring structure of a semiconductor device. Here, the thermal process temperatures of the subsequent semiconductor device manufacturing, such as the formation of the interlayer insulating film and the formation of the wiring structure, are all 450 ° C. or lower.

  By the semiconductor device manufacturing method, the n-channel MISFET Si gate electrode 6 and the first sidewall spacer 7 that exerts a strong compressive stress locally in the z direction of the channel region are simply formed. Further, the second side wall spacer 10 that exerts a strong local tensile stress on the Si gate electrode 6 of the p channel MISFET and the z direction of the channel region is simply formed. As described above, in the miniaturization of the element structure of the semiconductor device, the above-described n-channel MISFET and p-channel are used by a manufacturing method that uses a conventional semiconductor device manufacturing process as it is and has high consistency with the conventional technology. It becomes possible to easily improve the driving capability of the MISFET. In the above embodiment, the Si gate electrode 6 has a width dimension of about 65 nm and a height of about 150 nm. However, the improvement of the driving capability of the MISFET by using the stress from the side wall spacers It has been confirmed that this occurs when the width dimension (gate length) is 100 nm or less. Even in the case of a gate electrode formed of a material different from polysilicon other than the Si gate electrode, the same effect can be obtained by generating the stress as described above.

  In addition, the first silicide layer 9 that exerts a strong tensile stress locally on the x direction of the channel region of the n-channel MISFET is formed on the surface of the source / drain diffusion layer 8 by the method for manufacturing the semiconductor device. A second silicide layer 12 that exerts a strong compressive stress locally in the x direction of the channel region is simply formed on the surface of the source / drain diffusion layer 11. Thus, in this case as well, the conventional semiconductor device manufacturing process is used as it is, and the above-described driving capability of the n-channel MISFET and the p-channel MISFET is achieved by a manufacturing method having high consistency with the conventional technology. Can be easily improved.

For the first silicide layer 9, titanium disilicide (TiSi ₂ ) having a phase structure with low resistance, or various types of refractory metal silicides such as molybdenum silicide and tungsten silicide can be used. The second silicide layer 12 is preferably a nickel silicide layer. However, since the absolute value of the stress exerted by the nickel silicide layer is smaller than that of the first silicide layer 9, it is necessary to make it thicker than the first silicide layer. However, if the silicide layer is too thick, the junction characteristics of the source / drain diffusion layer 11 of the p-channel MISFET deteriorate, so that an appropriate film thickness exists. The same applies to the first silicide layer 9, and an appropriate film thickness exists. In the salicide technique described above, a silicide layer is also formed on the surface of the Si gate electrode 6. The thickness of the silicide layer is 1/5 or less of the Si gate electrode 6 as described above, and its influence is negligible when stress is applied by the sidewall spacer 7 or 10 described above.

  As mentioned above, although embodiment of this invention was described, embodiment mentioned above does not limit this invention. Those skilled in the art can make various modifications and changes without departing from the technical idea and the technical scope of the present invention.

  For example, a silicon oxide film having high porosity may be used for the first sidewall spacer 7 described above. In any case, any material film (whether an insulator, a semiconductor, or a conductor) that causes compressive stress in the gate electrode, or a laminated film thereof may be used. Similarly, a silicon nitride film formed by PECVD may be used for the second sidewall spacer 10, and in this case as well, a material film that generates tensile stress on the gate electrode (regardless of an insulator, a semiconductor, or a conductor) Alternatively, any laminated film of these may be used.

  Further, in the semiconductor device, between the n-channel MISFET and the p-channel MISFET, only the sidewall spacer is formed of the above-described different materials, and the silicide on the source / drain diffusion layers 8 and 11 is formed. The layers may be composed of the same material. Conversely, between the n-channel MISFET and the p-channel MISFET, only the silicide layer of the source / drain diffusion layer may be formed of a different material as described above, and the sidewall spacers may be formed of the same material.

  Furthermore, the present invention can be similarly applied not only when a semiconductor device is formed on a silicon substrate but also when a semiconductor device is formed on a compound semiconductor substrate such as a GaAs substrate or a GaN substrate.

It is a top view which shows the MISFET structure concerning embodiment of this invention. It is sectional drawing which shows the same MISFET structure. It is a perspective view of MISFET for demonstrating the effect of this invention. It is element sectional drawing according to process which shows the manufacturing method of the semiconductor device concerning embodiment of this invention. FIG. 5 is an element sectional view by process following the process illustrated in FIG. 4. FIG. 6 is an element sectional view by process following the process illustrated in FIG. 5. It is element sectional drawing which shows the stress provision resulting from the device structure of the semiconductor device concerning a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 1a p well layer 1b n well layer 2 element isolation region 3, 4 active region 5 gate insulating film 6 Si gate electrode 7 first sidewall spacer 8, 11 source / drain diffusion layer 8a, 11a extension layer 9 first Silicide layer 10 Second sidewall spacer 12 Second silicide layer 13 Cap film 14 Oxide mask

Claims (10)

  In a semiconductor device having an n-channel MISFET and a p-channel MISFET formed on a semiconductor substrate, a first sidewall spacer having a tensile stress is formed on a sidewall of a gate electrode of the n-channel MISFET, and the p-channel MISFET A semiconductor device, wherein a second sidewall spacer having a compressive stress is formed on a sidewall of the gate electrode.   2. The semiconductor device according to claim 1, wherein the first sidewall spacer is a silicon nitride film, and the second sidewall spacer is a silicon oxide film.   In a semiconductor device having an n-channel MISFET and a p-channel MISFET formed on a semiconductor substrate, a first silicide layer having a tensile stress is formed on the surface of the source / drain diffusion layer of the n-channel MISFET, and the p-channel A semiconductor device, wherein a second silicide layer having a compressive stress is formed on a surface of a source / drain diffusion layer of a MISFET.   In a semiconductor device having an n-channel MISFET and a p-channel MISFET formed on a semiconductor substrate, a first silicide layer having a tensile stress is formed on the surface of the source / drain diffusion layer of the n-channel MISFET, and the p-channel 3. The semiconductor device according to claim 1, wherein a second silicide layer having a compressive stress is formed on a surface of the source / drain diffusion layer of the MISFET.   5. The semiconductor device according to claim 3, wherein the first silicide layer is formed of cobalt disilicide, and the second silicide layer is formed of nickel silicide.   The semiconductor device according to claim 1, wherein a gate length of the gate electrode is 100 nm or less.   7. The silicon nitride film having a tensile stress is formed on the semiconductor substrate so as to cover the n-channel MISFET and the p-channel MISFET. 8. Semiconductor device. A method of manufacturing a semiconductor device in which an n-channel MISFET and a p-channel MISFET are formed on a semiconductor substrate,
Forming a polycrystalline silicon film on the semiconductor substrate via a gate insulating film;
Processing the polycrystalline silicon film to form a gate electrode structure;
A first sidewall spacer having a tensile stress is formed on the sidewall of the gate electrode structure of the n-channel MISFET, and a second sidewall spacer having a compressive stress is formed on the sidewall of the gate electrode structure of the p-channel MISFET. And the process of
A method for manufacturing a semiconductor device comprising: A method of manufacturing a semiconductor device in which an n-channel MISFET and a p-channel MISFET are formed on a semiconductor substrate,
Sequentially forming a source / drain diffusion layer containing one conductivity type impurity of the n-channel MISFET and a source / drain diffusion layer containing a reverse conductivity type impurity of the p-channel MISFET;
After forming both the source / drain diffusion layers, a first silicide layer having a tensile stress is formed on the surface of the source / drain diffusion layer of the n-channel MISFET, and then on the surface of the source / drain diffusion layer of the p-channel MISFET. Forming a second silicide layer having compressive stress;
A method for manufacturing a semiconductor device comprising: The first silicide layer is formed by covering the p-channel MISFET with an insulating film and depositing a first refractory metal film on the entire surface including the surface of the source / drain diffusion layer of the n-channel MISFET. The surface of the source / drain diffusion layer of the n-channel MISFET is silicided with the first refractory metal film by performing heat treatment, and the second silicide layer includes the first silicide layer and the p-channel MISFET. The second refractory metal film is deposited on the entire surface including the surface of the source / drain diffusion layer, and then a second heat treatment at a temperature lower than the temperature of the first heat treatment is performed, whereby the source / drain diffusion layer of the p-channel MISFET 10. The method of manufacturing a semiconductor device according to claim 9, wherein the surface is formed by silicidation with the second refractory metal film.

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