KR20080106797A - Method for fabricating a semiconductor device - Google Patents

Abstract

A manufacturing method of the semiconductor device is provided to reduce the equivalent thickness of capacitance of the gate insulating layer by maximizing the dosage of the conductive film. A manufacturing method of the semiconductor device comprises the following steps: the step for providing the silicon layer; the step for plasma-doping the silicon layer using the mixed gas of BF3 and B2H6; the step for providing the semiconductor substrate(100) consisting of the single-crystal silicon. The plasma-doping to the silicon layer is to form the reaction layer which is formed by the reaction of the mixed gas consisting of BF3 and B2H6, and the silicon.

Description

Method for fabricating a semiconductor device

1 to 10 are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

11 is a cross-sectional view of a method of manufacturing a semiconductor device in accordance with another embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

100 semiconductor substrate 110 gate insulating film

120: conductive film 130: first photosensitive film

140: first reaction layer 150: metal film

160: hard mask patterns 170 and 171: first and second gates

180: spacer 190: second photosensitive film

210: second reaction layer

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device using plasma doping.

In order to control the electrical characteristics of the semiconductor device, a process of adding an impurity to the semiconductor, that is, a doping process, is performed.

Plasma implantation techniques such as plasma immersion ion implanters (PIII) have been used as one of the doping processes. This implantation technique is cheap and has high throughput at low energy.

However, the plasma injection method does not have a material selection function, which may involve unintended etching and precipitation phenomena during the doping process. For example, when using BF ₃ as the dopant gas, plasma elements associated with fluorine (F) may cause unintended etching. These phenomena cause dopant loss and consequently deteriorate the characteristics of the semiconductor device.

The technical problem to be achieved by the present invention is to provide a method for manufacturing a semiconductor device that improves the etching and precipitation phenomenon during plasma doping.

The technical problems of the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

A semiconductor device according to an embodiment of the present invention for achieving the above technical problem includes providing a silicon layer, and plasma doping using a mixed gas of BF ₃ and B ₂ H ₆ in the silicon layer.

Other specific details of the invention are included in the detailed description and drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the art to which the present invention pertains. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

A method of manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 1 to 10. 1 to 10 are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1, an insulating film 110 and a conductive film 120 are formed on a semiconductor substrate 100.

First, the semiconductor substrate 100 may include an NMOS region and a PMOS region. As described below, the NMOS region and the PMOS region may be classified according to the type of gate and source / drain regions formed on the semiconductor substrate 100.

The NMOS region and the PMOS region of the semiconductor substrate 100 are separated into an active region and an inactive region by a device isolation film such as shallow trench isolation (STI) or field oxide (FOX). Subsequently, the insulating film 110 and the conductive film 120 are successively formed on the semiconductor substrate 100.

As the semiconductor substrate 100, a substrate made of one or more semiconductor materials selected from the group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, and InP, a silicon on insulator (SOI) substrate, or the like may be used. This is merely illustrative.

The insulating film 110 deposited on the semiconductor substrate 100 is a film for forming a gate insulating film, a silicon oxide film formed by thermal oxidation of the semiconductor substrate 100, SiON, GexOyNz, GexSiyOz, high dielectric constant materials, and the like. Combinations or laminated films in which these are stacked may be used. At this time, it may be formed by Chemical Vapor Deposition (CVD), but is not limited thereto. Here, for example, HfO ₂ , ZrO ₂ , Al ₂ O ₃ , Ta ₂ O ₅ , hafnium silicate, zirconium silicate, or a combination thereof may be used as the high dielectric constant material. The thickness of the insulating film 110 may be about 10 to 60Å, the type or thickness of the insulating film 110 can be adjusted within the object range of the present invention.

The conductive layer 120 stacked on the insulating layer 110 may be a polysilicon layer. In addition, a metal film such as W and TiN may be included below the conductive film 120, and other material films may be included as necessary.

Subsequently, as shown in FIG. 2, the first photoresist layer 130 is formed on the conductive layer 120. The first photoresist layer 130 is formed on the NMOS region to expose the conductive layer 120 of the PMOS region. Thereafter, the conductive layer 120 is doped with impurities. The impurity is a P-type impurity, and may be, for example, boron (B). In the doping, a plasma doping method is used, but the gas used in the plasma doping is a mixed gas of BF ₃ and B ₂ H ₆ . In the plasma atmosphere of the mixed gas, BF ₃ and B ₂ H ₆ may be in a ratio of about 50: 1, but are not limited thereto.

At this time, the conductive film 120 of the NMOS region where the first photoresist layer 130 is formed is not doped, and boron B is formed on the conductive layer 120 of the PMOS region where the first photoresist layer 130 is not formed. Doped.

Subsequently, as shown in FIG. 3, as a result of plasma doping to the conductive film 120, the mixed gas and silicon (Si), which is a constituent material of the conductive film 120, react with each other to form the conductive film 120 in the PMOS region. The reaction layer 130 may be formed on the upper side. The reaction layer 130 may include B, Si, and H. The reaction layer 130 may improve a problem caused by etching and precipitation of the conductive layer 120 which may appear during plasma doping using only one gas.

For example, since the plasma doping process has no material selection function, when only BF ₃ gas is used to dope B ions, the plasma formed may include not only B ions, but also F ions and other radicals. Unexpected etching of the conductive film 120 may occur due to the formed F ions and other radicals. When the etching phenomenon of the conductive film 120 occurs, since the thickness of the conductive film 120 becomes thin, the B ions are more deeply doped into the conductive film 120. In addition, when only B2H6 gas is used, the depth of the B ions doped into the conductive film 120 is relatively shallow because the reaction layer is thickly deposited on the upper portion of the conductive film 120 to prevent the implantation of B ions. Lose.

However, when the plasma doping using the method of manufacturing a semiconductor device according to the present invention, that is, a mixed gas of BF ₃ and B ₂ H ₆ It can be doped with a suitable concentration of B ions to the depth to be doped. This is understood to be due to the first reaction layer 140 formed on the conductive film 120 during plasma doping to compensate for the upper portion of the conductive film 120 etched by F ions and other radicals.

Here, the reaction layer 130 is formed to a thickness that does not interfere with the doping during the doping, and minimizes the dopant loss during the cleaning process for removing the subsequent photoresist, while not causing an increase in the interface resistance of the conductive film 120. desirable. For example, the thickness of the reaction layer 130 may be formed to 1000 Å or less, but is not limited thereto. The thickness of the reaction layer 130 may be adjusted by pressure, flow rate, and source power during plasma doping.

Subsequently, as shown in FIG. 4, the reaction layer and the photosensitive film formed during plasma doping are removed.

In a subsequent process, the first reaction layer 140 may be removed to lower the interface resistance between the metal film 150 and the conductive film 120 to be deposited on the conductive film 120, and the first reaction layer 140. ) And the first photoresist layer 130 may be removed together.

In detail, the first reaction layer 140 may be removed together during the cleaning process for removing the first photoresist layer 130. In this case, the first reaction layer 140 is positioned above the conductive film 120 to prevent the conductive film 120 from being directly exposed at the beginning of the cleaning process, thereby etching a part of the conductive film 120. Can be partially suppressed. Therefore, the first reaction layer 140 may improve dopant loss that may occur when the conductive layer 120 is etched. In this case, since the thickness of the first reaction layer 140 may affect the degree of improvement of the dopant loss, the formation of the first reaction layer 140 may minimize the dopant loss of the first reaction layer 140. It is desirable to consider the thickness.

Here, for the convenience of the process, the process of removing the first reaction layer 140 and the first photosensitive film 130 together has been described, but is not limited thereto. The first reaction layer 140 is first removed, and the first photosensitive film ( 130 may be eliminated or vice versa.

Subsequently, although not shown in the drawing, a photosensitive film exposing the conductive film 120 in the NMOS region is formed on the conductive film 120 in the PMOS region. Thereafter, the conductive layer 120 is doped with impurities. The impurity is an N-type impurity, and may be, for example, phosphorus (P) and arsenic (As). Thereafter, the photosensitive film is removed.

Subsequently, as shown in FIG. 5, the metal film 150 is formed on the conductive film 120.

The metal film 150 may be selectively formed and made of W, TiN, or the like. The metal film 150 may be formed by chemical vapor deposition (CVD). Here, interfacial resistance may occur between the conductive film 120 and the metal film 150. The interface resistance may be minimized since a problem of signal delay may occur during operation of the semiconductor device.

However, as described above, the thicker the thickness of the first reaction layer 140 formed during the plasma doping step in the conductive film 120 is, the more likely it will remain during removal. A portion of the remaining first reaction layer 140 may cause an increase in the interface resistance between the conductive film 120 and the metal film 150. Therefore, the degree of causing an increase in the interface resistance when the first reaction layer 130 is formed may also be a consideration for the thickness of the first reaction layer 130.

Subsequently, as illustrated in FIG. 6, a hard mask pattern 160 may be further formed on the metal layer 150 of the NMOS region and the PMOS region to pattern the gate, respectively. Here, the hard mask film formed on the metal film 150 to form the hard mask pattern 160 may be formed of, for example, a nitride film.

Next, as shown in FIG. 7, the conductive layer 120, the metal layer 150, and the insulating layer 110 are patterned by patterning the hard mask pattern 160 as an etch mask to form the first gate ( 170 and the second gate 171 of the PMOS region may be formed. The first and second gates 170 and 171 are stacked with conductive film patterns 120a and 120b, metal film patterns 130a and 130b, and gate insulating films 110a and 110b, respectively. The patterning process may be performed by sequentially removing the metal film 150, the conductive film 120, and the insulating film 110 by a conventional dry etching process or a wet etching process.

Subsequently, a spacer insulating layer may be conformally formed on the semiconductor substrate 100 and on the hard mask pattern 160. The spacer insulating film may be formed of, for example, a nitride film. The spacer insulating layer is anisotropically etched to form the spacer 180, and the etching is performed until the top surface of the hard mask pattern 160 is exposed.

Subsequently, as shown in FIG. 8, the second photoresist layer 190 is formed in the NMOS region, and the semiconductor substrate 100 of the PMOS region is formed using the hard mask pattern 160 and the spacer 180 of the PMOS region as doping masks. P-type impurities, such as boron (B), are doped onto the phase. Therefore, it can be doped using the gas containing boron (B). As a result, as shown in FIG. 9, the second source / drain regions 200 may be formed on both sides of the second gate electrode 171. Thereafter, the second photoresist layer 190 is removed.

Next, similarly to the second source / drain region 200 formed on the semiconductor substrate of the PMOS region, a gas containing N-type impurities such as phosphorus (P) and arsenic (As) is used for the semiconductor substrate of the NMOS region. The semiconductor device illustrated in FIG. 10 may be formed by performing the step of forming the first source / drain region 201 by doping.

Subsequently, the semiconductor device may be completed by further forming wirings to enable input and output of electrical signals to each transistor, forming a passivation layer on the substrate, and packaging the substrate. .

A semiconductor device including a conductive film 120 formed by a method of manufacturing a semiconductor device according to the present invention, that is, a plasma doping method using a mixed gas of BF ₃ and B ₂ H ₆ , may improve dopant loss to provide a conductive film 120. By maximizing the doping amount, a semiconductor device having a thin capacitance equivalent thickness (CET) of the gate insulating layer may be realized. Specifically, the depletion layer may be formed in the gate of the semiconductor device, but may be formed in a portion adjacent to the gate insulating layer. The width of the depletion layer may vary depending on the doping concentration of the gate of the semiconductor device, and as a result, the capacitive equivalent thickness of the gate insulating layer is affected. For example, when the doping concentration of the gate is low, the width of the depletion layer can be expanded. Accordingly, the capacitive equivalent thickness of the gate insulating film that affects the operation of the semiconductor device may increase. However, by maximizing the doping concentration of the gate, the expansion width of the depletion layer can be reduced in inverse proportion to the doping concentration. Accordingly, a semiconductor device having a thin capacitive equivalent thickness of the gate insulating film may be implemented. A semiconductor device having a thin capacitive equivalent thickness of the gate insulating film may be advantageous for high integration.

In addition, according to the manufacturing method according to the present invention, semiconductor devices manufactured from one wafer may be manufactured to have a capacitive equivalent thickness of a predetermined gate insulating film. This means that by manufacturing a semiconductor device conforming to the manufacturing standard, the reliability of the semiconductor device can be improved.

Hereinafter, a method of manufacturing a semiconductor device according to another embodiment of the present invention will be described.

Since the steps of forming the first and second gates in the NMOS region and the PMOS region, respectively, are substantially the same as those described with reference to FIGS. 1 to 7, the description thereof is omitted.

However, in FIG. 2, a gas including boron B may be used as a gas used for plasma doping of boron B in addition to a mixed gas of BF ₃ and B ₂ H ₆ .

Referring to FIG. 8, the second photosensitive layer 190 is formed in the NMOS region, and the boron is formed on the semiconductor substrate 100 of the PMOS region using the hard mask pattern 160 and the spacer 180 of the PMOS region as doping masks. Doping (B), but may be doped using a mixture of BF ₃ and B ₂ H ₆ gas.

As a result, referring to FIG. 11, a second source / drain region 200 doped with boron B is formed on a part of the semiconductor substrate 100 of the PMOS region, that is, on both sides of the second gate 170. In this case, the second reaction layer 210 may be formed on the second source / drain region 200.

The second reaction layer 210 may be a result formed by reacting silicon (Si), which is a constituent material of the semiconductor substrate 100, with a mixed gas of BF ₃ and B ₂ H ₆ . The second reaction layer 210 may serve to compensate for the etched portion when the phenomenon in which the semiconductor substrate 100 is etched by F ions and other radicals formed during plasma doping occurs. Accordingly, a second source / drain region 200 having a suitable depth and dose amount may be formed during plasma doping. Here, the result of the semiconductor device including the second reaction layer 210 is distinguished from the result of FIG. 9. The second reaction layer 210 may be removed together with the second photosensitive film 190 formed in FIG. 8, and subsequent steps are the same as those described with reference to FIG. 10.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

As described above, B ions may be doped into the gate and source / drain regions using a method of manufacturing a semiconductor device, that is, a mixed gas of BF ₃ and B ₂ H ₆ . By compensating for etching of a part of the doped portion due to the reaction layer formed during plasma doping, B ions can be doped to a suitable concentration at the depth to be doped, thereby maximizing the amount of doping of the conductive film, thereby increasing the capacitance of the gate insulating film. It is possible to implement a semiconductor device having a thin equivalent thickness.

Claims (7)

Providing a silicon layer, Method of manufacturing a semiconductor device comprising plasma doping the mixed layer of BF ₃ and B ₂ H ₆ to the silicon layer. The method of claim 1, Providing the silicon layer provides a semiconductor substrate made of single crystal silicon, and plasma doping the silicon layer is plasma doping to at least a portion of the semiconductor substrate. The method of claim 1, The silicon layer is a method of manufacturing a semiconductor device is a polysilicon layer formed on a substrate. The method of claim 1, Plasma doping the silicon layer includes forming a reaction layer formed by reaction of the mixed gas and silicon on the silicon layer. The method of claim 4, wherein Forming a photoresist film partially covering the silicon layer, Plasma doping the silicon layer comprises doping a portion of the silicon layer exposed by the photosensitive film. The method of claim 5, And removing the photosensitive film and the reaction layer together after the plasma doping. The method of claim 4, wherein The thickness of the said reaction layer is a manufacturing method of the semiconductor element which is 1000 GPa or less.

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