KR20080103277A - Semiconductor device and method for fabricating the same - Google Patents

Abstract

A semiconductor device and a manufacturing method thereof are provided to improve the gate depletion phenomenon by setting up the first and the second conductive layer pattern at the bottom part of the gate located on the first and second area. A semiconductor device comprises the semiconductor substrate(100) including the first area and the second area; the gate insulating layer formed on the first and second area of the semiconductor substrate; the first gate(140) including the first poly silicon film pattern(120) formed on the first conductive layer pattern and the first conductive layer pattern; the second conductive layer pattern(110b) thicker than the first conductive layer pattern(110a); the second gate(150) including the second polysilicon layer pattern formed on the second conductive layer pattern and the second conductive layer pattern. The second conductive layer pattern is formed on the gate insulating layer of the second part.

Description

Semiconductor device and method for manufacturing the same {Semiconductor device and method for fabricating the same}

1 is a cross-sectional view of a semiconductor device in accordance with an embodiment of the present invention.

2A to 2G are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

100 semiconductor substrate 103 gate insulating film

111: lower conductive film pattern 115: upper conductive film pattern

117: photoresist pattern 110a: first conductive film pattern

110b: second conductive film pattern 120: first polysilicon film pattern

122: second polysilicon film pattern 130: mask pattern

140: first gate 150: second gate

160: spacer

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device including a dual gate and a method for manufacturing the same.

In recent years, according to trends such as high performance and high speed of semiconductor devices, attempts have been made to optimize the performance of transistors for each type even in the case of semiconductor devices including NMOS transistors and PMOS transistors simultaneously.

In this attempt, technological advances have been made such as changing the structure of the gates of NMOS transistors and PMOS transistors, or using a high-k dielectric layer having a higher dielectric constant than the silicon oxide film.

For example, in a gate using a polysilicon film, a gate having a metal-inserted polysilicon (MIPS) structure is applied to improve the gate depletion phenomenon. However, in the case of a gate to which such a MIPS structure is applied, there is a difficulty in applying a different metal having an appropriate work function to an NMOS transistor and a PMOS transistor.

In the gate using the polysilicon film, when the high dielectric material film is formed as the gate insulating film, the threshold voltage may increase due to the reaction between the gate and the gate insulating film, and the impurities doped in the gate may be reduced as the thickness of the gate insulating film decreases. For example, the boron may penetrate the gate insulating layer and diffuse into the channel region, thereby deteriorating characteristics of the semiconductor device.

The technical problem to be achieved by the present invention is to provide a semiconductor device that improves the gate depletion phenomenon.

Another object of the present invention is to provide a method of manufacturing such a semiconductor device.

The technical problems of the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a semiconductor device including a semiconductor substrate including a first region and a second region, a gate insulating layer formed in the first and second regions on the semiconductor substrate, A first gate formed on the gate insulating film in a first region, the first gate including a first conductive film pattern and a first polysilicon film pattern formed on the first conductive film pattern, and on the gate insulating film in the second region And a second gate including a second conductive film pattern thicker than the first conductive film pattern and a second polysilicon film pattern formed on the second conductive film pattern.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a gate insulating film is formed in the first and second regions on a semiconductor substrate including a first region and a second region, and the gate A lower conductive film and an upper conductive film are sequentially formed on the insulating film, the upper conductive film of the first region is selectively removed, the lower conductive film of the first region is exposed, and a polysilicon film is formed on the entire surface of the resultant. By performing a patterning process, a first gate including a first conductive layer pattern in the first region and a first polysilicon layer pattern formed on the first conductive layer pattern, and the first conductive layer in the second region Forming a second gate including a second conductive film pattern thicker than the pattern and a second polysilicon film pattern formed on the second conductive film pattern. All.

Other specific details of the invention are included in the detailed description and drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the art to which the present invention pertains. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

Hereinafter, with reference to the accompanying drawings will be described embodiments of the present invention;

A semiconductor device according to an embodiment of the present invention will be described with reference to FIG. 1. 1 is a cross-sectional view of a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 1, a semiconductor device according to an exemplary embodiment includes a semiconductor substrate 100, a gate insulating layer 103, and first and second gates 140 and 150.

The semiconductor substrate 100 includes a first region and a second region. The first and second regions may be divided according to the type of gate formed on the semiconductor substrate 100 as described below. That is, as illustrated in FIG. 1, the semiconductor substrate 100 may be divided into a first region in which the first gate 140 is formed and a second region in which the second gate 150 is formed. Here, the first region may be an NMOS region and the second region may be a PMOS region.

As the semiconductor substrate 100, a substrate made of one or more semiconductor materials selected from the group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, and InP, a silicon on insulator (SOI) substrate, or the like may be used. This is merely illustrative.

Gate insulating layers 103 are formed in the first and second regions on the semiconductor substrate 100. The gate insulating film 103 may be, for example, a silicon oxide film, a high dielectric constant film, or the like. The high dielectric constant film refers to a film made of a material having a higher dielectric constant than a silicon oxide film. For example, the high dielectric film may be a film made of a material having a dielectric constant of 10 or more. As the high dielectric constant film, for example, an oxide film, an aluminate film, or a silicate film containing at least one metal such as Hf, Zr, Al, Ti, La, Y, Gd, Ta, or the like may be applied.

In addition, the thickness of the gate insulating film 103 may be about 10 to 60Å, the kind or thickness of the gate insulating film 103 can be adjusted within the object range of the present invention.

The first gate 140 and the second gate 150 are formed on the gate insulating layer 103 of the first region and the second region, respectively.

The first gate 140 is formed on the gate insulating layer 103 in the first region. In the first gate 140, a first conductive layer pattern 110a and a first polysilicon layer pattern 120 are stacked.

Here, the first conductive layer pattern 110a may be formed of a metal material formed of, for example, TaN, WN, TiN, Ta, W, Ti, Ru, HfN, HfSiN, TiSiN, TaSiN, HfAlN, or a combination thereof. Can be. The thickness of the first conductive layer pattern 110a may be about 1 to about 30 mm, but is not limited thereto.

The first polysilicon layer pattern 120 is positioned on the first conductive layer pattern 110a. The first polysilicon layer pattern 120 may have a suitable work function of about 4.0 to about 4.5 eV of the first gate 140. The first polysilicon layer pattern 120 may be formed of a polysilicon layer doped with N + type impurities, for example, phosphorus (P), arsenic (As), or the like. A mask pattern 130 may be further formed on the first polysilicon layer pattern 120.

On the other hand, the second gate 150 is formed on the gate insulating film 103 of the second region. In the second gate 150, a second conductive film pattern 110b and a second polysilicon film pattern 122 are stacked.

Here, the second conductive film pattern 110b is formed thicker than the aforementioned first conductive film pattern 110a. The thickness of the second conductive film pattern 110b is, for example, about 1 to 230 mm 3. The second conductive layer pattern 110b may include a lower conductive layer pattern 111 and an upper conductive layer pattern 115 thereon.

The lower conductive layer pattern 111 may be formed of the same material and the same thickness as the first conductive layer pattern 110a described above. Therefore, since the first conductive layer pattern 110a positioned in the first region and the lower conductive layer pattern 111 positioned in the second region can be formed together, the process can be easily performed.

The upper conductive layer pattern 115 may have a suitable work function of about 4.8 to 5.5 eV of the second gate 150. The upper conductive layer pattern 115 may be formed at about 1 to about 200 μs so that the second gate 150 has a suitable work function, but is not limited thereto.

The lower conductive layer pattern 111 and the upper conductive layer pattern 115 may be formed of the same material as the first conductive layer pattern 110a. In addition, the first conductive layer pattern 110a, the lower conductive layer pattern 111, and the upper conductive layer pattern 115 may be formed of the same metal material. In this case, the lower and upper conductive film patterns 111 and 115 control the formation methods of the lower and upper conductive films 111 'and 115', which will be described later, to form respective films having different composition ratios, and the like. An etching rate for the 115 ′ may be formed by etching using an etchant higher than the etching rate for the lower conductive layer 111 ′.

The second polysilicon film pattern 122 is positioned on the second conductive film pattern 110b, and the second polysilicon film pattern 122 is formed of the same material or P + type as the first polysilicon film pattern 120 described above. It may be made of a polysilicon film doped with impurities, for example, boron (B).

Spacers 160 may be formed on sidewalls of each of the gates 140 and 150, and source and drain regions 171 and 173 are disposed in a semiconductor substrate adjacent to each of the gates 140 and 150.

As such, the semiconductor device according to the exemplary embodiment includes only the polysilicon by including the first or second conductive layer patterns 110a and 110b at lower ends of the first and second polysilicon gates 140 and 150. Carrier depletion may occur at the lower end of the gate. Therefore, the gate depletion phenomenon can be improved by controlling the increase in the electrical thickness of the gate insulating film. In addition, as the first polysilicon layer pattern 120 positioned in the first region and the upper conductive layer pattern 115 positioned in the second region adjust the work function, the semiconductor devices have dual gates having optimized work functions. The reliability of the semiconductor device can be improved.

Also, in a gate formed of polysilicon, when a high dielectric material film such as HfSiON material is used as the gate insulating film, the threshold voltage may increase due to the reaction between the gate insulating film and the polysilicon gate formed on the gate insulating film. have. In addition, as the thickness of the gate insulating layer decreases, impurities doped in the gate, for example, may cause a problem that the characteristics of the semiconductor device deteriorate as boron diffuses through the gate insulating layer to the channel region. However, the inclusion of the first or second conductive layer patterns 110a and 110b at the lower end of the polysilicon gate has the effect of fundamentally blocking such a problem.

Hereinafter, a semiconductor device according to another exemplary embodiment of the present invention will be described with reference to FIG. 1.

Referring to FIG. 1, in the semiconductor device according to another exemplary embodiment, the first conductive layer pattern 110a is disposed in the first region of the semiconductor substrate 100, and the second conductive layer pattern 110b is formed in the semiconductor substrate 100. And the second conductive film pattern 110b is the same as the exemplary embodiment of the present invention except that the second conductive film pattern 110b includes two or more materials.

The second conductive film pattern 110b of the semiconductor device according to the exemplary embodiment of the present invention includes a lower conductive film pattern 111 and an upper conductive film pattern 115 thereon. Here, the lower conductive layer pattern 111 and the upper conductive layer pattern 115 may be formed of the same material. For example, the lower conductive layer pattern 111 and the upper conductive layer pattern 115 are formed of a metal material. However, the lower conductive layer pattern 111 and the upper conductive layer pattern 115 may be made of another metal material having different etching selectivity with respect to the etching etchant. This may be useful for selectively etching the upper conductive layer pattern 115 in a semiconductor manufacturing method to be described later.

According to another exemplary embodiment of the inventive concept, the semiconductor device may include first or second conductive layer patterns 110a and 110b at lower ends of the first and second polysilicon gates 140 and 150. The same effect as that of the exemplary embodiment, that is, the gate depletion phenomenon may be improved, and the characteristics of the semiconductor device may be improved by providing dual gates having optimized work functions. In addition, the formation of the lower and upper conductive film patterns 111 and 115 of the second conductive film pattern 110b is not limited to the respective forming methods.

Hereinafter, a method of manufacturing the aforementioned semiconductor devices will be described. In the following description of the manufacturing method, a process that can be formed according to process steps well known to those skilled in the art will be briefly described in order to avoid obscuring the present invention. In addition, descriptions of structures, materials, and the like that may be applied in substantially the same manner as described above will be omitted or briefly described below in order to avoid duplication.

2A through 2G are cross-sectional views sequentially illustrating a manufacturing method according to an exemplary embodiment of the present invention for manufacturing the semiconductor device of FIG. 1.

Referring to FIG. 2A, first, a gate insulating layer 103 is formed in first and second regions on the semiconductor substrate 100.

The gate insulating layer 103 may be formed by thermally oxidizing the semiconductor substrate 100 or by depositing a gate insulating material.

Then, as shown in FIG. 2B, the lower conductive film 111 ′ and the upper conductive film 115 ′ are formed on the entire surface of the semiconductor substrate 100 on which the gate insulating film 103 is formed.

The lower conductive layer 111 ′ and the upper conductive layer 115 ′ may be formed of the same material. Further, although the lower conductive film 111 ′ and the upper conductive film 115 ′ may be formed of the same metal material, the formation method of each film may be different. For example, the lower conductive film 111 'is formed by a method of sequential flow deposition (SFD), and the upper conductive film (Metal Organic CVD (MOCVD)) is formed thereon. 115 ').

 This is controlled to have different viewing selectivity with respect to the etching etchant by controlling the method of forming the lower conductive film 111 'and the upper conductive film 115' so that the upper conductive film 115 'in the first region in the subsequent process. May be selectively removed to leave only the lower conductive layer 111 ′.

Although not shown in the drawings, a hard mask layer may be selectively formed on the upper conductive layer 115 ′. The hard mask layer may be formed by Chemical Vapor Deposition (CVD), but is not limited thereto.

A material that can be used as the hard mask layer is a material having an etching selectivity with respect to the upper conductive layer 115 ′, and may be, for example, SiO 2, SiN, SiON, or Si.

Next, as shown in FIG. 2C, a photoresist pattern 117 exposing the first region is formed on the upper conductive layer 115 ′ in the second region. The photoresist pattern 117 can be formed by a conventional method.

Then, as illustrated in FIG. 2D, the upper conductive film 115 ′ formed in the first region is selectively removed. As a result, the first conductive layer 110 ′ a formed of only the lower conductive layer 111 ′ remains in the first region, and the lower conductive layer 111 ′ and the upper conductive layer 115 ′ are formed in the second region. The second conductive layer 110 ′ b may be maintained. If a hard mask exposing the first region is formed, the upper conductive layer formed in the first region may be selectively removed using the hard mask as an etching mask.

The selective removal of the upper conductive film 115 ′ in the first region may be performed by selecting the etching selectivity for the etching etchant according to the method of forming the lower conductive film 110 ′ and the upper conductive film 115 ′ as described above. It can be achieved by adjusting.

Specifically, even if the lower conductive layer 111 'and the upper conductive layer 115' are formed of the same material, the etching selectivity of the upper conductive layer 115 'with respect to the etching etchant is controlled by controlling the formation method of each layer. It may be adjusted to be formed higher than the lower conductive layer 110 ′. Accordingly, the upper conductive layer 115 ′ may be selectively removed, but the lower conductive layer 111 ′ may remain. In this case, the etching etchant is a material having a low etching selectivity so as not to etch the photoresist pattern 117 or to leave the photoresist pattern 117 until the upper conductive layer 115 'is removed. desirable. However, when the hard mask film pattern is used as an etching mask, only the etching selectivity for the hard mask film pattern is considered, and the etching selectivity for the photoresist pattern 117 may be excluded. have. According to a specific application example, when both the lower conductive film 111 'and the upper conductive film 115' are formed of TiN, the lower conductive film 111 'is formed by the SFD method, and the upper conductive film 115' is Formed by the MOCVD method, the etchant used comprises NH ₄ OH, H ₂ O ₂ , HO ₂ is a SC1 solution mixed in a ratio of about 1: 4: 20.

In this etching process, since the gate insulating film 103 of the first region is not exposed, damage to the gate insulating film 103 can be prevented in advance.

Next, as shown in FIG. 2E, the photoresist pattern 117 is removed.

At this time, when the hard mask film pattern is formed, the hard mask film pattern is also removed.

Next, as shown in FIG. 2F, a polysilicon film 120 ′ is formed on the entire surface of the semiconductor substrate. Then, a mask pattern 130 for patterning the gate may be further formed on the polysilicon film 120 '.

Next, as shown in FIG. 2G, the first gate 140 and the second gate 150 may be formed by patterning the mask pattern 130 as an etch mask. As shown in the drawing, the first conductive layer pattern 110a and the first polysilicon layer pattern 120 are stacked on the first gate 140, and the second conductive layer pattern is formed on the second gate 150. 110b and the second polysilicon film pattern 122 are stacked and provided. Here, since the second polysilicon layer pattern 122 of the second gate 150 may be formed of both a polysilicon layer doped with N + type or P + type impurities, the first polysilicon layer doped with N + type impurities may be formed. When the first polysilicon layer pattern 120 of the gate 140 is formed, they may be formed together. Therefore, it may be easier in the process compared to the device of the dual gate semiconductor which must form a polysilicon film doped with N + type and P + type impurities, respectively.

The patterning process may be performed by sequentially removing the polysilicon layer 120 ', the upper conductive layer 115', and the lower conductive layer 111 'by a conventional dry etching process or a wet etching process.

Thereafter, according to the process steps well known to those skilled in the art of semiconductor devices, forming the source and drain regions to complete the PMOS transistor and the NMOS transistor, forming a spacer, and the like. The semiconductor device shown in FIG. 1 can be formed.

In addition, as a subsequent step, the semiconductor device may be completed by forming wirings to enable input and output of electrical signals to each transistor, forming a passivation layer on the substrate, and packaging the substrate. . These subsequent steps omit the description in order to avoid obscuring the present invention.

Hereinafter, a method of manufacturing a semiconductor device according to another exemplary embodiment of the present invention will be described with reference to FIGS. 2A to 2G.

2A to 2G, a method of manufacturing a semiconductor device according to another embodiment of the present invention is performed except that a second conductive film including two or more materials is formed in a second region. Since it is the same as the method of manufacturing the semiconductor element of FIG. 1 which concerns on the example, the description is abbreviate | omitted.

A method of manufacturing a semiconductor device according to another embodiment of the present invention is to form a lower conductive film 111 ′ and an upper conductive film 115 ′ on a semiconductor substrate 100 on which a gate insulating film is formed. Can be formed. This is because the etching selectivity of the upper conductive film 115 'with respect to the etching etchant is higher than that of the lower conductive film 111' so that the upper conductive film 115 'is not controlled without controlling the formation method of each film. Although selectively removed, the lower conductive layer 111 ′ may be easily retained. Specific applications include that the lower conductive layer 111 'is HfSiON, the upper conductive layer 115' is HfCN, and the etchant used is an HF solution diluted at a ratio of about 500: 1.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

As described above, the semiconductor device according to the present invention may improve the gate depletion phenomenon by providing the first and second conductive layer patterns on the lower ends of the gates positioned on the first region and the second region. In addition, electrical properties can be improved by optimizing the work function. In addition, according to the method of manufacturing a semiconductor device according to the present invention, it is possible to implement a semiconductor device having dual gates having different structures without damaging the gate insulating film.

Claims (7)

A semiconductor substrate including a first region and a second region; A gate insulating film formed in the first and second regions on the semiconductor substrate; A first gate formed on the gate insulating film in the first region and including a first conductive film pattern and a first polysilicon film pattern formed on the first conductive film pattern; And A second gate formed on the gate insulating layer in the second region, the second gate including a second conductive layer pattern thicker than the first conductive layer pattern and a second polysilicon layer pattern formed on the second conductive layer pattern; Semiconductor device. According to claim 1, The second conductive layer pattern includes a lower conductive layer pattern and an upper conductive layer pattern formed on the lower conductive layer pattern, wherein the lower conductive layer pattern is formed of the same material as the first conductive layer pattern. According to claim 1, The first and second conductive film patterns may include TaN, WN, TiN, Ta, W, Ti, Ru, HfN, HfSiN, TiSiN, TaSiN, HfAlN, or a combination thereof. The method of claim 2, The first polysilicon layer pattern has a work function of 4.0 to 4.5 eV or less, and the upper conductive layer pattern has a work function of 4.8 to 5.5 eV. Forming a gate insulating film in the first and second regions on the semiconductor substrate including a first region and a second region, A lower conductive film and an upper conductive film are sequentially formed on the gate insulating film, Selectively removing the upper conductive film of the first region to expose the lower conductive film of the first region, Forming a polysilicon film on the entire surface of the resultant, Performing a patterning process to form a first gate including a first conductive layer pattern in the first region and a first polysilicon layer pattern formed on the first conductive layer pattern, and forming a first gate in the second region than the first conductive layer pattern Forming a second gate including a thick second conductive film pattern and a second polysilicon film pattern formed on the second conductive film pattern. The method of claim 5, The second conductive layer pattern includes a lower conductive layer pattern and an upper conductive layer pattern formed on the lower conductive layer pattern, wherein the lower conductive layer pattern is made of the same material as the first conductive layer pattern. The method of claim 5, The selective removal of the upper conductive layer is a method of manufacturing a semiconductor device by using an etching etchant having an etching rate for the upper conductive layer is higher than the etching rate for the lower conductive layer.

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