KR20030049896A - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor device Download PDFInfo
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- KR20030049896A KR20030049896A KR1020010080229A KR20010080229A KR20030049896A KR 20030049896 A KR20030049896 A KR 20030049896A KR 1020010080229 A KR1020010080229 A KR 1020010080229A KR 20010080229 A KR20010080229 A KR 20010080229A KR 20030049896 A KR20030049896 A KR 20030049896A
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- 238000000034 method Methods 0.000 title claims abstract description 36
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000005530 etching Methods 0.000 claims abstract description 22
- 239000012530 fluid Substances 0.000 claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000000231 atomic layer deposition Methods 0.000 claims abstract description 6
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 13
- 230000009969 flowable effect Effects 0.000 claims description 10
- 238000009832 plasma treatment Methods 0.000 claims description 6
- 238000006243 chemical reaction Methods 0.000 claims description 5
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 claims description 4
- 238000000280 densification Methods 0.000 claims description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 2
- 150000004767 nitrides Chemical class 0.000 abstract description 10
- 230000004888 barrier function Effects 0.000 abstract description 3
- 229910052751 metal Inorganic materials 0.000 abstract description 3
- 239000002184 metal Substances 0.000 abstract description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract 12
- 239000010408 film Substances 0.000 description 61
- 125000006850 spacer group Chemical group 0.000 description 7
- 239000011229 interlayer Substances 0.000 description 5
- 239000010410 layer Substances 0.000 description 5
- 239000010409 thin film Substances 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- -1 nitride nitride Chemical class 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- CTQNGGLPUBDAKN-UHFFFAOYSA-N O-Xylene Chemical compound CC1=CC=CC=C1C CTQNGGLPUBDAKN-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000007806 chemical reaction intermediate Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000543 intermediate Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000008096 xylene Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
- H01L21/02312—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour
- H01L21/02315—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
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Abstract
Description
본 발명은 반도체 기술에 관한 것으로, 특히 APL(Advanced Planalization Layer) 박막을 이용한 반도체 소자 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly, to a method of manufacturing a semiconductor device using an Advanced Planalization Layer (APL) thin film.
0.1㎛ 이하의 선폭을 갖는 반도체 소자 기술에서는 절연산화막의 갭-필(Gap-fill) 특성에 있어서 콘택홀 등의 스페이스가 감소하고 종횡비(Aspect ratio)가 점점 증가함에 따라 완전한 필링(Filling, 채움)이 불가능하여, 보이드(Void)가 생기는 문제점이 발생하는 바, 이러한 문제점을 해결하기 위해 플로우 특성을 갖는 절연막 즉, 유동성 절연막을 형성하는 기술인 APL(Advanced Planalization Layer) 박막에 대한 연구가 활발히 진행되고 있다.In the semiconductor device technology having a line width of 0.1 μm or less, in the gap-fill characteristics of the insulating oxide film, the filling of the contact hole is reduced as the space of the contact hole decreases and the aspect ratio gradually increases. Due to this problem, voids occur, and thus, an APL (Advanced Planalization Layer) thin film, which is a technology of forming an insulating film having flow characteristics, that is, a fluid insulating film, has been actively studied to solve such problems. .
이러한, APL 박막 기술 중 자기 평탄화 CVD(화학기상증착; 이하 CVD라 함)막은 상당히 유동성이 높은 반응 중간체를 형성하는 것으로, 막 형성을 할 때 우수하게 채움 평탄화를 실현할 수 있다. 그 때문에 평탄화된 층간절연막 형성을 단일한 공정으로 할 수 있어서 종래의 복잡한 공정에 비해서 공정 비용을 효과적으로 줄일 수 있는 바, 자기 평탄화 CVD막은 저압화학기상증착(Low Pressure Chemical Vapor Deposition; 이하 LPCVD라 함)법을 이용하여 반응소스로 과수(H2O2)와 사일렌(SiH4)을 이용하여 형성하며, 자체적인 플로우 특성을 갖고 있어 갭-필 특성이 우수한 장점이 있다.In the APL thin film technology, the self-planarized CVD (chemical vapor deposition; CVD) film forms a highly flowable reaction intermediate, which can achieve excellent fill planarization when forming the film. Therefore, the planarized interlayer insulating film can be formed as a single process, and the process cost can be effectively reduced as compared with the conventional complicated process. It is formed by using fruit tree (H 2 O 2 ) and xylene (SiH 4 ) as a reaction source by the method, and has an advantage of excellent gap-fill characteristics because it has its own flow characteristics.
그러나, 자기 평탄화 CVD막 즉, 유동성 산화막은 배선 애의 스페이스 지역의 골 내부에는 수십Å 정도의 미세기공(Nanopore)이 존재하는 단점이 있는 바, 이러한 미세기공은 랜딩플러그콘택(Landing Plug Contact; 이하 LPC라 함) 형성시 스페이스 내부에서 식각멈춤(Etch stop) 현상을 유발하여 원하는 크기의 콘택을 형성할 수 없는 문제점이 발생한다.However, the self-planarizing CVD film, that is, the flowable oxide film has a disadvantage in that there are several tens of nanoporosity inside the valley of the space area of the interconnection bar, and the micropores are called Landing Plug Contact. LPC) causes an etch stop phenomenon in the space to form a contact of a desired size.
도 1과 도 2는 LPC 식각 후의 단면을 도시한 SEM 사진으로서, 도 1에 도시된 'A'와 같이 식각멈춤에 의해 불완전한 콘택 오픈 형상이 발생한다.1 and 2 are SEM photographs showing the cross section after the LPC etching, incomplete contact open shape is generated by the etch stop as shown in 'A' shown in FIG.
한편, 전술한 식각멈춤 현상은 스페이스 내부에 존재하는 미세기공과 스페이스의 하부 지역에 존재하는 질화막 표면에서의 식각 정도차에 기인하는 것으로, 공정 스킴(Scheme)을 변경하여 스페이스 하부에 존재하지 않는 경우에는 도 2에 도시된 'B'와 같이 식각멈춤없이 양호한 콘택 오픈이 이루어진다.On the other hand, the etch stop phenomenon described above is due to the difference in the degree of etching between the micropores present in the space and the surface of the nitride film present in the lower region of the space, when the process scheme is changed and does not exist at the bottom of the space. As shown in FIG. 2, a good contact opening is performed without stopping the etching.
전술한 도 1의 제조 공정과 도 2의 제조 공정을 간단히 살펴 본다.The manufacturing process of FIG. 1 and the manufacturing process of FIG. 2 are briefly described.
도 1의 경우 비트라인 패턴을 형성한 다음 스페이서용 질화막을 형성하고 비트라인 사이를 충분히 채울 정도로 유동성 절연막을 형성한 후 LPC 공정을 통해 비트라인 사이의 기판을 노출시키는 일련의 공정을 거치게 되며, 도 2의 경우 비트라인 패턴을 형성한 다음 스페이서용 질화막을 형성하고 전면식각을 통해 질화막 스페이서를 형성한 후, 비트라인 사이를 충분히 채울 정도로 유동성 절연막을 형성한 후 LPC 공정을 통해 비트라인 사이의 기판을 노출시키는 일련의 공정을 거치게 된다.In the case of FIG. 1, after forming a bit line pattern, a nitride film for a spacer is formed, a fluid insulating layer is formed to sufficiently fill the bit lines, and then a series of processes are performed to expose the substrate between the bit lines through an LPC process. In the case of 2, after forming a bit line pattern, a nitride film for spacers is formed, and a nitride film spacer is formed through front etching, a fluid insulating film is formed to sufficiently fill the bit lines, and then the substrate between the bit lines is formed through an LPC process. It goes through a series of processes that expose them.
전술한 도 2의 제조 공정에 의해서는 LPC 공정이 양호한 콘택 오픈이 이루어지나, 스페이스 하부의 질화막을 제거하기 위해서는 추가의 식각 공정이 필요할 뿐만아니라 식각 후 텅스텐 등으로 이루어진 비트라인 위에 존재하는 하드마스크 질화막가 손실되어 자기 정렬콘택(Self Align Contact; 이하 SAC이라 함) 공정에서의 불량을 유발할 가능성이 있으며, 비트라인 식각 후 형성하는 스페이서용 질화막은 비트라인이 후속 공정에서 산화(Oxidation)되는 것을 방지하는 역할을 하기 때문에생략할 수 없다.In the manufacturing process of FIG. 2 described above, the LPC process has a good contact opening, but in order to remove the nitride film under the space, an additional etching process is required, and a hard mask nitride film on the bit line made of tungsten or the like after etching is formed. It may be lost and cause defects in the Self Align Contact (hereinafter referred to as SAC) process, and the nitride nitride film for spacers formed after etching the bit line prevents the bit line from being oxidized in a subsequent process. Because it can not be omitted.
본 발명은 상기한 종래기술의 문제점을 해결하기 위해 제안된 것으로서, 콘택 형성시 식각멈춤 특성을 방지하기에 적합한 반도체 소자 제조 방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the above problems of the prior art, and an object of the present invention is to provide a method for manufacturing a semiconductor device suitable for preventing an etch stop characteristic when forming a contact.
도 1과 도 2는 LPC 식각 후의 단면을 도시한 SEM 사진,1 and 2 are SEM photographs showing a cross section after LPC etching;
도 3a 내지 도 3c는 본 발명의 일실시예에 따른 반도체 소자 제조 공정을 도시한 단면도.3A to 3C are cross-sectional views illustrating a semiconductor device manufacturing process in accordance with an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
10 : 기판11 : 배리어막10 substrate 11 barrier film
12 : 금속막 13 : 질화막12 metal film 13 nitride film
14 : 알루미늄 산화막15 : 유동성 절연막14 aluminum oxide film 15 fluid insulating film
16 : 콘택홀16: contact hole
상기의 목적을 달성하기 위해 본 발명은, 기판 상에 이웃하는 다수의 도전패턴을 형성하는 단계; 상기 도전패턴이 형성된 전체 프로파일을 따라 알루미늄산화막을 형성하는 단계; 상기 알루미늄산화막 상에 유동성 절연막을 형성하는 단계; 및 상기 유동성 절연막을 선택적으로 식각하여 상기 도전패턴 사이의 상기 기판 표면을 노출시키는 콘택홀을 형성하는 단계를 포함하는 반도체 소자 제조 방법을 제공한다.In order to achieve the above object, the present invention comprises the steps of forming a plurality of neighboring conductive patterns on the substrate; Forming an aluminum oxide film along an entire profile in which the conductive pattern is formed; Forming a fluid insulating film on the aluminum oxide film; And selectively etching the flexible insulating layer to form a contact hole exposing the surface of the substrate between the conductive patterns.
본 발명은 유동성 절연막을 갭-필 물질로 사용하는 공정에서 콘택 식각시 발생하는 식각멈춤을 억제하여 유니폼(Uniform)한 콘택 형성을 이루기 위해, 유동성 절연막과 식각 정도에 차이를 갖는 질화막 대신에 알루미늄 산화막을 스페이서용 절연막으로 사용함으로써 식각멈춤 현상을 방지하여 양호한 콘택 형성 프로파일을 얻도록 하는 것을 기술적 특징으로 한다.According to the present invention, an aluminum oxide film is used instead of a nitride film having a difference in etching degree from the fluid insulating film in order to achieve uniform contact formation by suppressing the etch stop generated during contact etching in a process using the fluid insulating film as a gap-fill material. By using the insulating film for the spacer to prevent the etching stop phenomenon to obtain a good contact formation profile is a technical feature.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부한 도 3a 내지 도 3c를 참조하여 상세하게 설명한다.Hereinafter, in order to explain in detail enough to enable those skilled in the art to easily carry out the technical idea of the present invention, refer to FIGS. 3A to 3C attached to the most preferred embodiment of the present invention. It will be described in detail.
도 3a 내지 도 3c는 본 발명의 일실시예에 따른 반도체 소자 제조 공정을 도시한 단면도로서, 이를 참조하여 후술한다.3A to 3C are cross-sectional views illustrating a semiconductor device manufacturing process according to an embodiment of the present invention, which will be described later with reference to the drawings.
먼저, 도 3a에 도시된 바와 같이 반도체 소자를 이루기 위한 여러 요소가 형성된 기판(10) 상에 소정의 도전패턴을 형성하는 바, 도전패턴은 워드라인 또는 비트라인 등을 포함하며, 이하에서는 비트라인을 그 일예로 하여 설명한다.First, as shown in FIG. 3A, a predetermined conductive pattern is formed on a substrate 10 on which various elements for forming a semiconductor device are formed. The conductive pattern includes a word line or a bit line, and in the following, a bit line Will be described as an example.
구체적으로, 배리어막(11)과 텅스텐 등의 비트라인용 금속막(12)과 하드마스크용 질화막(13)을 차례로 증착한 후, 비트라인 마스크를 이용한 선택적 공정을 실시하여 비트라인(B/L)을 형성한다.Specifically, the barrier film 11, the bit line metal film 12 such as tungsten, and the hard mask nitride film 13 are sequentially deposited, and then a bit line (B / L) is performed by performing a selective process using a bit line mask. ).
다음으로, 도 3b에 도시된 바와 같이 비트라인(B/L)을 포함한 프로파일을 따라 스페이서용 알루미늄 산화막(14)을 형성하는 바, 이 때 콘택 스페이스 등을 감안하여 10Å ∼ 100Å의 두께로 얇게 형성한다.Next, as shown in FIG. 3B, an aluminum oxide film 14 for spacers is formed along the profile including the bit lines B / L. At this time, in consideration of a contact space, the aluminum oxide film 14 is thinly formed to have a thickness of 10 μs to 100 μs. do.
이 때, 원자층증착(Atomic Layer Deposition; 이하 ALD라 함)법을 이용하는 것이 바람직한 바, 주지된 바와 같이 ALD법은 수십Å의 얇은 두께로의 형성이 가능하며 단차피복성(Step coverage) 또한 우수하다.At this time, it is preferable to use atomic layer deposition (hereinafter referred to as ALD) method. As is well known, the ALD method can be formed to a thin thickness of several tens of micrometers and also has excellent step coverage. Do.
다음으로, 도 3c에 도시된 바와 같이 비트라인(B/L) 사이의 스페이스를 충분히 채울 수 있을 정도로 유동성 절연막(15)을 형성한 다음, 유동성 절연막을 선택적으로 식각하여 기판(10) 표면을 노출시키는 콘택홀(16)을 형성한다.Next, as shown in FIG. 3C, the liquid insulating film 15 is formed to sufficiently fill the space between the bit lines B / L, and then the liquid insulating film is selectively etched to expose the surface of the substrate 10. Contact holes 16 are formed.
한편, 본 발명에서는 후속 층간절연막으로 HDP 산화막 대신 플로우 및 자체 평탄화 특성이 우수한 APL 박막을 층간절연막으로 적용하며, 특히 APL 박막 기술 중 자기 평탄화 CVD막을 적용하는 바, 자기 평탄화 CVD막은 상당히 유동성이 높은 반응 중간체를 형성하는 것으로, 막 형성을 할 때 우수하게 채움 평탄화를 실현할 수 있다. 그 때문에 평탄화된 층간절연막 형성을 단일한 공정으로 할 수 있어서 종래의 복잡한 공정에 비해서 공정 비용을 효과적으로 줄일 수 있다.Meanwhile, in the present invention, an APL thin film having excellent flow and self-planarization properties is applied as an interlayer insulating film instead of an HDP oxide film as a subsequent interlayer insulating film. In particular, a self-planarizing CVD film is applied in the APL thin film technology. By forming the intermediate, it is possible to realize filling flattening excellent when forming a film. Therefore, the planarized interlayer insulating film can be formed as a single process, and the process cost can be effectively reduced as compared with the conventional complicated process.
이러한 자기 평탄화 CVD막 즉, 유동성 절연막(15)은 LPCVD법에 의해 SiH4와 H2O2에 의한 CVD로 형성한 실리콘산화막으로 상당히 우수한 채움 평탄성을 갖고 있으며, 또한 형성된 막은 막중의 함유 수분이 적어 고품질이다.This self-planarized CVD film, that is, the fluid insulating film 15 is a silicon oxide film formed by CVD by SiH 4 and H 2 O 2 by LPCVD, and has a very good filling flatness. It is high quality.
구체적으로, 유동성 절연막(15)을 형성하기 전에 후속 유동성 절연막의 접착력 및 갭-필(Gap-fill) 특성을 향상시키기 위해 플라즈마 처리가 필요하며, 이 때 N2O를 포함한 플라즈마를 이용한다.Specifically, before forming the flowable insulating film 15, a plasma treatment is required to improve the adhesion and gap-fill characteristics of the subsequent flowable insulating film, wherein a plasma including N 2 O is used.
이어서, 알루미늄산화막(14) 상부에 유동성 절연막(15)을 형성하는 바, N2O 등의 질소를 포함하는 반응소스를 이용한 LPVCD법을 사용하여 적절한 두께로 형성하며, 이 때 유동성 절연막(15)은 SiOxHy(x는 0 ∼ 3, y는 0 ∼ 1)의 성분을 포함한다.Subsequently, the flowable insulating film 15 is formed on the aluminum oxide film 14, and is formed to an appropriate thickness by using an LPVCD method using a reaction source containing nitrogen such as N 2 O. is SiO x H y (x is from 0 to 3, y is from 0 to 1) contain components.
구체적으로, 전술한 질소를 포함하는 반응소스는 SiH4, SiHa(CH3)b(a, b는 0∼ 4), H2O2, O2, H2O 및 N2O를 포함하는 것으로, 이러한 반응소스를 이용하여 100mTorr ∼ 2Torr의 저압 및 -10℃ ∼ 100℃의 온도 하에서 실시하며, 이 때 100SCCM ∼ 3000SCCM 유량의 N2O를 사용하는 것이 바람직하다.Specifically, the reaction source containing nitrogen described above includes SiH 4 , SiHa (CH 3 ) b (a, b is 0 to 4), H 2 O 2 , O 2 , H 2 O and N 2 O. Using such a reaction source, it is carried out under a low pressure of 100 mTorr to 2 Torr and a temperature of -10 ° C to 100 ° C, and it is preferable to use N 2 O at a flow rate of 100SCCM to 3000SCCM.
이어서, 유동성 절연막(15) 형성에 따른 유동성 절연막(15) 내에 잔류하는 수분을 제거하며 유동성 절연막(15)의 치밀화를 위해 플라즈마 처리 또는 열처리를 추가로 실시한다.Subsequently, water remaining in the fluid insulating film 15 due to the formation of the fluid insulating film 15 is removed, and plasma treatment or heat treatment is further performed for densification of the fluid insulating film 15.
구체적으로, 플라즈마 처리는 SiH4, SiHa(CH3)b(a, b는 0 ∼4), N2, NH3, O2, O3, Ar, He, Ne 또는 N2O 등의 가스를 혼합하여 5초 ∼ 200초 동안 실시하며, 열처리는 O2, N2, O3, N2O 또는 H2등의 가스 분위기 및 600℃ ∼ 800℃의 온도 하에서 10초 ∼ 200초 동안 실시하는 것이 바람직하다.Specifically, the plasma treatment is a gas such as SiH 4 , SiH a (CH 3) b (a, b is 0 to 4), N 2 , NH 3 , O 2 , O 3 , Ar, He, Ne or N 2 O The mixture is carried out for 5 seconds to 200 seconds, and the heat treatment is performed for 10 seconds to 200 seconds under a gas atmosphere such as O 2 , N 2 , O 3 , N 2 O, or H 2 and a temperature of 600 ° C. to 800 ° C. desirable.
계속해서, 유동성 절연막(15) 상에 콘택 형성을 위한 포토레지스트 패턴(도시하지 않음)을 형성한 다음, 이를 식각마스크로 한 선택적 식각 공정을 통해 비트라인(B/L) 사이의 기판(10) 표면을 노출시키는 콘택홀(16)을 형성한다.Subsequently, a photoresist pattern (not shown) for forming a contact is formed on the flowable insulating layer 15, and then the substrate 10 between the bit lines B / L is subjected to a selective etching process using the etching mask as an etching mask. A contact hole 16 exposing the surface is formed.
따라서, 알루미늄산화막(14)에 의해 후속 공정에 따른 비트라인(B/L)의 산화를 방지할 수 있으며, 알루미늄산화막(14)과 유동성 절연막(15)의 식각 정도가 비슷하여 식각멈춤이 발생하지 않으며, 균일한 식각 프로파일을 얻을 수 있다.Accordingly, the oxidation of the bit line (B / L) according to a subsequent process can be prevented by the aluminum oxide film 14, and the etching degree of the aluminum oxide film 14 and the flowable insulating film 15 is similar, so that the etching stop does not occur. And a uniform etching profile can be obtained.
전술한 본 발명은, 유동성 절연막을 층간절연막으로 사용하는 경우 비트라인등의 스페이서용 절연막으로 알루미늄 산화막을 적용함으로써, 종래의 유동성 절연막과 스페이서용 질화막의 식각 정도의 차이에 기인한 식각멈춤 현상을 방지할 수 있으며, 유니폼한 콘택을 형성할 수 있음을 실시예를 통해 알아 보았다.In the present invention described above, when the fluid insulating film is used as an interlayer insulating film, by applying an aluminum oxide film as a spacer insulating film such as a bit line, an etching stop phenomenon due to a difference in etching degree between the conventional fluid insulating film and the spacer nitride film is prevented. It can be seen, it was found through the embodiment that a uniform contact can be formed.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 본 발명은, 콘택 오픈 결함을 방지함으로써 소자의 불량 확률을 감소시킬 수 있어, 궁극적으로 반도체 소자의 수율을 향상시킬 수 있는 탁월한 효과를 기대할 수 있다.As described above, the present invention can reduce the probability of failure of a device by preventing contact open defects, so that an excellent effect of ultimately improving the yield of a semiconductor device can be expected.
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