KR100927394B1 - Semiconductor device using selective epitaxial growth method and manufacturing method thereof - Google Patents

Abstract

The present invention provides a semiconductor device and a method of manufacturing the same that can reduce the resistance so as to be applicable even in a semiconductor process of 50 nm or less in forming a plug using SEG, A plurality of neighboring conductive layer patterns; A silicon epi layer which is in contact with the substrate between the conductive layer patterns and is formed at a height lower than the height of the conductive layer pattern from the silicon substrate; And a tungsten film formed on the silicon epi layer and formed as a plug stacked with the silicon epi layer, the tungsten film being isolated from the neighboring plug.

The present invention also provides a method of manufacturing a semiconductor device, comprising: forming a plurality of conductive layer patterns disposed on a silicon substrate and adjacent to each other; Forming an insulating film on the entire surface of the conductive layer pattern; Forming a photoresist pattern for forming a contact hole between the conductive layer patterns on the insulating film; Etching the insulating film using the photoresist pattern as an etching mask to form a contact hole exposing the silicon substrate; Forming a silicon epitaxial layer in contact with the exposed silicon substrate through the contact hole and having a height lower than the height of the conductive layer pattern from the silicon substrate; Depositing a tungsten film on the silicon epilayer; And polishing the tungsten film through a chemical mechanical polishing process to form a plug in which the silicon epilayer and the tungsten film are stacked.

Selective epitaxial growth (SEG), plug, facet, silicon epilayer, tungsten film.

Description

FIELD OF THE INVENTION [0001] The present invention relates to a semiconductor device using a selective epitaxial growth method,             

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional SEM photograph showing a silicon epilayer grown as a contact plug.

2 is a graph showing the cell resistance change between a plug formed by the SEG method and a plug formed by polysilicon deposition.

3 is an SEM photograph showing abnormal silicon growth when a plug is formed by the SEG method.

4 is a cross-sectional view of a semiconductor device including a plug formed by simultaneously applying SEG and polysilicon deposition.

5A to 5E are cross-sectional views illustrating a plug forming process of a semiconductor device according to an embodiment of the present invention.

6 is a sectional view showing a semiconductor device in which a plug having a double structure is formed according to an embodiment of the present invention;

Description of the Related Art [0002]                 

50: substrate 51: conductive region

52: conductive layer 53: hard mask

54: etch stop film 55: insulating film

57: silicon epi layer 58: tungsten film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor technology, and more particularly, to a method of forming a plug using Selective Epitaxial Growth (SEG).

Research on the use of SEG as a method of forming a plug material after the self alignment contact (hereinafter referred to as SAC) forming process in a series of manufacturing processes for constituting a semiconductor device has been actively carried out, When the plug is formed, the contact resistance can be reduced by one to two times or more in the line width of less than 0.1 탆 compared with the conventional deposition.

1 is a cross-sectional SEM photograph showing a silicon epilayer grown as a contact plug.

1, a conductive pattern, for example, a gate electrode pattern having a structure in which a conductive layer 11 and a hard mask 12 are laminated is formed on a silicon substrate 10. An insulating film 13 is formed on a conductive pattern Respectively. A plug 15 penetrating the insulating film 13 and contacted to the silicon substrate 10 is formed.

The plug 15 is a silicon epitaxial layer grown on the silicon substrate 10 and the silicon epi layer is grown as monocrystalline silicon 15a in the contact region of the silicon substrate 10 as shown, The polysilicon 15b is grown on the sidewalls of the polysilicon 15b.

Since the plug 15 made of the silicon epitaxial layer grows in the contact portion with the silicon substrate 10 as described above, the contact area between the silicon substrate 10 and the single crystal silicon 15a is reduced Increase in contact resistance is suppressed.

2 is a graph showing a change in cell resistance between a plug formed by the SEG method and a plug formed by polysilicon deposition.

2 (a) is a graph showing the probability of occurrence of the cell resistance (k? / Tr.) Size. Referring to this, the plug A of the SEG type has a cell resistance of 20 It can be seen that the cell B has almost the cell resistance between 20 (k? / Tr.) And 40 (k? / Tr.).

2B is a graph showing a change in cell resistance (k [Omega] / Tr.) According to a contact open area (mu m ² ). Referring to FIG. 2B, It can be seen that the cell resistance A is located lower in the graph than the cell resistance (k? / Tr.) Of the plug B by the polysilicon deposition method, and the cell resistance is small.

A brief description will be given of the plug forming process by the SEG method.

First, a plurality of word lines are formed on a silicon substrate, a nitride-based etch stop layer is deposited along a word line formed profile, and an oxide interlayer insulating film is deposited on the entire surface. Then, an interlayer insulating layer and an etch stop layer are selectively etched through the SAC etching process to form a contact hole exposing the silicon substrate between the word lines. Then, a silicon epitaxial layer is formed from the silicon substrate exposed by the contact hole formation through the SEG method Grow.

3 is a SEM photograph showing abnormal silicon growth when a plug is formed by the SEG method.

Referring to FIG. 3, a thin film grown by SEG induces irregular silicon growth during growth, thereby causing defective devices such as a silicon cluster. A reference numeral '30' represents a chunk of silicon that is selectively broken during SEG growth, which causes defects in the subsequent process.

In addition, the silicon epitaxial layer grown by the SEG method tends to grow in an angular form such as a facet or the like, thereby causing a void or the like in the insulating film in the subsequent insulating film processing step.

In addition, as described above, although the silicon epitaxial layer by the SEG growth has a lower resistance than the polysilicon thin film, the thin film is still high for application to devices of 50 nm or less.

Meanwhile, in order to solve the above-mentioned problems, a method of concurrently using the SEG method and the polysilicon deposition method has been proposed.

4 is a cross-sectional view of a semiconductor device including a plug formed by simultaneously applying SEG and polysilicon deposition.

4, a conductive pattern, for example, a gate electrode pattern having a structure in which a conductive layer 41 and a hard mask 42 are laminated is formed on a silicon substrate 40. An insulating film 43 is formed on the conductive pattern, Respectively. A plug which is passed through the insulating film 13 and is contacted with the silicon substrate 10 is formed.

The plug consists of a silicon epilayer 44 grown on the silicon substrate 40 and a polysilicon layer 45 deposited thereon.

However, due to the high integration of semiconductor devices, the process technology of 50 nm or less has a limitation in paralleling the SEG method and polysilicon deposition due to the high resistivity of the silicon itself.

SUMMARY OF THE INVENTION The present invention has been proposed in order to solve the problems of the prior art described above, and it is an object of the present invention to provide a semiconductor device capable of lowering the resistance so as to be applicable to a semiconductor process of 50 nm or less in forming a plug using SEG, .

According to an aspect of the present invention, there is provided a semiconductor device comprising: a plurality of conductive layer patterns disposed on a silicon substrate and adjacent to each other; A silicon epi layer which is in contact with the substrate between the conductive layer patterns and is formed at a height lower than the height of the conductive layer pattern from the silicon substrate; And a tungsten film formed on the silicon epi layer and formed as a plug stacked with the silicon epi layer, the tungsten film being isolated from the neighboring plug.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a plurality of conductive layer patterns disposed on a silicon substrate and adjacent to each other; Forming an insulating film on the entire surface of the conductive layer pattern; Forming a photoresist pattern for forming a contact hole between the conductive layer patterns on the insulating film; Etching the insulating film using the photoresist pattern as an etching mask to form a contact hole exposing the silicon substrate; Forming a silicon epitaxial layer in contact with the exposed silicon substrate through the contact hole and having a height lower than the height of the conductive layer pattern from the silicon substrate; Depositing a tungsten film on the silicon epilayer; And polishing the tungsten film through a chemical mechanical polishing process to form a plug in which the silicon epilayer and the tungsten film are stacked.

A silicon epitaxial layer is formed by a SEG process on a portion of a lower portion which is in contact with a silicon substrate when a plug is formed and a highly conductive material such as tungsten is deposited on the silicon epitaxial layer and a tungsten film By forming stacked plugs, it is possible to suppress facet and pore generation and to lower the resistance in the course of the subsequent process.                     

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to explain the present invention in detail so that those skilled in the art can easily carry out the technical idea of the present invention. do.

6 is a cross-sectional view illustrating a semiconductor device having a plug of a double structure according to an embodiment of the present invention.

6, a plurality of conductive layer patterns in which a conductive layer 52 and a hard mask 53 are laminated are formed on a silicon substrate 50. A plurality of conductive layer patterns are formed on the silicon substrate 50 between the conductive layer patterns, (Not shown). A silicon nitride layer-based etch stop layer 54 is formed on the sidewall of the conductive layer pattern and a silicon epi layer 57 and a tungsten layer 58 formed by the SEG firing are stacked on the conductive region 51 between the conductive layer patterns A plug is formed. The plug is planarized over the hard mask 53 and the insulating film 55.

Here, the conductive layer pattern may include a gate electrode pattern, a bit line pattern, a metal wiring, or the like. And the gate oxide film disposed between the conductive layer 52 and the substrate 50 when the conductive layer pattern is a gate electrode pattern. The conductive region 51 at this time is an impurity junction layer such as a source / drain.

Although the tungsten film 58 is planarized with the hard mask 53 in the drawing, the tungsten film 58 may be planarized with the insulating film 55 such that the insulating film 55 remains on the hard mask 53.

6, in the present invention, a silicon epitaxial layer 57 of the SEG type is applied to a portion of the plug which is in contact with the substrate 50, and a tungsten film whose resistivity is lower than that of the polysilicon film The cell resistance can be lowered, and generation of puddles and voids in the subsequent process due to the application of the SEG method can be prevented.

Hereinafter, a manufacturing process of the semiconductor device having the above-described structure will be described.

5A to 5E are cross-sectional views illustrating a plug forming process of a semiconductor device according to an embodiment of the present invention.

First, as shown in FIG. 5A, a predetermined conductive layer pattern is formed on a substrate 50 on which various elements for forming a semiconductor element such as the conductive region 51 are formed. The conductive layer pattern includes a bit line pattern, Metal wiring or a gate electrode pattern.

The gate insulating film (not shown) and the polysilicon, tungsten, tungsten silicide, or the like may be used alone or in combination to form a conductive layer and a nitride-based hard mask A gate electrode pattern having a structure in which a conductive layer 58 and a hard mask 58 are laminated is formed by performing a photolithography process using a mask for forming a gate electrode pattern.

Then, the etching stopper film 54 is thinly deposited along the profile in which the conductive layer pattern is formed.

The etch stop layer 54 prevents the loss of the conductive layer pattern during the subsequent self alignment contact (SAC) etch process and secures the etch selectivity with the insulating layer, It is desirable to use series.

Subsequently, the insulating film 55 is deposited so as to sufficiently fill the space between the gate electrodes.

The insulating film 55 may be formed of a BPSG (Boro Phospho Silicate Glass) film, a BSG (Boro Silicate Glass) film, a PSG (Phospho Silicate Glass) film, an HDP (High Density Plasma) Or an APL (Advanced Planarization Layer) film.

Then, as shown in Fig. 5B, the contact hole 56 is formed in the conductive region 51 between the conductive layer patterns through the SAC etching process.

Specifically, a photoresist pattern (not shown) for the SAC etching process is formed, and then the insulating film 55 and the etching stopper film 54 are sequentially etched using the photoresist pattern as an etching mask to form conductive regions (51) is exposed.

The above-described SAC etching process uses a plasma containing a recipe, that is, a CF series gas, used in a conventional SAC etching process.

Next, as shown in FIG. 5C, the silicon epitaxial layer 57 is grown by applying the SEG method on the exposed silicon substrate 50 in accordance with the formation of the contact hole 56, specifically, on the conductive region 51.

Specifically, a PH ₃ / H ₂ partial pressure ratio (0.4-0.8) of DCS (SiH ₂ Cl ₂ ) / HCl / H ₂ gas was formed at a temperature of 800 ° C. to 1000 ° C. and a pressure of 10 Torr to 200 Torr, The silicon epitaxial layer 57 is grown from the conductive region 51. At this time, the growth thickness of the silicon epitaxial layer 57 may be a thickness capable of forming a contact with the conductive region 51 on the bottom surface of the contact hole 56. For example, to a thickness of about 500 Å to 3000 Å.

Then, as shown in FIG. 5D, a tungsten film 58 'is deposited on the entire surface of the silicon epitaxial layer 57 where the silicon epitaxial layer 57 is grown, so that the contact hole 56 partially filled with the tungsten film 58 can be sufficiently filled .

Next, as shown in FIG. 5E, the tungsten film 58 'and the insulating film 55 are polished by a CMP process using the abrasive target to which the hard mask 53 is exposed, so that the adjacent plugs are isolated from each other (isolated) A plug having a structure in which a silicon epitaxial layer 57 and a tungsten film 58 are laminated is formed.

Although the plug is planarized with the hard mask 58, the plug may be planarized so that a part of the insulating film 55 remains on the hard mask 58.

On the other hand, a barrier film may be additionally formed between the silicon epitaxial layer 57 and the tungsten film 58. At this time, a TiN film, a TaN film, a TaW film, or a TiW film is used as the barrier film, and it is preferable that the thickness is 100 Å to 1000 Å.

In the present invention as described above, a silicon epitaxial layer is formed by a SEG process on a portion of a lower portion which is in contact with a silicon substrate when a plug is formed, and a highly conductive material such as tungsten, By forming a plug in which an epi layer and a tungsten film are stacked, it is possible to suppress the generation of puddles and pores and to lower the resistance in the course of the subsequent process.                     

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. In addition, it will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention as described above can reduce the resistance of the plug and prevent the occurrence of defects in the subsequent process, and ultimately, an excellent effect of improving the yield of semiconductor devices can be expected.

Claims (6)

A plurality of conductive layer patterns disposed on a silicon substrate and adjacent to each other; A silicon epi layer which is contacted with the silicon substrate between the conductive layer patterns and is formed at a height lower than the height of the conductive layer pattern from the silicon substrate; And A tungsten film formed on the silicon epi layer and stacked with the silicon epi layer to a height of the conductive layer pattern, ≪ / RTI > The method according to claim 1, Wherein the silicon epitaxial layer has a thickness of 500 ANGSTROM to 3000 ANGSTROM. The method according to claim 1, Wherein the conductive layer pattern is any one of a gate electrode pattern, a bit line pattern, and a metal wiring pattern. Forming a plurality of neighboring conductive layer patterns disposed on a silicon substrate; Forming an insulating film on the entire surface of the conductive layer pattern; Forming a photoresist pattern for forming a contact hole between the conductive layer patterns on the insulating film; Etching the insulating film using the photoresist pattern as an etching mask to form a contact hole exposing the silicon substrate; Forming a silicon epitaxial layer in contact with the exposed silicon substrate through the contact hole and having a height lower than the height of the conductive layer pattern from the silicon substrate; Depositing a tungsten film on the silicon epilayer; And Polishing the tungsten film through a chemical mechanical polishing process to form a plug in which the silicon epilayer and the tungsten film are stacked ≪ / RTI > 5. The method of claim 4, Wherein the silicon epitaxial layer is formed to a thickness of 500 to 3000 ANGSTROM. 5. The method of claim 4, In the step of forming the silicon epi layer, (PH ₃ / H ₂ partial pressure ratio (0.4-0.8) of DCS (SiH ₂ Cl ₂ ) / HCl / H ₂ gas at a temperature of 800 ° C. to 1000 ° C. and a pressure of 10 Torr to 200 Torr) Wherein a silicon epitaxial layer is grown.

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