KR100445063B1 - Formation method for capacitor in semiconductor device - Google Patents

Abstract

The present invention relates to a method for forming a capacitor of a semiconductor device, the method comprising: forming a nitride film spacer on an inner sidewall of a storage node contact hole, depositing a plug polysilicon to a thickness such that the inside of the storage node contact hole is buried, a capacitor structure Forming a capacitor structure by forming and etching an oxide film for formation, sequentially depositing a polycrystalline polysilicon doping layer and amorphous silicon in-situ for forming a lower electrode on the oxide film including the capacitor structure, the amorphous silicon and Chemically mechanically polishing the polycrystalline polysilicon doped layer to form a lower electrode of the capacitor, forming and doping hemispherical silicon grains in the lower electrode, and a dielectric layer on the lower electrode on which the hemispherical silicon grains are formed. Forming upper electrodes in sequence Including a step, the present invention increases the leakage current due to the breakage of the hemispherical silicon grain or double bit failure by bridge formation, the bridge phenomenon due to the growth of the hemispherical silicon grain seed on the top surface of the storage node and yield of self-aligned contact This deterioration problem can be solved, process margin can be secured and yield improvement can be expected.

Description

FORMATION METHOD FOR CAPACITOR IN SEMICONDUCTOR DEVICE

The present invention relates to a method of forming a capacitor of a semiconductor device, in particular, a method of forming a capacitor having a convex structure that can be used for memory storage of a next-generation semiconductor product to which a fine circuit line width technology of 0.16 μm or less is applied.

The method of forming the lower electrode of the conventional capacitor can be largely divided into the following two methods.

The first method is to deposit polysilicon for the lower electrode of the capacitor, and then grow hemisphere spherical grain polysilicon or meta-stable polysilicon on polysilicon to increase the surface area of the charge storage electrode, followed by chemical mechanical polishing. Mechanical Polishing (CMP) is a method for completing the lower electrode of the memory cell. However, in this method, since chemical mechanical polishing is performed while hemispherical silicon grains are formed, the hemispherical silicon grains are easily broken by chemical mechanical polishing, and the broken grains are not completely removed in the subsequent wet cleaning process. If not removed in this state, the subsequent step coverage of the subsequent chemical vapor deposition film (capacitor dielectric film and upper electrode) may be reduced to increase the leakage current of the capacitor, or may be embedded between the storage node and the node. There is a problem of causing a dual bit fail by forming a bridge.

The second method is a method of depositing a storage node polysilicon, which is a lower electrode, followed by chemical mechanical polishing, and then growing a hemispherical silicon grain on polysilicon for increasing surface area to complete a charge storage electrode. This method can prevent the breakage of hemispherical silicon grains by chemical mechanical polishing as described above, but as shown in the accompanying CD-SEM photograph of FIG. Hemispherical silicon grain seeds (SiH ₄ or Si ₂ H ₆ ) are partially grown on the top surface of the node polysilicon. As a result, when the space between the storage node and the node becomes narrow or severe, there is a problem that a bridge between nodes is formed and also causes a double bit failure.

In order to solve the above problems, when the method of forming a lower electrode using a photo-resist coated hard mask poly etch-back and a storage node poly etch process, Although the disadvantages of the two methods can be solved, it is difficult to form a wide pattern that can measure the thickness during the process, it is difficult to monitor on the lot (lot) has a problem that efficient process management is difficult.

In addition, in the storage node contact and plug poly formation, there is a problem that the lower electrode area is actually reduced because the plug poly rises about 100 μs over the barrier nitride layer, and there is no process margin when a misalignment occurs in the storage electrode mask process. In the etching process, there was a problem that bridges could occur between adjacent contact plugs and storage nodes. In addition, when a misalignment occurs in the contact mask process when forming the storage node contact, a leakage current occurs between the bit line and the storage node contact, thereby lowering the self-aligned contact yield.

Disclosure of Invention The present invention has been made in view of the above-described problems of the related art, and an object thereof is to provide a method of forming a capacitor to prevent leakage current between a bit line and a storage node contact and to prevent a bridge between lower electrodes. have.

FIG. 1A is a SEM photograph showing a phenomenon in which a space between storage is narrowed due to growth of polysilicon on a storage node when forming a hemispherical silicon grain in forming a capacitor according to the prior art.

Figure 1b is a SEM photograph showing that in the formation of the capacitor according to the present invention, the growth of polysilicon on the top of the storage node during the formation of hemispherical silicon grains is suppressed.

2A to 2G are cross-sectional views illustrating a manufacturing process of a capacitor according to the present invention.

Explanation of symbols of main parts of drawings

200: substrate 210: bit line

220: hard mask

230: oxide film or nitride film spacer

240: interlayer dielectrics (ILD2)

250: storage node contact spacer

260: plug poly

270: barrier spacer

280: oxide film for forming the capacitor

290: polysilicon for lower electrode

300: hemispherical silicon grain (Hemi Spherical Grain or Meta-Stable Polysilicon)

310: upper electrode

According to an aspect of the present invention, there is provided a method of forming a capacitor of a semiconductor device, the method comprising: forming an oxide layer on a semiconductor substrate on which a bit line is formed, selectively etching the oxide layer to form a storage node contact hole in an area where a capacitor between the bit lines is to be formed Forming a nitride film spacer on an inner sidewall of the storage node contact hole; depositing a plug polysilicon to a thickness such that the inside of the storage node contact hole is embedded; and depositing a plug polysilicon on the front surface of the capacitor including the plug polysilicon. Forming a nitride film barrier for etching the oxide film for forming, forming and etching an oxide film for forming a capacitor structure on the nitride film barrier, and forming a capacitor structure; forming a lower electrode on the oxide film including the capacitor structure Polycrystalline polysilicon doping layer for Depositing amorphous silicon in-situ in sequence, chemical mechanical polishing of the amorphous silicon and the polycrystalline polysilicon doping layer to form a lower electrode of the capacitor, and forming and doping hemispherical silicon grains in the lower electrode And forming a dielectric layer and an upper electrode in sequence on the lower electrode on which the hemispherical silicon grains are formed.

In the method of forming the capacitor, the thickness of the nitride film spacer is preferably 200 μs or less, and the formation of the plug polysilicon is performed using a low pressure chemical vapor deposition method or a rapid thermal process using doped polysilicon having a phosphorus concentration of 2E20 atoms / cc or more. It is desirable to. In addition, the thickness of the nitride film barrier is preferably 200 to 800 GPa, and the thickness of the oxide film for forming the capacitor structure is preferably 12,000 GPa or more. It is also preferable to deposit the polycrystalline silicon doped layer at 560 to 620 ° C., and then deposit the amorphous silicon layer at a temperature of 480 to 550 ° C. in-situ, wherein the deposition of the polycrystalline silicon doped layer is SiH ₄ gas or inert. Injecting SiH ₄ gas diluted in the gas as a raw material gas at 500 to 2000sccm, PH ₃ gas diluted in He or N ₂ at 100 ~ 800sccm with a dopant, and the amorphous silicon layer is Si It is preferable to deposit each containing gas as source gas. In addition, the dielectric layer is preferably TaON or Ta ₂ O ₅ , the upper electrode is preferably at least one selected from TiN, TaN, W, WSi, Ru, Ir, Pt.

Hereinafter, a manufacturing method according to an embodiment of the present invention will be described with reference to the accompanying drawings.

Example

As shown in FIG. 2A, an interlayer insulating layer (ILD2) 240 is first formed on the semiconductor substrate 200 on which the lower structure including the bit line 210, the bit line hard mask 220, and the bit line nitride film spacer 230 is formed. Deposited. Thereafter, as shown in FIG. 2B, the storage node contact hole was formed through the contact mask process and the contact etching process. The contact etching was performed by dry etching, and overetched by about 30%.

Thereafter, after the nitride film 250 was deposited as shown in FIG. 2B, the nitride spacer 250 was formed on the sidewall of the contact hole through the front etch back (FIG. 2C), and then reverse etching was performed. . Afterwards a plug polysilicon 260 was deposited (FIG. 2D). As the polysilicon 260 for the plug, a doped polysilicon having a phosphorus concentration of 2E + 20 atoms / cc or more was deposited using a low pressure chemical machine deposition or a rapid thermal process (RTP) apparatus.

Thereafter, a nitride barrier 270 for etching termination of the oxide layer 280 for capacitor formation was deposited (FIG. 2E). Since the nitride barrier 270 should act as a barrier during dry and wet etching of the oxide layer, the nitride barrier 270 was deposited to a thickness of 200 to 800 Pa using low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, or rapid heat treatment equipment.

Thereafter, an oxide film 280 was formed to form a capacitor (FIG. 2F). The oxide 280 for capacitor formation was deposited to a desired thickness using a PE-TEOS or PSG oxide film. In general, when a wiring process of 0.16 μm or less is applied, a charge required to obtain a capacitance of 25 fF / cell or more In order to secure the area of a storage electrode, it is preferable to deposit at 12,000 GPa or more. Thereafter, the oxide layer 280 and the nitride barrier 270 were etched using the cell mask to form an internal structure of the capacitor. In the etching of the oxide film 280, the etching selectivity ratio of the oxide film to the nitride film was 5 to 20: 1 in order to use the nitride film as a barrier. Since the nitride film barrier 270 is over-etched by 10 to 50% to fully open the surface of the plug polysilicon 260. After etching the nitride film barrier 270, the contaminant impurities on the surface of the plug polysilicon 260 are completely removed once again to prevent an increase in contact interface resistance between the lower electrode poly and the plug polysilicon 260. It was lightly etched dry using an O ₂ plasma.

Then, polysilicon 290 for lower electrodes was formed on the inner sidewall of the capacitor as a double thin film of polycrystalline silicon and amorphous silicon. First, under a pressure of the temperature, and 0.2 ~ 1.5 Torr or less than 560 ℃ 650 ℃, SiH ₄ of 500 to 2000sccm injection to the SiH ₄ gas diluted with gas or inert gas as a source gas, diluted in He or N ₂ PH Polycrystalline silicon was deposited using ₃ gases as a dopant in a ratio of 100-800 sccm. Further, after depositing polycrystalline silicon, amorphous silicon was deposited using a gas such as SiH ₄ or Si ₂ H ₆ containing Si at a temperature of 480 ° C. or higher and 550 ° C. or lower and a pressure of 0.5 to 1.5 Torr.

After the photoresist was coated, the polysilicon 290 for lower electrodes was chemically mechanically polished and the porter resist was removed. At this time, the photoresist was coated to a thickness of 0.5 ~ 1.5㎛, the chemical mechanical polishing was carried out while maintaining a pH of 6 to 11 using an abrasive such as silica, alumina, ceria having a size of 50 ~ 300nm.

Then, hemispherical silicon grains 300 were formed in the storage node and then doped. The doping was performed immediately after formation of the hemispherical polysilicon while maintaining a constant pressure in the range of 1 to 100 Torr in a furnace for 30 to 120 minutes at 600 ± 50 ° C. under a phosphorous gas atmosphere. The doping is not based on a heat treatment method, and may be a method of doping by discharging the plasma (RF = 100 ~ 500W) for 30 to 120 seconds in an atmosphere of pH 3 in the sheet-type chamber, 750 using a rapid heat treatment process Doping by using radiant heat for 30 to 120 seconds in a pH 3 atmosphere in the temperature range of ~ 950 ℃.

In order to maximize the doping effect by removing impurities and natural oxide films including organic components or metal components on the surface of the hemispherical silicon grain 300 on the lower electrode, the cleaning solution containing a hydrofluoric acid solution is first washed with sulfuric acid solution before doping treatment. It was subjected to a wet cleaning treatment to remove impurities and natural oxide film by secondary cleaning.

Then, a TaON or Ta ₂ O ₅ dielectric film is deposited on the lower electrode, and then the upper electrode 310 is formed of a metal such as TaN, W, WSi, Ru, Ir, Pt, or the like, to form a capacitor as shown in FIG. 2G. Completed.

Then, dopant polysilicon may be stacked as a buffer layer to secure structural stability on the upper electrode and to improve durability of the upper electrode against thermal or electrical shock.

The present invention is not limited by the above embodiments, and various modifications are possible in the range including the elements of the claims.

The present invention having the configuration as described above has the following effects.

First, after the planarization of the interlayer insulating film, the nitride spacer (200 Å or less) is formed before the deposition of the plug poly. After the plug poly is deposited, the front poly back etching is performed to form the poly plug of the lower electrode. As a result, leakage current is generated between the bit line and the storage node contact, and the yield of the self-aligned contact can be overcome. Thus, a process margin can be secured and a yield improvement can be expected.

Second, after the chemical mechanical polishing process, the present invention grows the hemispherical silicon grains for increasing the area of the lower electrode so that the hemispherical silicon grains are broken and the broken grains are not completely cleaned in the subsequent wet cleaning process. It can be fundamentally prevented from being embedded inside, resulting in poor step coverage of subsequent chemical vapor deposition films (capacitor dielectric film and upper electrode), thereby increasing leakage current or forming bridges, resulting in electrical failures such as double bit failures. .

Third, the present invention inhibits partial growth of hemispherical silicon grain seeds on polycrystalline polysilicon, which is the uppermost surface of the lower electrode, thereby preventing the bridge phenomenon between adjacent lower electrodes.

Claims (11)

In the capacitor forming method of a semiconductor device, Forming an oxide film on the semiconductor substrate on which the bit lines are formed; Selectively etching the oxide layer to form a storage node contact hole in an area where a capacitor between the bit lines is to be formed; Forming a nitride spacer on an inner sidewall of the storage node contact hole; Depositing plug polysilicon to a thickness such that an interior of the storage node contact hole is buried; Forming a nitride barrier barrier for etching the oxide layer to form a capacitor structure on the entire surface including the plug polysilicon; Forming a capacitor structure by forming and etching an oxide film for forming a capacitor structure on the nitride film barrier; Sequentially depositing a polycrystalline polysilicon doped layer and amorphous silicon for forming a lower electrode on an oxide film including the capacitor structure in situ; Chemical mechanical polishing the amorphous silicon and the polycrystalline polysilicon doped layer to form a lower electrode of the capacitor; Forming and doping hemispherical silicon grains in the lower electrode; And Sequentially forming a dielectric layer and an upper electrode on the lower electrode on which the hemispherical silicon grains are formed Concave-type capacitor forming method of a semiconductor device comprising a. The method of claim 1, And depositing the polycrystalline silicon doped layer at 560 ° C. to 620 ° C., and then depositing the amorphous silicon at a temperature of 480 ° C. to 550 ° C. in-situ. The method of claim 2, Deposition of the doped polysilicon layer SiH ₄ gas or to the SiH ₄ gas diluted with an inert gas as a raw material gas was charged with 500 to 2000sccm, injected into 100~800sccm the PH ₃ gas diluted with He or N ₂ as a dopant Concave-type capacitor forming method of a semiconductor device, characterized in that consisting of. The method of claim 2, And forming the amorphous silicon layer using a Si-containing gas as a source gas. The method of claim 1, And a thickness of the nitride film spacer is less than 200 GPa. The method of claim 1, The plug polysilicon is formed using a doped polysilicon having a phosphorus concentration of 2E20 atoms / cc or more, and a low pressure chemical vapor deposition method or a rapid heat treatment method is used to form a concave capacitor of a semiconductor device. The method of claim 1, And a thickness of the nitride film barrier is 200 to 800 kHz. The method of claim 1, The thickness of the oxide film for forming the capacitor structure is a convex capacitor forming method of a semiconductor device, characterized in that more than 12,000 1. The method of claim 1, And the dielectric layer is TaON or Ta ₂ O ₅ . The method of claim 1, And the upper electrode is at least one selected from TiN, TaN, W, WSi, Ru, Ir, and Pt. delete