JP3408451B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method, and more particularly to a dynamic semiconductor memory device (hereinafter
And a method of forming a lower electrode of a memory stack capacitor (described as DRAM).

[0002]

2. Description of the Related Art As semiconductor devices become highly integrated, DRAM
The cell size is decreasing and the capacitor area is becoming smaller and smaller, so that a three-dimensional structure (three-dimensional structure) is unavoidable in order to secure a sufficient capacity of the capacitor. Therefore, various capacitor structures have been considered. As such a capacitor structure, there are a fin type structure and a crown structure. In addition, a method of increasing the surface area of the capacitor electrode by forming unevenness of polysilicon on the surface of the storage node that constitutes the capacitor electrode made of a polysilicon film has also been devised. At this time, the uneven polysilicon is changed to a rough poly or HS from its surface state.
G-Si (Hemi Spherical Grain-
Silicon).

FIG. 3 is a structural sectional view of a capacitor lower electrode of a conventional DRAM and its vicinity. In FIG. 3, 1 is a substrate, 2 is an element isolation region, 3 is an interlayer insulating film formed on the substrate 1, 4 is a bit line, 5 is a word line, and 6 is a capacitor connection hole for connecting a substrate and a capacitor. , 7 is a stack capacitor lower electrode made of polysilicon, 7a is a hemispherical polyconic uneven crystal (referred to as HSG-Si) formed to increase the surface area of the lower electrode, and 8 is a stack capacitor lower electrode and HSG-Si 7a. A stacked capacitor upper electrode made of polysilicon formed on the upper dielectric film (not shown).

A conventional method for manufacturing a DRAM capacitor will be described with reference to FIG. First, after forming the element isolation region 2 on the substrate 1, the word line 5 is formed by polycide or the like. Then, BPSG (bor
onphosphosili-cate Glass)
After depositing an oxide film such as that having a thickness of 500 to 600 nm, after heat treatment, the surface is flattened by wet etching or CMP polishing to form an interlayer insulating film 3a. After that, an opening is formed in the interlayer insulating film 3a by anisotropic dry etching for connecting the bit line, polysilicon is deposited on the opening and the interlayer insulating film 3b, and the bit line 4 is patterned using the photolithography technique. To do. A polycide film is used for the bit line 4.

Next, an interlayer insulating film 3 made of an oxide film such as BPSG.
After b is deposited to a thickness of 500 to 600 nm, a chemical mechanical polishing method (hereinafter referred to as CMP (Chemical-Mechanic) is used.
inter-layer insulating film 3 by the al-polishing method)
The surface of b is flattened, and the capacitor connection hole 6 penetrating the interlayer insulating films 3a and 3b by photolithography is used.
To form.

Next, an amorphous silicon film (not shown) in which impurities such as phosphorus are implanted is deposited on the interlayer insulating film 3b including the capacitor connection hole 6 by the CVD method, and the lithography technique is used. The amorphous silicon film is etched by a chlorine-based dry etching method to form a stack node lower electrode 7 of a storage node.

Next, the substrate 1 is subjected to heat treatment at 750 ° C. to 800 ° C. for about 60 minutes in a dilute disilane (Si ₂ H ₆ ) atmosphere, so that the amorphous silicon film of the lower electrode 7 of the stacked capacitor is formed. Is crystallized into a polysilicon film, and HSG-Si 7a is formed on the surface of the stack capacitor lower electrode 7 in the process. This H
The lower electrode 7 of the stack capacitor is formed by SG-Si7a.
The surface area of the capacitor can be increased, and the capacitance of the capacitor can be increased.

[0008]

However, in the above-described method for manufacturing a semiconductor device, in the roughening treatment step of the surface of the lower electrode 7a of the stack capacitor, the disilane gas, which is the raw material of the silicon thin film, is diluted but at a high temperature. Since it is exposed below, a polysilicon film may be formed on the entire surface of the interlayer insulating film 3b. Also, HS
The G-Si 7a also grows on the side surface of the stack capacitor lower electrode 7, and the non-uniformly-formed polysilicon deposit on the interlayer insulating film 3b between the adjacent stack capacitor lower electrodes 7 is the adjacent stack capacitor lower electrode 7. There is a problem in that the semiconductor device is short-circuited and the reliability of the semiconductor device is reduced.

With the thinning of the stack capacitor lower electrodes, the distance between the stack capacitor lower electrodes has been reduced, and the HSG-Si grown on the side surface of the stack capacitor lower electrode 7 causes a short circuit between the stack capacitor lower electrodes 7. There is a problem that causes it.

A method for preventing a short circuit due to HSG-Si in the lower electrode of the stack capacitor in the prior art as described above is disclosed in JP-A-8-298309 and JP-A-9-167833.

In these publications, a capacitor electrode made of an amorphous silicon film is formed on a substrate, the amorphous silicon film is heat-treated, and HSG-Si is formed on the surface of the capacitor electrode by crystal growth by this heat treatment. The surface is heat-treated in a halogen-based gas atmosphere. When this capacitor electrode is heat-treated in a halogen-based gas atmosphere, polysilicon is thermochemically etched. However, since the etching rate is locally large in the grain boundary, the HSG- on the surface of the capacitor electrode is The unevenness of Si is increased, and at the same time, a deposit made of polysilicon formed on an unnecessary portion of the interlayer insulating film is also thermochemically etched to improve the insulation between the capacitor electrodes. is there.

In this case, a short circuit can be prevented immediately after the HSG-Si is formed, but the HSG is formed by the cleaning process before the capacitive insulating film such as the nitride film is formed on the lower electrode of the stack capacitor.
-Si grains are locally peeled off, and the peeled grains have an interval of 0.0.
There is a problem in that the gap between the capacitor lower electrodes adjacent to each other is 2 to 0.06 μm and the capacitor lower electrodes are short-circuited.

[0013]

A first structure of a method of manufacturing a semiconductor device according to the present invention comprises a step of forming an interlayer insulating film on a semiconductor substrate and a connection penetrating the interlayer insulating film to the surface of the semiconductor substrate. Forming a hole, depositing a first conductive film made of an N + amorphous silicon film on the interlayer insulating film, and simultaneously filling the connection hole with the first conductive film; Patterning the conductive film to form a stack capacitor lower electrode, depositing an insulating oxide film covering the stack capacitor lower electrode on the interlayer insulating film, polishing the insulating oxide film, and stacking the insulating film. A step of flattening so as to have the same height as the upper surface of the lower electrode; a step of forming an uneven surface made of polysilicon on the surface of the lower electrode of the stack capacitor by heat treatment ; A step of forming a capacitive insulating film on the top,
Depositing a second conductive film on the capacitive insulating film, and patterning the second conductive film to form a stack capacitor upper electrode.

A second structure of the method for manufacturing a semiconductor device of the present invention comprises the steps of forming an interlayer insulating film on a semiconductor substrate, and forming a connection hole penetrating to the surface of the semiconductor substrate in the interlayer insulating film. A step of filling the connection hole with a third conductive film to form a connection plug, a step of depositing an insulating oxide film on the interlayer insulating film including the upper surface of the connection plug, and a predetermined position of the insulating oxide film. Forming a recess reaching the surface of the interlayer insulating film, and exposing the upper surface of the connection plug in the recess; and forming a fourth conductive film made of an N ⁺ amorphous silicon film in the recess on the upper surface of the recess. A step of forming a stack capacitor lower electrode by depositing at the same height as, and a step of forming an uneven surface made of polysilicon on the surface of the stack capacitor lower electrode by heat treatment,
Forming a capacitor insulating film on the uneven surface, and then depositing and patterning a second conductive film on the capacitor insulating film to form a stack capacitor upper electrode.

In the present invention, an uneven surface (HSG-Si) made of polysilicon is formed on the lower electrode of the stack capacitor.
(Hemispheral Grain Sili
(referred to as “con”) is formed, since the side surface of the lower electrode of the stack capacitor is buried in the insulating oxide film, the HSG-Si on the side surface of the lower electrode of the stack capacitor is formed.
Can be prevented and the reliability of the electrical insulation between the lower electrodes of the stack capacitor can be improved.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Next, a first embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is an enlarged cross-sectional view of a capacitor formation main part of a DRAM semiconductor device for explaining the steps of the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

First, 3 is formed on the surface of the substrate 1 such as P-type silicon.
An element isolation region 2 of a LOCOS type field oxide film of about 00 nm is formed. Then, the N ⁺ polysilicon film of about 100 nm is covered with a tungsten polycide film of a tungsten silicide multilayer film of about 100 nm, and the word line 5 is formed by photolithography using anisotropic etching such as reactive ion etching (RIE). Pattern.

Next, TEOS (tetraethoxysilane: S
i (OC ₂ H ₅ ) ₄ ), TMP (trimethyl phosphate: PO (OCH ₃ ) ₃ ), TMB (trimethyl borate: B (OCH ₃ ) ₃ ) and ozone as raw materials 350
An interlayer insulating film 3a of a BPSG film having a thickness of 500 to 600 nm is deposited by an atmospheric pressure CVD method at -400 ° C. After film formation, baking is performed at 700 ° C. for 20 minutes. Then, a wet etching method using buffered hydrofluoric acid or a CMP method is used to flatten the thickness to 200 nm.

Next, a bit contact hole (not shown in the figure) for connecting the bit line 4 is formed in the interlayer insulating film 3a by photolithography using anisotropic etching such as RIE, and then an N ⁺ polysilicon film is formed. While filling the bit contact hole, a 100 nm thick N film is formed on the interlayer insulating film 3a.
⁺ Deposit polysilicon film. After a tungsten silicide film of about 100 nm is deposited thereon to form a tungsten polycide film, reactive ion etching (R
The bit line 4 is patterned by photolithography using anisotropic etching such as IE).

Then, an interlayer insulating film 3b of a BPSG film is deposited to a thickness of 500 to 600 nm on the interlayer insulating film 3a including the bit lines 4 by the same method as the formation of the interlayer insulating film 3a, and 700
After heat treatment at 20 ° C. for 20 minutes, the interlayer insulating film 3b is wet-etched using buffered hydrofluoric acid (HF) or C
It is flattened to a thickness of 200 nm by the MP method.

Next, the interlayer insulating films 3a and 3b are formed by a photolithography technique using anisotropic etching such as RIE.
Capacitor connection hole 6 for penetrating the substrate and connecting to the substrate 1
Then, a N ⁺ amorphous silicon film (see the figure) is formed by a low pressure CVD method using disilane and phosphine (PH ₃ ) as raw materials at 500 ° C. to 550 ° C. (Not specified) is formed on the entire surface. This amorphous silicon film is patterned by a photolithography technique using anisotropic dry etching such as RIE to form a stack capacitor lower electrode 7 made of an amorphous silicon film. Amorphous silicon is also filled in the capacitor connecting hole 6 (see FIG. 1A for the above).

Prior to the above-mentioned coating of the amorphous silicon film, the capacitor connecting hole 6 is filled with a non-silicon based conductive film (for example, a tungsten film) to form a contact plug, and then the amorphous silicon film is deposited. Patterning may be performed to form the lower electrode 7 of the stack capacitor.

Next, SiO of 500 nm to 1000 nm is used.
_{After the two} insulating oxide films 9 are deposited, they are planarized by CMP until the surface of the lower electrode of the stack capacitor is exposed.
The insulating oxide film 9 is formed by using silane gas (monosilane) and oxygen gas as raw materials at 350 to 400 ° C.
Atmospheric pressure CVD method can be used.

Then, after removing the natural oxide film on the surface of the stack capacitor electrode 7 with diluted hydrofluoric acid, SiH ₄ gas is added to
The amorphous silicon of the stack capacitor lower electrode 7 is changed into an N-type polysilicon film by heat treatment at 560 ° C. for 30 minutes with a 5 SCCM flow CVD apparatus, and the upper surface of the stack capacitor lower electrode 7 is converted into HSG. HSG-Si 7a of uneven polysilicon crystal is formed on the upper surface of the stack capacitor lower electrode 7 (see FIG. 1B).
reference).

Next, a 1 nm SiO ₂ film is formed on the entire surface by lamp annealing at 870 ° C. for 60 seconds, and then the entire surface is formed by low pressure CVD at 650 ° C. using monosilane and ammonia (NH ₃ ) as raw materials. After forming a silicon nitride film (not shown) with a thickness of 8 nm on the surface, oxygen and hydrogen (H ₂ )
And are maintained in a burning atmosphere burned at 800 to 850 ° C. for 30 minutes to form an oxide film (1 nm or less) on the surface of the silicon nitride film, and a capacity composed of three layers of SiO ₂ / nitride film / SiO ₂ An insulating film (not shown in the figure) is formed.

Subsequently, an N-type polycrystalline silicon film having a film thickness of about 100 nm is formed on the entire surface by a low pressure CVD method using disilane and phosphine as raw materials, and further RTA is performed at 800 ° C. for about 10 seconds. The stacked capacitor upper electrode 8 is formed, and the capacitor of the present invention is formed (see FIG. 1C for the above).

In FIG. 1B, since the side surface of the stack capacitor lower electrode is filled with the insulating oxide film 9, HSG-Si is prevented from growing on the side surface of the stack capacitor lower electrode.

Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 2 is an enlarged cross-sectional view of the capacitor portion of the DRAM semiconductor device for explaining the method of manufacturing the semiconductor device according to the second embodiment of the present invention.

First, 3 is formed on the surface of the substrate 1 such as P-type silicon.
An element isolation region 2 of a LOCOS type field oxide film of about 00 nm is formed. Then, the N ⁺ polysilicon film of about 100 nm is covered with a tungsten polycide film of a tungsten silicide multilayer film of about 100 nm, and the word line 5 is formed by photolithography using anisotropic etching such as reactive ion etching (RIE). Pattern.

Next, TEOS (tetraethoxysilane: S
i (OC ₂ H 5) ₄ ), TMP (trimethyl phosphate: PO (OCH ₃ ) ₃ ), TMB (trimethyl borate: B (OCH ₃ ) ₃ ) and ozone as raw materials 350
An interlayer insulating film 3a of a BPSG film having a thickness of 500 to 600 nm is deposited by an atmospheric pressure CVD method at -400 ° C. After film formation, baking is performed at 700 ° C. for 20 minutes. Then, using a wet etching method or a CMP method, it is flattened to a thickness of 200 nm.

Next, a bit contact hole (not shown in the figure) for connecting the bit line 4 is formed in the interlayer insulating film 3a by photolithography using anisotropic etching such as RIE, and then an N ⁺ polysilicon film is formed. The bit contact hole is filled and a thickness of 100 nm is deposited on the interlayer insulating film 3a. After depositing tungsten silicide of about 100 nm thereon to form a tungsten polycide film, the bit line 4 is formed by photolithography using anisotropic etching such as reactive ion etching (RIE).
Pattern.

Then, an interlayer insulating film 3b of a BPSG film is deposited to a thickness of 500 to 600 nm on the interlayer insulating film 3a including the bit lines 4 by the same method as the formation of the interlayer insulating film 3a, and 700
After heat treatment at ℃ for 20 minutes, wet etch back to 20
Planarize to a thickness of 0 nm.

Next, the interlayer insulating films 3a and 3b are formed by a photolithography technique using anisotropic etching such as RIE.
After forming a capacitor connecting hole for penetrating through the substrate and connecting to the substrate 1, a conductive film (for example, tungsten (W)) for filling the capacitor connecting hole is deposited on the interlayer insulating film 3b,
The conductive film other than the capacitor connecting hole is removed by photolithography to form the capacitor connecting plug 6a (see FIG. 2A above).

Next, after depositing an insulating oxide film 9 of a silicon oxide film (SiO ₂ film) of 500 nm to 600 nm by the atmospheric pressure CVD method similar to that of the first embodiment, CMP is performed.
After planarizing the surface of the insulating oxide film 9 by the method, the insulating oxide film 9 is anisotropically etched by photolithography to form a recess for forming the lower electrode of the stack capacitor. In this etching, the upper surface of the capacitor connecting plug is also exposed at the same time (see FIG. 2B). Unlike the first embodiment, the stack capacitor lower electrode is not patterned on the interlayer insulating film 3b on which the insulating oxide film 9 is deposited. Therefore, in this embodiment, the insulating oxide film 9 is formed. Has the effect of reducing the thickness of the.

Next, disilane and phosphine (PH ₃ )
After forming an N ⁺ amorphous silicon film (not shown in the figure) on the entire surface by a low pressure CVD method at 500 ° C. to 550 ° C. using and as raw materials, a film thickness of about 600 nm is formed.
The stacked capacitor lower electrode 7 is formed by polishing until the surface of the insulating oxide film 9 is exposed and planarized.

Next, after removing the natural oxide film on the surface of the stack capacitor electrode 7 with dilute hydrofluoric acid, SiH ₄ gas is added to 75
The amorphous silicon of the stack capacitor lower electrode 7 is changed into an N-type polysilicon film by heat treatment at 560 ° C. for 30 minutes using a SCCM-flowing CVD device, and the upper surface of the stack capacitor lower electrode 7 is made HSG. On the surface of the lower electrode 7 of the stack capacitor, HSG-Si 7a of uneven polysilicon crystal is formed.

Next, a 1 nm SiO ₂ film was formed on the entire surface by lamp annealing at 870 ° C. for 60 seconds, and then the entire surface was formed by a low pressure CVD method at 650 ° C. using monosilane and ammonia (NH ₃ ) as raw materials. After forming a silicon nitride film (not shown) with a thickness of 8 nm on the surface, oxygen and hydrogen (H ₂ )
And are maintained in a burning atmosphere burned at 800 to 850 ° C. for 30 minutes to form an oxide film (1 nm or less) on the surface of the silicon nitride film, and a capacity composed of three layers of SiO ₂ / nitride film / SiO ₂ An insulating film (not shown in the figure) is formed.

Subsequently, an N-type polycrystalline silicon film having a film thickness of about 100 nm is formed on the entire surface by a low pressure CVD method using disilane and phosphine as raw materials, and further RTA is performed at 800 ° C. for about 10 seconds. The stack capacitor upper electrode 8 is formed, and the capacitor is formed (see FIG. 2C above).

[0039]

According to the present invention, a stack capacitor is provided.
The lower electrode has an uneven surface made of polysilicon (HSG-Si
(Hemispheral Grain Sili
(con)) is formed.
Since the side surface of the bottom electrode of the shaft is buried in the insulating oxide film
The HSG-Si on the side surface of the lower electrode of the stack capacitor.
Growth can be prevented and the voltage between the lower electrodes of the stack capacitor can be prevented.
The reliability of the air insulation can be improved.

[Brief description of drawings]

FIG. 1 is an enlarged cross-sectional view of a capacitor formation main part of a DRAM semiconductor device for explaining the steps of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is an enlarged cross-sectional view of a capacitor formation main part of a DRAM semiconductor device for explaining the steps of the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

FIG. 3 is a structural cross-sectional view of a capacitor lower electrode of a conventional DRAM and its vicinity.

[Explanation of symbols]

1 substrate 2 element isolation region 3a, 3b Interlayer insulating film 4 bit line 5 word lines 6 Capacitor connection hole 6a Capacitor connection plug 7 Stack capacitor lower electrode 7a HSG-Si 8 Stacked capacitor upper electrode 9 Insulating oxide film

Claims (8)

(57) [Claims] 1. A step of forming an interlayer insulating film on a semiconductor substrate, a step of forming a connection hole penetrating to the surface of the semiconductor substrate in the interlayer insulating film, and N ⁺ on the interlayer insulating film.
Depositing a first conductive film made of an amorphous silicon film and simultaneously filling the connection hole with the first conductive film;
Patterning the first conductive film to form a stack capacitor lower electrode, depositing an insulating oxide film covering the stack capacitor lower electrode on the interlayer insulating film, and polishing the insulating oxide film. A step of flattening so as to have the same height as the top surface of the lower electrode of the stack capacitor; a step of forming an uneven surface made of polysilicon on the surface of the lower electrode of the stack capacitor by heat treatment ; A method of manufacturing a semiconductor device, comprising: a forming step; and a step of depositing a second conductive film on the capacitive insulating film and then patterning the second conductive film to form a stack capacitor upper electrode. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the insulating oxide film is a silicon oxide film. 3. The method of manufacturing a semiconductor device according to claim 1, wherein a chemical mechanical polishing method is used as a method of planarizing the insulating oxide film after depositing the insulating oxide film. 4. The method of manufacturing a semiconductor device according to claim 2, wherein an atmospheric pressure CVD method using silane gas and oxygen gas as raw materials is used as a method of forming the silicon oxide film. 5. A step of forming an interlayer insulating film on a semiconductor substrate, a step of forming a connection hole penetrating to the surface of the semiconductor substrate in the interlayer insulating film, and filling the connection hole with a third conductive film. At the same time as forming a connection plug, depositing an insulating oxide film on the interlayer insulating film including the upper surface of the connecting plug, and forming a recess reaching a surface of the insulating film at a predetermined position of the insulating oxide film. Exposing the upper surface of the connection plug in the recess, and N ^{+ in the} recess.
A step of depositing a fourth conductive film made of an amorphous silicon film at the same height as the upper surface of the recess to form a stack capacitor lower electrode, and an uneven surface made of polysilicon on the surface of the stack capacitor lower electrode by heat treatment. And a step of forming a capacitive insulating film on the concavo-convex surface and then depositing and patterning a second conductive film on the capacitive insulating film to form a stacked capacitor upper electrode. A method for manufacturing a characteristic semiconductor device. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the insulating oxide film is a silicon oxide film. 7. The method of manufacturing a semiconductor device according to claim 6, wherein an atmospheric pressure CVD method using silane gas and oxygen gas as raw materials is used as a method of forming the silicon oxide film. 8. The method of manufacturing a semiconductor device according to claim 5, wherein a tungsten (W) film is used as the third conductive film.