KR20030049159A - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

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KR20030049159A
KR20030049159A KR1020010079297A KR20010079297A KR20030049159A KR 20030049159 A KR20030049159 A KR 20030049159A KR 1020010079297 A KR1020010079297 A KR 1020010079297A KR 20010079297 A KR20010079297 A KR 20010079297A KR 20030049159 A KR20030049159 A KR 20030049159A
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South Korea
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film
insulating film
etch stop
etching
semiconductor device
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KR1020010079297A
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Korean (ko)
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이성권
이민석
서원준
김상익
황창연
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주식회사 하이닉스반도체
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Publication of KR20030049159A publication Critical patent/KR20030049159A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02181—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02189—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing zirconium, e.g. ZrO2

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to be capable of improving etch profile when forming a contact by using an APL(Advanced Planarization Layer). CONSTITUTION: A plurality of conductive patterns are formed on a substrate(10). A nitride-based spacer insulating layer(14,15) and an etch stop layer(16) are sequentially formed on the conductive patterns. A fluidity insulating layer(17), such as an advanced planarization layer, is formed on the etch stop layer(16). By selectively etching the fluidity insulating layer(17), the etch stop layer(16) is exposed. A contact hole(19) is then formed to expose the surface of the substrate(10) by selectively etching the exposed etch stop layer and the spacer insulating layer.

Description

반도체 소자 제조 방법{METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}Semiconductor device manufacturing method {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

본 발명은 반도체 기술에 관한 것으로, 특히 APL(Advanced PlanalizationLayer) 박막을 이용한 반도체 소자 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly, to a method of manufacturing a semiconductor device using an APL (Advanced Planalization Layer) thin film.

0.1㎛ 이하의 선폭을 갖는 반도체 소자 기술에서는 절연산화막의 갭-필(Gap-fill) 특성에 있어서 콘택홀 등의 스페이스가 감소하고 종횡비(Aspect ratio)가 점점 증가함에 따라 완전한 필링(Filling, 채움)이 불가능하여, 보이드(Void)가 생기는 문제점이 발생하는 바, 이러한 문제점을 해결하기 위해 플로우 특성을 갖는 절연막 즉, 유동성 절연막을 형성하는 기술인 APL(Advanced Planalization Layer) 박막에 대한 연구가 활발히 진행되고 있다.In the semiconductor device technology having a line width of 0.1 μm or less, in the gap-fill characteristics of the insulating oxide film, the filling of the contact hole is reduced as the space of the contact hole decreases and the aspect ratio gradually increases. Due to this problem, voids occur, and thus, an APL (Advanced Planalization Layer) thin film, which is a technology of forming an insulating film having flow characteristics, that is, a fluid insulating film, has been actively studied to solve such problems. .

이러한, APL 박막 기술 중 자기 평탄화 CVD(화학기상증착; 이하 CVD라 함)막은 상당히 유동성이 높은 반응 중간체를 형성하는 것으로, 막 형성을 할 때 우수하게 채움 평탄화를 실현할 수 있다. 그 때문에 평탄화된 층간절연막 형성을 단일한 공정으로 할 수 있어서 종래의 복잡한 공정에 비해서 공정 비용을 효과적으로 줄일 수 있는 바, 자기 평탄화 CVD막은 저압화학기상증착(Low Pressure Chemical Vapor Deposition; 이하 LPCVD라 함)법을 이용하여 반응소스로 과수(H2O2)와 사일렌(SiH4)을 이용하여 형성하며, 자체적인 플로우 특성을 갖고 있어 갭-필 특성이 우수한 장점이 있다.In the APL thin film technology, the self-planarized CVD (chemical vapor deposition; CVD) film forms a highly flowable reaction intermediate, which can achieve excellent fill planarization when forming the film. Therefore, the planarized interlayer insulating film can be formed as a single process, and the process cost can be effectively reduced as compared with the conventional complicated process. It is formed by using fruit tree (H 2 O 2 ) and xylene (SiH 4 ) as a reaction source by the method, and has an advantage of excellent gap-fill characteristics because it has its own flow characteristics.

전술한 유동성 절연막의 장점을 요약하면 다음과 같다.The advantages of the above-described fluid insulating film is summarized as follows.

가. 갭-필 특성이 우수하다.end. Good gap-fill characteristics.

나. 막 안정성이 높다.I. Membrane stability is high.

다. 크랙(Crack)과 들뜸(Lifting) 형상이 발생하지 않는다.All. Cracks and lifting shapes do not occur.

라. 650℃ 이하의 온도에서 증착하므로 열경비(Thermal budget)가 낮다.la. The thermal budget is low due to deposition at temperatures below 650 ° C.

마. 1000℃ 이상의 온도에 대한 내성이 있다.hemp. It is resistant to temperatures of at least 1000 ° C.

바. 강한 케미컬에 대한 내성과 평탄성을 갖는다.bar. Strong chemical resistance and flatness.

그러나, 자기 평탄화 CVD막 즉, 유동성 절연막은 배선 내의 스페이스 지역의 골 내부에는 수십Å 정도의 미세기공(Nanopore)이 존재하는 단점이 있는 바, 이러한 미세기공은 랜딩플러그콘택(Landing Plug Contact; 이하 LPC라 함) 형성시 스페이스 내부에서 식각멈춤(Etch stop) 현상을 유발하여 원하는 크기의 콘택을 형성할 수 없는 문제점이 발생한다.However, the self-planarizing CVD film, that is, the fluid insulating film has a disadvantage in that there are several tens of nanopore inside the valley of the space area in the wiring, and the micropore has a landing plug contact (LPC). When forming, it causes an etch stop phenomenon inside the space, and thus a problem in that a contact having a desired size cannot be formed.

도 1과 도 2는 각각 유동성 절연막 형성 및 LPC 식각 후의 단면을 각각 도시한 SEM 사진으로서, 도 1에 도시된 'A'와 같이 좁은 스페이스 지역에 미세기공이 존재하게 되어, 도 2에 도시된 'B'와 같이 식각멈춤에 의해 불완전한 콘택 오픈 형상이 발생한다.1 and 2 are SEM photographs showing the cross-sections after the formation of the flowable insulating film and the LPC etching, respectively, and micropores exist in a narrow space region as shown in FIG. An incomplete contact open shape is generated by the etching stop as in B '.

이는 유동성 절연막의 물성적 한계 즉, 패턴의 선간거리가 작을 경우 증착 후 어닐링(Annealing)시 빠져나오지 못한 수소 원소에 의한 미세기공이 주 원인이며, 전술한 불균일한 식각 프로파일은 특히 하지층이 질화막계열일 경우 주로 발생한다.This is mainly due to the physical limitations of the flowable insulating layer, that is, the micropores due to hydrogen elements which did not escape during annealing after deposition when the line distance of the pattern is small. Occurs mainly when

본 발명은 상기한 종래기술의 문제점을 해결하기 위해 제안된 것으로서, 콘택 형성시 양호한 식각 프로파일을 얻기에 적합한 반도체 소자 제조 방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method for manufacturing a semiconductor device suitable for obtaining a good etching profile when forming a contact.

도 1은 유동성 절연막 형성 후의 단면을 도시한 SEM 사진,1 is a SEM photograph showing a cross section after formation of a flowable insulating film;

도 2는 유동성 절연막의 LPC 식각 후의 단면을 도시한 SEM 사진,2 is a SEM photograph showing a cross section after LPC etching of a flowable insulating film,

도 3a 내지 도 3c는 본 발명의 일실시예에 따른 반도체 소자 제조 공정을 도시한 단면도.3A to 3C are cross-sectional views illustrating a semiconductor device manufacturing process in accordance with an embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

10 : 기판11 : 게이트절연막10 substrate 11 gate insulating film

12 : 게이트전극용 전도막 13 : 하드마스크12: conductive film for gate electrode 13: hard mask

14, 15 : 스페이서용 절연막16 : 식각멈춤막14, 15 insulating film for spacer 16: etching stop film

17 : 유동성 절연막19 : 콘택홀17: fluid insulating film 19: contact hole

상기의 목적을 달성하기 위해 본 발명은, 기판 상에 이웃하는 다수의 도전패턴을 형성하는 단계; 상기 도전패턴이 형성된 전체 프로파일을 따라 질화막계열의 스페이서용 절연막과 식각멈춤막을 차례로 형성하는 단계; 상기 식각멈춤막 상에 유동성 절연막을 형성하는 단계; 상기 유동성 절연막을 선택적으로 식각하여 상기 도전패턴 사이의 상기 식각멈춤막을 노출시키는 단계; 및 상기 식각멈춤막과 상기 스페이서용 절연막을 선택적으로 식각하여 상기 기판 표면을 노출시키는 콘택홀을 형성하는 단계를 포함하는 반도체 소자 제조 방법을 제공한다.In order to achieve the above object, the present invention comprises the steps of forming a plurality of neighboring conductive patterns on the substrate; Sequentially forming an insulating film for a spacer of an nitride film series and an etch stop film along the entire profile where the conductive pattern is formed; Forming a flowable insulating film on the etch stop film; Selectively etching the flowable insulating film to expose the etch stop layer between the conductive patterns; And selectively etching the etch stop layer and the spacer insulating layer to form a contact hole exposing the surface of the substrate.

본 발명은 유동성 절연막을 갭-필 물질로 사용하는 공정에서 콘택 식각시 발생하는 식각멈춤을 억제하여 유니폼(Uniform)한 콘택 형성을 이루기 위해, 유동성 절연막과 식각 정도에 차이를 갖는 질화막 사이에 알루미늄 산화막 등을 식각멈춤막으로 사용하여 식각 단계를 분리실시함으로써 종래의 식각멈춤 현상을 방지하여 양호한 콘택 형성 프로파일을 얻도록 하는 것을 기술적 특징으로 한다.The present invention provides a uniform contact formation by suppressing the etch stop generated during contact etching in the process of using the fluid insulating film as a gap-fill material, the aluminum oxide film between the nitride and the nitride film having a difference in the etching degree It is a technical feature that the etching step is separated using the back as an etch stop film to prevent a conventional etch stop phenomenon to obtain a good contact formation profile.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부한 도면을 참조하여 상세하게 설명하는 바, 도 3a내지 도 3c는 본 발명의 일실시예에 따른 반도체 소자 제조 공정을 도시한 단면도이다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. 3A to 3C are cross-sectional views illustrating a semiconductor device manufacturing process according to an embodiment of the present invention.

먼저, 도 3a에 도시된 바와 같이 반도체 소자를 이루기 위한 여러 요소가 형성된 기판(10) 상에 소정의 도전패턴을 형성하는 바, 도전패턴은 비트라인 또는 게이트전극 등을 포함하며, 이하에서는 게이트전극을 그 일예로 하여 설명한다.First, as shown in FIG. 3A, a predetermined conductive pattern is formed on the substrate 10 on which various elements for forming a semiconductor device are formed. The conductive pattern includes a bit line or a gate electrode, and hereinafter, a gate electrode. Will be described as an example.

구체적으로, 산화막계열의 게이트절연막(11)과 폴리실리콘, 텅스텐 또는 텅스텐 실리사이드 등을 단독 또는 혼합하여 게이트전극용 전도막(12)과 질화막 등의 하드마스크(13)을 차례로 증착한 후, 게이트전극 마스크를 이용한 사진식각 공정을 실시하여 게이트전극을 형성한다.Specifically, the gate insulating film 11 and the polysilicon, tungsten or tungsten silicide or the like are deposited alone or mixed to deposit the gate electrode conductive film 12 and the hard mask 13 such as a nitride film in sequence, and then the gate electrode. The gate electrode is formed by performing a photolithography process using a mask.

이어서, 게이트전극 측벽을 보호하기 위해 스페이서용 절연막(14, 15)을 차례로 형성하는 바, 이 때 실리콘질화막 또는 실리콘 산화질화막을 이용하여 각각 50Å ∼ 500Å의 두께로 형성하며, 계속해서 스페이서용 절연막(16) 상에 게이트전극간 스페이스를 감안하여 식각멈춤막(16)을 50Å ∼ 500Å의 두께로 얇게 형성하는 바, 이 때 후속 유동성 절연막과의 선택비를 갖도록 Al2O3, HfO2, ZrO2, ZnO2, Ta2O5또는 SiOCH5등을 이용하며, 이 때, 원자층증착(Atomic Layer Deposition; 이하 ALD라 함)법을 이용하는 것이 바람직한 바, 주지된 바와 같이 ALD법은 수십Å의 얇은 두께로의 형성이 가능하며 단차피복성(Step coverage) 또한 우수하다.Subsequently, spacer insulating films 14 and 15 are sequentially formed in order to protect the sidewalls of the gate electrode. At this time, the silicon insulating film or the silicon oxynitride film is formed to have a thickness of 50 kPa to 500 kPa, and the spacer insulating film ( 16) The etch stop layer 16 is thinly formed to have a thickness of 50 kV to 500 kV in consideration of the space between the gate electrodes, so that Al 2 O 3 , HfO 2 , and ZrO 2 have a selectivity with the subsequent fluid insulating layer. , ZnO 2 , Ta 2 O 5, or SiOCH 5 , and the like, and in this case, it is preferable to use atomic layer deposition (hereinafter referred to as ALD) method. It can be formed in thickness and has excellent step coverage.

계속해서, 게이트전극 사이의 스페이스를 충분히 채울 수 있을 정도로 유동성 절연막(17)을 형성한다.Subsequently, the fluid insulating film 17 is formed to sufficiently fill the space between the gate electrodes.

한편, 본 발명에서는 후속 층간절연막으로 HDP 산화막 대신 플로우 및 자체 평탄화 특성이 우수한 APL 박막을 층간절연막으로 적용하며, 특히 APL 박막 기술 중 자기 평탄화 CVD막을 적용하는 바, 자기 평탄화 CVD막은 상당히 유동성이 높은 반응 중간체를 형성하는 것으로, 막 형성을 할 때 우수하게 채움 평탄화를 실현할 수 있다. 그 때문에 평탄화된 층간절연막 형성을 단일한 공정으로 할 수 있어서 종래의 복잡한 공정에 비해서 공정 비용을 효과적으로 줄일 수 있다.Meanwhile, in the present invention, an APL thin film having excellent flow and self-planarization properties is applied as an interlayer insulating film instead of an HDP oxide film as a subsequent interlayer insulating film. In particular, a self-planarizing CVD film is applied in the APL thin film technology. By forming the intermediate, it is possible to realize filling flattening excellent when forming a film. Therefore, the planarized interlayer insulating film can be formed as a single process, and the process cost can be effectively reduced as compared with the conventional complicated process.

이러한 자기 평탄화 CVD막 즉, 유동성 절연막(17)은 LPCVD법에 의해 SiH4와 H2O2에 의한 CVD로 형성한 실리콘산화막으로 상당히 우수한 채움 평탄성을 갖고 있으며, 또한 형성된 막은 막중의 함유 수분이 적어 고품질이다.This self-planarizing CVD film, that is, the fluid insulating film 17 is a silicon oxide film formed by CVD by SiH 4 and H 2 O 2 by LPCVD, and has a very good filling flatness, and the formed film has a low content of moisture in the film. It is high quality.

구체적으로, 유동성 절연막(17)을 형성하기 전에 후속 유동성 절연막의 접착력 및 갭-필 특성을 향상시키기 위해 플라즈마 처리가 필요하며, 이 때 N2O를 포함한 플라즈마를 이용한 다음, N2O 등의 질소를 포함하는 반응소스를 이용한 LPVCD법을 사용하여 2000Å ∼ 10000Å의 두께로 형성하며, 이 때 유동성 절연막(17)은 SiOxHy(x는 0 ∼ 3, y는 0 ∼ 1)의 성분을 포함한다.Nitrogen, and a plasma treatment is required in order to improve the filter characteristics, this time using a plasma, including N 2 O, and then, such as N 2 O - specifically, the adhesive force and the gap of the subsequent liquid insulating film before the formation of the liquid insulating film 17 Using a LPVCD method using a reaction source containing a to form a thickness of 2000 kPa ~ 10000 kPa, wherein the flowable insulating film 17 contains components of SiO x H y (x is 0-3, y is 0-1) do.

구체적으로, 전술한 질소를 포함하는 반응소스는 SiH4, SiHa(CH3)b(a, b는 0 ∼ 4), H2O2, O2, H2O 및 N2O를 포함하는 것으로, 이러한 반응소스를 이용하여 100mTorr ∼ 2Torr의 저압 및 -10℃ ∼ 100℃의 온도 하에서 실시하며, 이 때 100SCCM ∼ 3000SCCM 유량의 N2O를 사용하는 것이 바람직하다.Specifically, the reaction source containing nitrogen described above includes SiH 4 , SiHa (CH 3 ) b (a, b is 0 to 4), H 2 O 2 , O 2 , H 2 O and N 2 O. Using such a reaction source, it is carried out under a low pressure of 100 mTorr to 2 Torr and a temperature of -10 ° C to 100 ° C, and it is preferable to use N 2 O at a flow rate of 100SCCM to 3000SCCM.

이어서, 유동성 절연막(17) 형성에 따른 유동성 절연막(17) 내에 잔류하는 수분을 제거하며 유동성 절연막(17)의 치밀화를 위해 플라즈마 처리 또는 열처리를 추가로 실시한다.Subsequently, water remaining in the fluid insulating film 17 due to the formation of the fluid insulating film 17 is removed, and plasma treatment or heat treatment is further performed for densification of the fluid insulating film 17.

구체적으로, 플라즈마 처리는 SiH4, SiHa(CH3)b(a, b는 0 ∼4), N2, NH3, O2, O3, Ar, He, Ne 또는 N2O 등의 가스를 혼합하여 5초 ∼ 200초 동안 실시하며, 열처리는 O2, N2, O3, N2O 또는 H2등의 가스 분위기 및 600℃ ∼ 800℃의 온도 하에서 10초 ∼ 200초 동안 실시하는 것이 바람직하다.Specifically, the plasma treatment is a gas such as SiH 4 , SiH a (CH 3 ) b (a, b is 0 to 4), N 2 , NH 3 , O 2 , O 3 , Ar, He, Ne or N 2 O The mixture is carried out for 5 seconds to 200 seconds, and the heat treatment is carried out for 10 seconds to 200 seconds under a gas atmosphere such as O 2 , N 2 , O 3 , N 2 O or H 2 and a temperature of 600 ℃ to 800 ℃ It is preferable.

다음으로, 도 3b에 도시된 바와 같이 유동성 절연막(17) 상에 콘택 형성을 위한 포토레지스트 패턴(18)을 형성한 다음, 포토레지스트 패턴(18)을 식각마스크로 한 선택적 식각 공정을 통해 유동성 절연막(17)을 식각하는 바, 이 때 식각멈춤막(16) 상에서 유동성 절연막(17)과 질화막계열의 스페이서용 절연막(16)의 식각률 차이에 의한 불균일한 식각 프로파일 형성을 억제한 다음, 계속해서 도 3c에 도시된 바와 같이 식각멈춤막(16)과 스페이서용 절연막(15, 16)을 식각하여 게이트전극 사이의 기판(10) 표면을 오출시키는 콘택홀(19)을 형성한다.Next, as shown in FIG. 3B, the photoresist pattern 18 for forming a contact is formed on the flow insulating film 17, and then the flow insulating film is subjected to a selective etching process using the photoresist pattern 18 as an etching mask. (17) is etched. At this time, the formation of the non-uniform etching profile caused by the difference in the etching rate of the flowable insulating film 17 and the nitride film-based spacer insulating film 16 on the etch stop film 16 is suppressed. As shown in FIG. 3C, the etch stop layer 16 and the spacer insulating layers 15 and 16 are etched to form a contact hole 19 that exposes the surface of the substrate 10 between the gate electrodes.

이 때, 통상의 SAC 공정시 사용하는 불소계플라즈마 예컨대, C4F8, CHF3, C2F6또는 SF6등의 불소계 가스에 Ar, O2또는 CO 등을 적절히 혼합하여 사용한다.At this time, Ar, O 2 , CO, or the like is suitably used in fluorine-based plasmas used in a normal SAC process, such as C 4 F 8 , CHF 3 , C 2 F 6, or SF 6 .

이 때, 전술한 바와 같이 식각멈춤막(16)에서 일차로 식각을 멈춤 후 일련의 식각 공정을 계속해서 진행할 수도 있으며, 스페이서용 절연막(160 위에서 식각을멈추고 포토레지스트 패턴(18)을 제거한 다음, 게이트전극 주변에 USG(Undoped Silicate Glass) 케핑(Capping)을 위한 산화막을 증착하거나 또는 불산계 용액을 사용하여 하지 액티브 면적을 확보한 후에 플라즈마 식각을 통해 스페이서용 절연막(16, 15)을 제거할 수도 있다.At this time, as described above, after stopping the etching in the etch stop layer 16, a series of etching processes may be continued, and the etching stops on the spacer insulating layer 160 and the photoresist pattern 18 is removed. After depositing an oxide film for USG (Undoped Silicate Glass) capping around the gate electrode or using a hydrofluoric acid solution, the insulating layer 16 and 15 for the spacer may be removed by plasma etching. have.

전술한 본 발명은, 유동성 절연막을 층간절연막으로 사용하며 게이트전극 등의 스페이서용 절연막을 질화막으로 사용하는 경우 그 상부에 알루미늄 산화막 등의 식각멈춤막을 적용함으로써, 종래의 유동성 절연막과 스페이서용 질화막의 식각 정도의 차이에 기인한 불균일한 식각 프로파일의 발생 등을 방지, 즉 유니폼한 콘택을 형성할 수 있음을 실시예를 통해 알아 보았다.According to the present invention, when the insulating film for the spacer such as the gate electrode is used as the nitride film and the etching insulating film such as the aluminum oxide film is applied on the upper portion of the present invention, the liquid insulating film and the nitride film for the spacer are etched. The embodiment has been found to prevent the occurrence of a non-uniform etching profile due to the difference in degree, that is, to form a uniform contact.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 바와 같은 본 발명은, 콘택 프로파일을 개선함으로써 소자의 불량 확률을 감소시킬 수 있어, 궁극적으로 반도체 소자의 수율을 향상시킬 수 있는 탁월한 효과를 기대할 수 있다.As described above, the present invention can reduce the probability of failure of a device by improving a contact profile, so that an excellent effect of ultimately improving the yield of a semiconductor device can be expected.

Claims (7)

기판 상에 이웃하는 다수의 도전패턴을 형성하는 단계;Forming a plurality of neighboring conductive patterns on the substrate; 상기 도전패턴이 형성된 전체 프로파일을 따라 질화막계열의 스페이서용 절연막과 식각멈춤막을 차례로 형성하는 단계;Sequentially forming an insulating film for a spacer of an nitride film series and an etch stop film along the entire profile where the conductive pattern is formed; 상기 식각멈춤막 상에 유동성 절연막을 형성하는 단계;Forming a flowable insulating film on the etch stop film; 상기 유동성 절연막을 선택적으로 식각하여 상기 도전패턴 사이의 상기 식각멈춤막을 노출시키는 단계; 및Selectively etching the flowable insulating film to expose the etch stop layer between the conductive patterns; And 상기 식각멈춤막과 상기 스페이서용 절연막을 선택적으로 식각하여 상기 기판 표면을 노출시키는 콘택홀을 형성하는 단계Selectively etching the etch stop layer and the spacer insulating layer to form a contact hole exposing the surface of the substrate 를 포함하는 반도체 소자 제조 방법.Semiconductor device manufacturing method comprising a. 제 1 항에 있어서,The method of claim 1, 상기 식각멈춤막을 50Å 내지 500Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자 제조 방법.The etching stop film is a semiconductor device manufacturing method, characterized in that to form a thickness of 50 ~ 500Å. 제 1 항에 있어서,The method of claim 1, 상기 식각멈춤막은 Al2O3, HfO2, ZrO2, ZnO2, Ta2O5또는 SiOCH5을 포함하는 것을 특징으로 하는 반도체 소자 제조 방법.The etch stop layer includes Al 2 O 3 , HfO 2 , ZrO 2 , ZnO 2 , Ta 2 O 5 or SiOCH 5 . 제 1 항에 있어서,The method of claim 1, 상기 유동성 절연막을 2000Å 내지 10000Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자 제조 방법.The flowable insulating film is a semiconductor device manufacturing method characterized in that to form a thickness of 2000kPa to 10000kPa. 제 1 항에 있어서,The method of claim 1, 상기 유동성 절연막과 상기 식각멈춤막 및 상기 스페이서용 절연막을 식각하는 단계에서 불소계 플라즈마를 이용하는 특징으로 하는 반도체 소자 제조 방법.And using a fluorine-based plasma in etching the fluid insulating film, the etch stop film, and the spacer insulating film. 제 1 항에 있어서,The method of claim 1, 상기 스페이서용 절연막을 50Å 내지 500Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자 제조 방법.The spacer insulating film is formed to a thickness of 50 kV to 500 kV. 제 1 항에 있어서,The method of claim 1, 상기 스페이서용 절연막을 실리콘질화막 또는 실리콘산화질화막을 단독 또는 적층하여 사용하는 것을 특징으로 하는 반도체 소자 제조 방법.And a silicon nitride film or a silicon oxynitride film alone or laminated.
KR1020010079297A 2001-12-14 2001-12-14 Method for fabricating semiconductor device KR20030049159A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100459724B1 (en) * 2002-09-11 2004-12-03 삼성전자주식회사 Semiconductor device having a SiN etch stopper by low temperature ALD and fabricating method the same
KR100780607B1 (en) * 2006-06-30 2007-11-30 주식회사 하이닉스반도체 Method for fabricating semiconductor device
KR100908828B1 (en) * 2006-12-27 2009-07-21 주식회사 하이닉스반도체 Method for manufacturing a semiconductor device having a landing plug contact
US7589006B2 (en) 2006-06-30 2009-09-15 Hynix Semiconductor Inc. Method for manufacturing semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100459724B1 (en) * 2002-09-11 2004-12-03 삼성전자주식회사 Semiconductor device having a SiN etch stopper by low temperature ALD and fabricating method the same
KR100780607B1 (en) * 2006-06-30 2007-11-30 주식회사 하이닉스반도체 Method for fabricating semiconductor device
US7589006B2 (en) 2006-06-30 2009-09-15 Hynix Semiconductor Inc. Method for manufacturing semiconductor device
KR100908828B1 (en) * 2006-12-27 2009-07-21 주식회사 하이닉스반도체 Method for manufacturing a semiconductor device having a landing plug contact

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