KR100428685B1 - Method for fabrication of semiconductor device - Google Patents
Method for fabrication of semiconductor device Download PDFInfo
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- KR100428685B1 KR100428685B1 KR10-2001-0080161A KR20010080161A KR100428685B1 KR 100428685 B1 KR100428685 B1 KR 100428685B1 KR 20010080161 A KR20010080161 A KR 20010080161A KR 100428685 B1 KR100428685 B1 KR 100428685B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
Abstract
본 발명은 APL 막 등의 유동성 절연막을 층간절연막으로 사용하는 반도체 소자의 콘택 형성 공정에서 콘택 영역의 상부가 넓어지는 현상을 방지할 수 있는 반도체 소자 제조 방법을 제공하기 위한 것으로, 이를 위해 본 발명은, 기판 상에 절연막을 형성하는 단계; 상기 절연막을 관통하여 상기 기판에 콘택되며, 그 상부가 평탄화된 플러그를 형성하는 단계; 상기 플러그를 포함한 전체 구조 상에 SiH4, SiHa(CH3)b(a, b는 0 ∼ 4), H2O2, O2, H2O 및 N2O를 포함하는 반응소스를 이용하여 유동성 절연막을 형성하는 단계; 상기 유동성 절연막 상에 후속 습식 세정시 상기 유동성 절연막에 비해 식각 내성을 갖는 식각방지막으로 SiH4-산화막을 인시튜로 형성하는 단계; 상기 식각방지막과 상기 유동성 절연막을 선택적으로 식각하여 플러그 표면을 노출시키는 콘택홀을 형성하는 단계; 및 상기 식각단계에서 발생한 식각잔유물을 제거하기 위해 습식 세정하는 단계를 포함하는 반도체 소자 제조 방법을 제공한다.The present invention is to provide a method for manufacturing a semiconductor device that can prevent the phenomenon that the upper portion of the contact region in the contact forming process of the semiconductor device using a fluid insulating film such as an APL film as an interlayer insulating film, Forming an insulating film on the substrate; Forming a plug penetrating the insulating film and contacting the substrate and having a flattened upper portion thereof; Reaction source containing SiH 4 , SiHa (CH 3 ) b (a, b is 0-4), H 2 O 2 , O 2 , H 2 O and N 2 O on the entire structure including the plug Forming a flowable insulating film; Forming an SiH 4 -oxide film in situ as an anti-etching film having an etching resistance compared to the flowable insulating film upon subsequent wet cleaning on the flowable insulating film; Selectively etching the etch stop layer and the flowable insulating layer to form a contact hole exposing a plug surface; And it provides a semiconductor device manufacturing method comprising the step of wet cleaning to remove the etching residue generated in the etching step.
Description
본 발명은 반도체 기술에 관한 것으로, 특히 APL(Advanced Planalization Layer) 박막을 이용한 반도체 소자 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly, to a method of manufacturing a semiconductor device using an Advanced Planalization Layer (APL) thin film.
0.16㎛ 이하의 선폭을 갖는 반도체 소자 기술에서는 절연산화막의 갭-필(Gap-fill) 특성에 있어서 콘택홀 등의 스페이스가 감소하고 종횡비(Aspect ratio)가 점점 증가함에 따라 완전한 필링(Filling, 채움)이 불가능하여, 보이드(Void)가 생기는 문제점이 발생한다.In the semiconductor device technology having a line width of 0.16 µm or less, the filling of the gap is performed as the space of the contact hole decreases and the aspect ratio gradually increases in the gap-fill characteristics of the insulating oxide film. This is impossible, and a problem arises in which voids are generated.
또한, 폴리실리콘 플러그간의 격리(Isolation) 후에는 화학기계적연마(Chemical Mechanical Polishing; 이하 CMP라 함) 공정시 디싱(Dishing)에 의해 플러그 형성 영역 즉, 게이트 스페이스 영역의 골이 깊어지게 된다.도 1은 플러그 격리를 위한 CMP 후의 프로파일을 도시한 SEM(Scanning electron spectroscopy) 사진을 나타내는 바, 'A'는 전술한 디싱 현상을 도시하고 있다.In addition, after isolation between the polysilicon plugs, the valleys of the plug formation regions, that is, the gate space regions, are deepened by dishing during the chemical mechanical polishing (CMP) process. Shows a scanning electron spectroscopy (SEM) photograph showing the profile after CMP for plug isolation, and 'A' shows the dishing phenomenon described above.
따라서, 플러그와 비트라인 간의 절연을 위한 산화막 형성시에 보이드가 발생하고 게이트 스페이스의 골을 완전히 매립할 수 없으며, 비트라인 패턴 형성시에 레지듀(Residue)가 발생하여 'B'와 같이 브릿지(Bridge)가 발생한다(여기서 SiH4-USG의 층간절연막 적용).Therefore, voids are generated when the oxide film for insulation between the plug and the bit line is formed, and valleys in the gate space cannot be completely filled. Residue occurs when the bit line pattern is formed. Bridge) (wherein the interlayer insulating film of SiH 4 -USG is applied).
이러한 문제점을 해결하기 위해 플로우 특성을 갖는 절연막 즉, 유동성 절연막 중의 하나인 APL(Advanced Planalization Layer)막에 대한 연구가 활발히 진행되고 있다.In order to solve this problem, researches on an insulating film having a flow characteristic, that is, an APL (Advanced Planalization Layer) film, which is one of the fluid insulating films, have been actively conducted.
이러한, APL 박막 기술 중 자기 평탄화 CVD(화학기상증착; 이하 CVD라 함)막은 상당히 유동성이 높은 반응 중간체를 형성하는 것으로, 막 형성을 할 때 우수하게 채움 평탄화를 실현할 수 있다. 그 때문에 평탄화된 층간절연막 형성을 단일한 공정으로 할 수 있어서 종래의 복잡한 공정에 비해서 공정 비용을 효과적으로 줄일 수 있다. 자기 평탄화 CVD막 즉, 유동성 절연막(이하 유동성 절연막이라 함)은 저압화학기상증착(Low Pressure Chemical Vapor Deposition; 이하 LPCVD라 함)법을 이용하여 반응소스로 과수(H2O2)와 사일렌(SiH4)을 이용하여 형성하며, 자체적인 플로우 특성을 갖고 있어 갭-필 특성이 우수한 장점이 있다.In the APL thin film technology, the self-planarized CVD (chemical vapor deposition; CVD) film forms a highly flowable reaction intermediate, which can achieve excellent fill planarization when forming the film. Therefore, the planarized interlayer insulating film can be formed as a single process, and the process cost can be effectively reduced as compared with the conventional complicated process. The self-planarizing CVD film, ie, the fluid insulating film (hereinafter referred to as the fluid insulating film), is a reaction source using low pressure chemical vapor deposition (LPCVD) method as a reaction source of fruit water (H 2 O 2 ) and xylene ( It is formed by using SiH 4 ), and has its own flow characteristics, so the gap-fill characteristics are excellent.
도 2는 유동성 절연막의 빠른 식각 특성에 기인한 콘택 상부의 넓어짐(Widening) 현상을 도시한 평면 사진이다.FIG. 2 is a planar photograph illustrating a widening phenomenon of an upper portion of a contact due to a fast etching characteristic of a flowable insulating layer.
유동성 절연막은 상기한 장점에도 불구하고 습식 세정시 사용되는 케미컬(Chemical)에 대한 식각률이 빠른 단점이 있다.즉, 비트라인 콘택을 형성한 후, 비트라인 전세정 공정에서 도 2의 'C'와 같이 상부의 콘택 크기가 넓어지는 문제점이 발생하며, 콘택 상부에서는 약 150Å 정도까지 개구부가 커진 것을 확인할 수 있다.Despite the above-mentioned advantages, the flowable insulating layer has a disadvantage in that the etch rate for the chemical used in the wet cleaning is fast. That is, after the bit line contact is formed, 'C' of FIG. As a result, a problem arises in that the contact size of the upper part is widened, and the opening is enlarged to about 150Å at the upper part of the contact.
한편, 전술한 문제점을 방지하기 위해 비트라인 콘택 형성시 콘택 사이즈를 미리 작게 형성하는 방법도 강구되었으나, 타겟 보다 작은 콘택을 형성하기가 어려우며, 또 다른 방법으로 완충산화막식각제(Buffered Oxide Etchant; NH4F + HF + H2O, 이하 BOE라 함)를 이용한 세정 시간을 감소시키는 방법이 있으나, 이 또한 세정 시간을 충분히 확보하기가 힘들어 비트라인 콘택 저항이 증가하는 문제점이 발생한다.On the other hand, in order to prevent the above-mentioned problems, a method of forming a contact size smaller when forming a bit line contact has been made in advance, but it is difficult to form a smaller contact than a target, and as another method, a buffered oxide etchant (NH); 4 F + HF + H 2 O, hereinafter referred to as BOE, there is a method for reducing the cleaning time, but this also causes a problem that the bit line contact resistance increases because it is difficult to secure enough cleaning time.
본 발명은 상기한 종래기술의 문제점을 해결하기 위해 제안된 것으로서, APL 막 등의 유동성 절연막을 층간절연막으로 사용하는 반도체 소자의 콘택 형성 공정에서 콘택 영역의 상부가 넓어지는 현상을 방지할 수 있는 반도체 소자 제조 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and is a semiconductor capable of preventing the upper portion of a contact region from being widened in a contact forming process of a semiconductor device using a fluid insulating film such as an APL film as an interlayer insulating film. Its purpose is to provide a device manufacturing method.
도 1은 플러그 격리를 위한 CMP 후의 프로파일을 도시한 SEM 사진,1 is a SEM photograph showing the profile after CMP for plug isolation;
도 2는 유동성 절연막의 빠른 식각 특성에 기인한 콘택 상부의 넓어짐 현상을 도시한 평면 사진,FIG. 2 is a planar photograph showing a widening phenomenon of the upper part of the contact due to the fast etching characteristic of the flowable insulating film; FIG.
도 3a 내지 도 3c는 본 발명의 일실시예에 따른 반도체 소자 제조 공정을 도시한 단면도.3A to 3C are cross-sectional views illustrating a semiconductor device manufacturing process in accordance with an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
10 : 기판 11 : 게이트절연막10 substrate 11 gate insulating film
12 : 게이트전극 13 : 하드마스크12 gate electrode 13 hard mask
15: 절연막 16 : 플러그15: insulating film 16: plug
17 : 유동성 절연막 18 : 식각방지막17 flowable insulating film 18 etching prevention film
19 : 콘택홀19: contact hole
상기의 목적을 달성하기 위해 본 발명은, 기판 상에 절연막을 형성하는 단계; 상기 절연막을 관통하여 상기 기판에 콘택되며, 그 상부가 평탄화된 플러그를 형성하는 단계; 상기 플러그를 포함한 전체 구조 상에 SiH4, SiHa(CH3)b(a, b는 0 ∼ 4), H2O2, O2, H2O 및 N2O를 포함하는 반응소스를 이용하여 유동성 절연막을 형성하는 단계; 상기 유동성 절연막 상에 후속 습식 세정시 상기 유동성 절연막에 비해 식각 내성을 갖는 식각방지막으로 SiH4-산화막을 인시튜로 형성하는 단계; 상기 식각방지막과 상기 유동성 절연막을 선택적으로 식각하여 플러그 표면을 노출시키는 콘택홀을 형성하는 단계; 및 상기 식각단계에서 발생한 식각잔유물을 제거하기 위해 습식 세정하는 단계를 포함하는 반도체 소자 제조 방법을 제공한다.The present invention to achieve the above object, forming an insulating film on a substrate; Forming a plug penetrating the insulating film and contacting the substrate and having a flattened upper portion thereof; Reaction source containing SiH 4 , SiHa (CH 3 ) b (a, b is 0-4), H 2 O 2 , O 2 , H 2 O and N 2 O on the entire structure including the plug Forming a flowable insulating film; Forming an SiH 4 -oxide film in situ as an anti-etching film having an etching resistance compared to the flowable insulating film upon subsequent wet cleaning on the flowable insulating film; Selectively etching the etch stop layer and the flowable insulating layer to form a contact hole exposing a plug surface; And it provides a semiconductor device manufacturing method comprising the step of wet cleaning to remove the etching residue generated in the etching step.
본 발명은 유동성 절연막을 층간절연막으로 사용하는 공정에서 콘택 식각 후 실시하는 세정시 케미컬에 대해 식각률이 높은 유동성 절연막에 비해 케미컬에 대한 식각 내성을 갖는 사일렌(SiH4) 계열의 산화막을 APL막 등의 유동성 절연막과 인시튜(In-situ) 공정으로 일정 두께로 형성함으로써, 양호한 콘택 프로파일을 얻을 수 있으며 습식 케미컬을 이용한 세정공정시 유동성 절연막의 빠른 식각 특성으로 인해 콘택 상부가 넓어지는 현상을 방지하고자 한다.According to the present invention, in the process of using a fluid insulating film as an interlayer insulating film, a silicon oxide (SiH 4 ) -based oxide film having an etching resistance against chemicals is compared to a fluid insulating film having a high etch rate for chemicals after contact etching. By forming a certain thickness in the in-situ process with the flowable insulating film of the can obtain a good contact profile and to prevent the contact upper part widening due to the fast etching characteristics of the flowable insulating film during the cleaning process using the wet chemical do.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부한 도 3a 내지 도 3c를 참조하여 상세하게 설명한다.Hereinafter, in order to explain in detail enough to enable those skilled in the art to easily carry out the technical idea of the present invention, refer to FIGS. 3A to 3C attached to the most preferred embodiment of the present invention. It will be described in detail.
도 3a 내지 도 3c는 본 발명의 일실시예에 따른 반도체 소자 제조 공정을 도시한 단면도로서, 이를 참조하여 후술한다.3A to 3C are cross-sectional views illustrating a semiconductor device manufacturing process according to an embodiment of the present invention, which will be described later with reference to the drawings.
먼저, 도 3a에 도시된 바와 같이 반도체 소자를 이루기 위한 여러 요소가 형성된 기판(10) 상에 소정의 도전패턴을 형성하는 바, 도전패턴은 게이트전극을 포함하며, 이하에서는 게이트전극을 그 일예로 하여 설명한다.First, as shown in FIG. 3A, a predetermined conductive pattern is formed on a substrate 10 on which various elements for forming a semiconductor element are formed. The conductive pattern includes a gate electrode, and the gate electrode is exemplarily described below. Will be explained.
구체적으로, 게이트절연막(11)과 폴리실리콘, 텅스텐, 텅스텐 실리사이드 등이 단독 또는 적층된 형태의 게이트전극(12)과 질화막 등을 이용한 하드마스크(13)를 포함하는 게이트전극 패턴을 형성한 후, 게이트전극 패턴이 형성된 기판(10) 전면에 절연막(15)을 형성한 다음, 절연막(15)을 선택적으로 식각하여 게이트전극 패턴 사이의 기판(10) 표면을 노출시킨다. 이어서, 전면에 폴리실리콘 등을 증착한 다음 CMP 공정을 실시하여 이웃하는 플러그(16)와 서로 격리된 플러그(16)를 형성한다.Specifically, after the gate insulating pattern 11 and the gate electrode pattern including the gate electrode 12 having a single or stacked form of polysilicon, tungsten, tungsten silicide, etc., and a hard mask 13 using a nitride film, etc. are formed, After the insulating film 15 is formed on the entire surface of the substrate 10 on which the gate electrode pattern is formed, the insulating film 15 is selectively etched to expose the surface of the substrate 10 between the gate electrode patterns. Subsequently, polysilicon or the like is deposited on the entire surface, and then a CMP process is performed to form a plug 16 isolated from the neighboring plug 16.
한편, CMP 공정에 따른 하드마스크(13)와 플러그(16) 물질 및 절연막(15) 사이의 식각률 차이에 의해 플러그(16)에서는 도시된 'X'와 같이 디싱 현상이 발생하게 된다.On the other hand, due to the difference in the etching rate between the hard mask 13, the plug 16 material and the insulating film 15 according to the CMP process, dishing occurs in the plug 16 as shown in the 'X'.
따라서, 도 3b에 도시된 바와 같이 디싱가 발생한 플러그(16) 상부를 충분히 채울 수 있도록 유동성 절연막(17)을 형성한 다음, 인시튜 공정에 의해 200Å ∼300Å 두께의 식각방지막(18)을 형성한다.Accordingly, as shown in FIG. 3B, the fluid insulating layer 17 is formed to sufficiently fill the upper portion of the plug 16 on which dishing has occurred, and then an etch stop layer 18 having a thickness of 200 μs to 300 μs is formed by an in situ process. .
이 때, 식각방지막(18)은 SiH4를 이용한 산화막으로 유동성 절연막(17)에 비해 후속 세정시 사용되는 케미컬에 의한 식각률이 낮아 후속 공정에서 유동성 절연막(17)의 식각 방지 역할을 수행하는 역할을 하며, 그 증착 또한 인시튜로 공정이 진행되며, 유동성 절연막(17)의 반응소스인 SiH4를 사용하므로 별도의 추가 공정이라고 할 수 없다.At this time, the etching prevention film 18 is an oxide film using SiH 4, and has a lower etching rate due to chemicals used in subsequent cleaning than the fluid insulating film 17, and thus serves to prevent etching of the fluid insulating film 17 in a subsequent process. In addition, the deposition is also carried out in situ, and since SiH 4 , which is a reaction source of the flowable insulating layer 17, is used, it is not a separate additional process.
한편, 본 발명에서는 층간절연용 절연막으로 HDP 산화막 대신 플로우 및 자체 평탄화 특성이 우수한 APL 박막을 층간절연막으로 적용하며, 특히 APL 박막 기술 중 자기 평탄화 CVD막 형성 기술을 적용한다.자기 평탄화 CVD막은 상당히 유동성이 높은 반응 중간체를 형성하는 것으로, 막 형성을 할 때 우수하게 채움 평탄화를 실현할 수 있다. 그 때문에 평탄화된 층간절연막 형성을 단일한 공정으로 할 수 있어서 종래의 복잡한 공정에 비해서 공정 비용을 효과적으로 줄일 수 있다.In the present invention, an APL thin film having excellent flow and self-planarization properties is used as an interlayer insulating film instead of an HDP oxide film, and in particular, a self-planarizing CVD film forming technology is applied among the APL thin film technologies. By forming this high reaction intermediate, it is possible to realize filling planarization at the time of film formation. Therefore, the planarized interlayer insulating film can be formed as a single process, and the process cost can be effectively reduced as compared with the conventional complicated process.
이러한 자기 평탄화 CVD막 즉, 유동성 절연막(17)은 LPCVD법에 의해 SiH4와 H2O2에 의한 CVD로 형성한 실리콘산화막으로 상당히 우수한 채움 평탄성을 갖고 있으며, 또한 형성된 막은 막중의 함유 수분이 적어 고품질이다.This self-planarizing CVD film, that is, the fluid insulating film 17 is a silicon oxide film formed by CVD by SiH 4 and H 2 O 2 by LPCVD, and has a very good filling flatness, and the formed film has a low content of moisture in the film. It is high quality.
구체적으로, 유동성 절연막(17)을 형성하기 전에 후속 유동성 절연막의 접착력 및 갭-필(Gap-fill) 특성을 향상시키기 위해 플라즈마 처리가 필요하며, 이 때 N2O를 포함한 플라즈마를 이용한다.유동성 절연막(17)을 형성할 때, N2O 등의 질소를 포함하는 반응소스를 이용한 LPVCD법을 사용하여 적절한 두께로 형성하며, 이 때 유동성 절연막(17)은 SiOxHy(x는 0 ∼ 3, y는 0 ∼ 1)의 성분을 포함한다.Specifically, before forming the flowable insulating film 17, a plasma treatment is required to improve the adhesion and gap-fill characteristics of the subsequent flowable insulating film, wherein a plasma containing N 2 O is used. (17) is formed to an appropriate thickness by using the LPVCD method using a reaction source containing nitrogen such as N 2 O, wherein the flowable insulating film 17 is SiO x H y (x is 0 to 3 and y contains the component of 0-1.
구체적으로, 질소를 포함하는 반응소스는 SiH4, SiHa(CH3)b(a, b는 0 ∼ 4), H2O2, O2, H2O 및 N2O를 포함하는 것으로, 이러한 반응소스를 이용하여 100mTorr ∼ 2Torr의 저압 및 -10℃ ∼ 100℃의 온도 하에서 실시하며, 이 때 100SCCM ∼ 3000SCCM 정도의 N2O를 사용하는 것이 바람직하다.Specifically, the reaction source containing nitrogen includes SiH 4 , SiHa (CH 3 ) b (a, b is 0 to 4), H 2 O 2 , O 2 , H 2 O and N 2 O, The reaction source is used under a low pressure of 100 mTorr to 2 Torr and a temperature of −10 ° C. to 100 ° C., where N 2 O of about 100 SCCM to 3000 SCCM is preferably used.
이어서, 유동성 절연막(17) 형성에 따른 유동성 절연막(17) 내에 잔류하는 수분을 제거하며, 막치밀화를 위해 플라즈마 처리 또는 열처리를 추가로 실시한다.Subsequently, moisture remaining in the fluid insulating film 17 due to the formation of the fluid insulating film 17 is removed, and a plasma treatment or heat treatment is further performed for film densification.
구체적으로, 플라즈마 처리는 SiH4, SiHa(CH3)b(a, b는 0 ∼4), N2, NH3, O2, O3, Ar, He, Ne 또는 N2O 등의 가스를 혼합하여 5초 ∼ 200초 동안 실시하며, 열처리는 O2, N2, O3, N2O 또는 H2등의 가스 분위기 및 600℃ ∼ 800℃의 온도 하에서 10초 ∼ 200초 동안 실시하는 것이 바람직하다.Specifically, the plasma treatment is a gas such as SiH 4 , SiH a (CH 3) b (a, b is 0 to 4), N 2 , NH 3 , O 2 , O 3 , Ar, He, Ne or N 2 O The mixture is carried out for 5 seconds to 200 seconds, and the heat treatment is performed for 10 seconds to 200 seconds under a gas atmosphere such as O 2 , N 2 , O 3 , N 2 O, or H 2 and a temperature of 600 ° C. to 800 ° C. desirable.
계속해서, 도 3c에 도시된 바와 같이 식각방지막(18) 상에 콘택 형성을 위한 포토레지스트 패턴(도시하지 않음)을 형성한 다음, 이를 식각마스크로 한 선택적 식각 공정을 통해 플러그(16) 표면을 노출시키는 콘택홀(19)을 형성한다.Subsequently, as shown in FIG. 3C, a photoresist pattern (not shown) for forming a contact is formed on the etch stop layer 18, and then the surface of the plug 16 is formed by a selective etching process using the etch mask as an etch mask. A contact hole 19 for exposing is formed.
이어서, 비트라인 또는 스토리지노드 형성을 위한 전도층 증착을 위한 전세정 공정을 실시하는 바, 완충산화막식각제를 이용하여 전술한 콘택홀(19) 형성에 따른 식각 잔유물을 제거한다.이 때, 식각률이 비교적 낮은 식각방지막(18)에 의해 유동성 절연막(17)의 손실을 방지할 수 있어, 콘택 상부의 넓어지는 현상이 억제된다.Subsequently, a pre-cleaning process for depositing a conductive layer for forming a bit line or a storage node is performed to remove the etching residues due to the formation of the contact hole 19 using a buffer oxide film etchant. This relatively low etching prevention film 18 can prevent the loss of the fluid insulating film 17, thereby suppressing the phenomenon of widening the upper portion of the contact.
전술한 본 발명은, 유동성 절연막을 층간절연막으로 사용하는 경우 콘택 형성시 유동성 절연막 상부에 SiH4-산화막 계열의 절연막을 형성함으로써, 비트라인 등의 형성을 위한 전세정 공정에서 습식 케미컬에 의한 유동성 절연막의 손실로 인하여 발생하는 콘택 상부의 넓어짐 현상을 방지할 수 있음을 실시예를 통해 알아 보았다.In the present invention described above, when the fluid insulating film is used as an interlayer insulating film, a SiH 4 -oxide-based insulating film is formed on the fluid insulating film at the time of contact formation, whereby the fluid insulating film by the wet chemical in the pre-cleaning process for the formation of the bit line, etc. It was found through the examples that the spreading phenomenon of the upper portion of the contact caused by the loss of the can be prevented.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 본 발명은, 콘택 오픈 결함을 방지함으로써 소자의 불량 확률을 감소시킬 수 있어, 궁극적으로 반도체 소자의 수율을 향상시킬 수 있는 탁월한 효과를 기대할 수 있다.As described above, the present invention can reduce the probability of failure of a device by preventing contact open defects, so that an excellent effect of ultimately improving the yield of a semiconductor device can be expected.
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