KR100513367B1 - Method for Forming Interlayer Insulating Film of Semiconductor Device - Google Patents
Method for Forming Interlayer Insulating Film of Semiconductor Device Download PDFInfo
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- KR100513367B1 KR100513367B1 KR10-2003-0050924A KR20030050924A KR100513367B1 KR 100513367 B1 KR100513367 B1 KR 100513367B1 KR 20030050924 A KR20030050924 A KR 20030050924A KR 100513367 B1 KR100513367 B1 KR 100513367B1
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02065—Cleaning during device manufacture during, before or after processing of insulating layers the processing being a planarization of insulating layers
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
Abstract
본 발명은 반도체 소자의 층간 절연막 형성 방법에 관한 것으로, 보다 상세하게는 반도체 소자의 제조 시, 갭 필(gap-fill) 능력이 우수한 플로우-필(flow-fill) 물질을 이용하여 제 1 층간 절연막을 형성한 다음, 그 상부에 제 2 층간 절연막을 형성함으로써, 게이트 전극 사이에 보이드(void) 형성을 막아 후속 랜딩 플러그 폴리(landing plug poly) 형성 공정 시에 플러그 브리지(bridge)가 발생되는 것을 방지할 수 있다.The present invention relates to a method for forming an interlayer insulating film of a semiconductor device, and more particularly, a first interlayer insulating film using a flow-fill material having excellent gap fill capability when manufacturing a semiconductor device. And then forming a second interlayer insulating film thereon, thereby preventing voids from forming between the gate electrodes to prevent the occurrence of plug bridges during subsequent landing plug poly forming processes. can do.
Description
본 발명은 반도체 소자의 층간 절연막 형성 방법에 관한 것으로, 보다 상세하게는 반도체 소자의 제조 시, 갭 필(gap-fill) 능력이 우수한 플로우-필(flow-fill) 물질을 이용하여 제 1 층간 절연막을 형성한 다음, 그 상부에 제 2 층간 절연막을 형성함으로써, 게이트 전극 사이에 보이드(void) 형성을 막아 후속 랜딩 플러그 폴리(landing plug poly) 형성 공정 시에 플러그 브리지(bridge)가 발생되는 것을 방지할 수 있다.The present invention relates to a method for forming an interlayer insulating film of a semiconductor device, and more particularly, a first interlayer insulating film using a flow-fill material having excellent gap fill capability when manufacturing a semiconductor device. And then forming a second interlayer insulating film thereon, thereby preventing voids from forming between the gate electrodes to prevent the occurrence of plug bridges during subsequent landing plug poly forming processes. can do.
현재 반도체 소자가 점점 더 고집적화 및 고밀도화 됨에 따라, 패턴 넓이(width) 및 패턴과 패턴 사이의 간격(space)은 현저하게 감소되는 반면, 여러 층의 도전체층을 적층시켜 패턴을 높이 형성하기 때문에, 패턴의 아스펙트비(aspect ratio)는 증가되었다. As semiconductor devices become more and more dense and dense at present, the pattern width and the space between the pattern and the pattern are remarkably reduced, whereas the pattern is formed by stacking multiple layers of conductor layers to form a pattern. The aspect ratio of was increased.
이와 같이, 반도체 소자의 디자인 룰(design rule)이 감소되면서 패턴의 아스펙트비가 증가하였기 때문에, 게이트 전극 사이의 공간을 매립하여 절연 효과 및 후속 공정에 의한 소자의 변형을 방지할 수 있는 갭 필 공정을 수행하는 것이 점점 더 어려워졌다.As described above, since the aspect ratio of the pattern increases as the design rule of the semiconductor device decreases, a gap fill process that can fill the space between the gate electrodes to prevent the deformation of the device due to the insulation effect and subsequent processes. It became more and more difficult to carry out.
상기 갭 필 공정은 일반적인 공정으로, 0.3㎛ 이하의 반도체 소자의 제조 시에 게이트 전극의 전면에 보로포스포실리케이트(borophosphosilicate glass; BPSG)를 형성한 후, 어닐링(annealing)공정으로 상기 BPSG 막을 플로우 시켜 게이트 전극 사이의 공간을 매립하는 방법이다. The gap fill process is a general process, in which a borophosphosilicate glass (BPSG) is formed on a front surface of a gate electrode when a semiconductor device having a thickness of 0.3 μm or less is formed, and then the BPSG film is flowed by an annealing process. It is a method of filling a space between gate electrodes.
이때, 상기 BPSG막은 갭 필 특성이 낮기 때문에, 패턴의 아스팩트 비가 높은 경우, 어닐링 공정만으로는 완전한 갭 필 공정 효과를 얻을 수 없다. 그래서, 공정이 완료 된 후 게이트 전극 사이에는 보이드가 형성되고, 후속 랜딩 플러그 폴리(landing plug poly) 형성 공정 시에 폴리가 상기 보이드의 내부로 매립되어 플러그의 브릿지(bridge)가 유발된다. At this time, since the BPSG film has a low gap fill property, when the aspect ratio of the pattern is high, a full gap fill process effect cannot be obtained only by the annealing process. Thus, voids are formed between the gate electrodes after the process is completed, and the poly is embedded in the voids in a subsequent landing plug poly forming process, causing a bridge of the plug.
도 1a 내지 도 1d는 종래 방법을 도시한 공정도이다.1A to 1D are process diagrams showing a conventional method.
도 1a를 참조하면, 소자분리막(3)이 구비된 반도체 기판(1) 상부에 다결정 실리콘층(5), 게이트 전극용 도전체층(7) 및 하드마스크 질화막(9)을 순차적으로 형성한다.Referring to FIG. 1A, the polycrystalline silicon layer 5, the gate electrode conductor layer 7, and the hard mask nitride layer 9 are sequentially formed on the semiconductor substrate 1 having the device isolation layer 3.
도 1b를 참조하면, 하드마스크 질화막(9), 게이트 전극용 도전체층(7) 및 다결정 실리콘층(5)에 대한 선택적 식각 공정을 수행하여, 하드마스크 질화막 패턴(9a), 게이트 전극용 도전체 패턴(7a) 및 다결정 실리콘 패턴(5a)이 순차적으로 형성되어 있는 게이트 전극(10)을 형성한다.Referring to FIG. 1B, a selective etching process is performed on the hard mask nitride film 9, the gate electrode conductor layer 7, and the polycrystalline silicon layer 5 to perform the hard mask nitride film pattern 9a and the gate electrode conductor. The gate electrode 10 in which the pattern 7a and the polycrystalline silicon pattern 5a are sequentially formed is formed.
그리고, 게이트 전극(10)을 포함하는 결과물 전면에 질화막(미도시)을 형성한 다음 식각하여, 질화막 스페이서(11)를 형성한다.In addition, a nitride film (not shown) is formed on the entire surface of the resultant including the gate electrode 10 and then etched to form the nitride film spacer 11.
도 1c를 참조하면, 게이트 전극(10) 및 질화막 스페이서(11)를 포함하는 결과물의 전면에 BPSG막을 이용하여 층간 절연막(15)을 형성한 다음, BPSG막을 플로우시키기 위하여 어닐링 공정을 수행한다.Referring to FIG. 1C, an interlayer insulating film 15 is formed on the entire surface of the resultant including the gate electrode 10 and the nitride film spacer 11 by using a BPSG film, and then an annealing process is performed to flow the BPSG film.
이때, 상기 층간 절연막은 하드마스크 질화막 패턴(9a)상부로부터 4000∼7000Å의 두께로 형성하고, 상기 어닐링 공정은 스팀(steam) 분위기하의 700∼900℃ 온도에서 20∼40분 동안 수행된다.In this case, the interlayer insulating film is formed to have a thickness of 4000 to 7000 kPa from the top of the hard mask nitride film pattern 9a, and the annealing process is performed for 20 to 40 minutes at a temperature of 700 to 900 ° C. under a steam atmosphere.
도 1d를 참조하면, 하드마스크 질화막 패턴(9a)이 노출될 때까지 BPSG막(15)에 대한 CMP 공정을 수행함으로써, 게이트 전극 사이의 공간에 층간 절연막(15)을 형성한다.Referring to FIG. 1D, an interlayer insulating film 15 is formed in a space between gate electrodes by performing a CMP process on the BPSG film 15 until the hard mask nitride film pattern 9a is exposed.
이때, 상기 도 1c의 어닐링 공정을 수행할 때, BPSG막의 낮은 갭 필 특성으로 인하여, 도 1d에 도시한 바와 같이 게이트 전극(10) 사이의 층간 절연막(15) 내부에 보이드(17)가 형성된다. At this time, when the annealing process of FIG. 1C is performed, voids 17 are formed in the interlayer insulating layer 15 between the gate electrodes 10 due to the low gap fill characteristic of the BPSG film, as shown in FIG. 1D. .
이와 같이, 상기 종래 방법에 따른 층간 절연막 형성 공정에서는 BPSG 막을 플로우 시키기 위한 열공정 수행 시에, 게이트 물질의 열 팽창 계수 차이에 의한 스트레스(stress)가 증가하고, 게이트 형성을 위해 주입(doped)된 입자들의 확산으로 트랜지스터(transistor)의 특성이 저하되는 등의 BPSG 막에 의한 서머 버짓(thermal burget)의 영향이 발생되며, 층간 절연막 내부의 보이드 발생으로 후속 랜딩 플러그 폴리 형성 공정 시에 플러그의 브릿지를 발생시켜 불안정한 소자가 제조되므로, 소자의 수율이 감소된다.As described above, in the interlayer insulating film forming process according to the conventional method, when the thermal process is performed to flow the BPSG film, stress due to a difference in the coefficient of thermal expansion of the gate material increases, and is implanted to form the gate. The diffusion of particles causes the effects of thermal budgets caused by the BPSG film, such as deterioration of the characteristics of the transistor, and the generation of voids in the interlayer insulating film. By generating an unstable device, the yield of the device is reduced.
이에 본 발명자들은 상기와 같은 문제점을 해결하기 위하여, 서머 버짓 및 보이드의 발생 없이 게이트 전극 사이를 매립할 수 있는 층간 절연막 형성 방법을 제공하는 것을 목적으로 한다. Accordingly, an object of the present invention is to provide a method for forming an interlayer insulating film that can be buried between the gate electrode without the generation of thermal budget and voids.
상기 목적을 달성하기 위하여 본 발명에서는 게이트 전극 사이에 플로우 필을 이용한 제 1 층간 절연막을 형성한 다음, 그 상부에 제 2 층간 절연막을 형성함으로써, 안정한 반도체 소자를 제조할 수 있는 층간 절연막 형성 방법을 제공한다.In order to achieve the above object, the present invention provides a method for forming an interlayer insulating film capable of manufacturing a stable semiconductor device by forming a first interlayer insulating film using a flow fill between gate electrodes and then forming a second interlayer insulating film thereon. to provide.
이하 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail.
소자분리막이 구비된 반도체 기판 상부에 게이트 전극을 형성하는 단계;Forming a gate electrode on the semiconductor substrate including the device isolation layer;
상기 게이트 전극 측면에 질화막 스페이서를 형성하는 단계;Forming a nitride film spacer on a side of the gate electrode;
상기 게이트 전극 및 질화막 스페이서를 포함하는 결과물 전면에 플로우 필 물질을 이용한 제 1 층간 절연막을 형성하는 단계; 베이크 공정을 수행하여 상기 제 1 층간 절연막을 젤 상태의 SiOx로 형성하는 단계;상기 게이트 전극 상부가 노출될 때까지, 상기 제 1 층간 절연막에 대한 CMP 공정을 수행하는 단계;Forming a first interlayer insulating film using a flow fill material on the entire surface of the resultant material including the gate electrode and the nitride film spacer; Performing a baking process to form the first interlayer insulating layer as SiO x in a gel state; performing a CMP process on the first interlayer insulating layer until the upper portion of the gate electrode is exposed;
삭제delete
상기 제 1 층간 절연막에 대한 어닐링 공정을 수행하는 단계; 및Performing an annealing process on the first interlayer insulating film; And
상기 어닐링 된 제 1 층간 절연막 상부에 제 2 층간 절연막을 형성하는 단계를 포함하는 반도체 소자의 층간 절연막 형성 방법을 제공한다.It provides a method for forming an interlayer insulating film of a semiconductor device comprising the step of forming a second interlayer insulating film on the annealed first interlayer insulating film.
이때, 상기 게이트 전극은 다결정 실리콘 패턴, 게이트 전극용 도전체 패턴 및 하드마스크 질화막 패턴이 순차적으로 형성된 것이 바람직하다.In this case, the gate electrode may be formed of a polycrystalline silicon pattern, a conductor pattern for the gate electrode, and a hard mask nitride layer pattern sequentially.
상기 플로우-필 물질은 반응기 내부로 SiH4+H2O2의 혼합 기체를 가하면 Si(OH)4 상태로 웨이퍼에 흡착, 응축되었다가, 베이킹 공정을 수행하는 동안 수분이 제거되어 젤(gel) 상태의 SiOx로 형성되면서, 패턴 사이의 좁은 공간으로 흘러 매립한다. 이때, 상기 젤 상태의 SiOx는 플로우 특성이 스핀 온 글라스(spin on glass)와 같이 아주 우수하기 때문에, 0.1㎛ 이하의 좁은 공간에서도 보이드 없이 층을 매립할 수 있다.The flow-fill material is adsorbed and condensed on the wafer in Si (OH) 4 state by adding a mixed gas of SiH 4 + H 2 O 2 into the reactor. Formed with SiO x in the state, it flows into a narrow space between patterns and is buried. In this case, since SiO x of the gel state is very excellent in flow characteristics such as spin on glass, the layer may be buried without voids even in a narrow space of 0.1 μm or less.
또한, 상기 제 1 층간 절연막을 형성한 다음, 어닐링 공정 없이 베이킹 공정만 수행하고, 후속 CMP 공정을 수행한다. 그 결과, 상기 제 1 층간 절연막이 하드마스크 질화막 패턴 상부에 고밀도화로 형성되는 것을 방지하므로, 하드마스크 질화막에 대한 연마 선택비를 증가시킬 수 있다.In addition, after the first interlayer insulating film is formed, only a baking process is performed without an annealing process and a subsequent CMP process is performed. As a result, since the first interlayer insulating film is prevented from being densely formed on the hard mask nitride film pattern, the polishing selectivity for the hard mask nitride film can be increased.
이하, 첨부 도면을 이용하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a를 참조하면, 소자분리막(23)이 구비된 반도체 기판(21) 상부에 다결정 실리콘막(25), 게이트 전극용 도전체층(27) 및 하드마스크 질화막(29)을 순차적으로 형성한다.Referring to FIG. 2A, the polycrystalline silicon film 25, the gate electrode conductor layer 27, and the hard mask nitride film 29 are sequentially formed on the semiconductor substrate 21 provided with the device isolation film 23.
이때, 상기 게이트 전극용 도전체층은 도핑 실리콘, 폴리 실리콘, 텅스텐(W), 텅스텐 나이트라이드(WN), 텅스텐 실리사이드(WSiX), 또는 티타늄 실리사이드(TiSiX) 등을 이용하여 형성할 수 있다.In this case, the conductor layer for the gate electrode may be formed using doped silicon, polysilicon, tungsten (W), tungsten nitride (WN), tungsten silicide (WSi X ), or titanium silicide (TiSi X ).
또한, 상기 하드마스크 질화막은 2000∼4000Å의 두께로 형성하는 것이 바람직하다.In addition, the hard mask nitride film is preferably formed to a thickness of 2000 to 4000 kPa.
도 2b를 참조하면, 다결정 실리콘막(25), 게이트 전극용 도전체층(27) 및 하드마스크 질화막(29)에 대한 선택적 식각공정을 수행하여, 다결정 실리콘 패턴 (25a), 게이트 전극용 도전체 패턴(27a) 및 하드마스크 질화막 패턴(29a)이 순차적으로 형성된 게이트 전극(30)을 형성한다.Referring to FIG. 2B, a selective etching process is performed on the polycrystalline silicon film 25, the gate electrode conductor layer 27, and the hard mask nitride film 29 to perform the polycrystalline silicon pattern 25a and the conductor pattern for the gate electrode. A gate electrode 30 in which the 27a and the hard mask nitride film pattern 29a are sequentially formed is formed.
그 다음, 게이트 전극(30)을 포함한 결과물 전면에 하드마스크 질화막 패턴(29a)으로부터 200∼300Å의 두께의 질화막을 형성한 후, 식각하여 질화막 스페이서(31)를 형성한다. Subsequently, a nitride film having a thickness of 200 to 300 으로부터 is formed from the hard mask nitride film pattern 29a on the entire surface including the gate electrode 30 and then etched to form the nitride film spacer 31.
이때, 상기 스페이서를 산화막으로 형성하는 경우 게이트 전극용 도전체층으로 형성한 텅스텐 실리사이드의 산화가 발생될 수 있으므로, 질화막을 이용하여 형성하는 것이 바람직하다.In this case, when the spacer is formed of an oxide film, oxidation of tungsten silicide formed of the conductor layer for the gate electrode may occur, so that the spacer is formed using a nitride film.
도 2c를 참조하면, 게이트 전극(30) 및 질화막 스페이서(31)를 포함한 결과물 전면에 대하여 플로우 필 물질을 이용한 제 1 층간 절연막(33)을 형성한다.Referring to FIG. 2C, the first interlayer insulating layer 33 using the flow fill material is formed on the entire surface of the resultant including the gate electrode 30 and the nitride film spacer 31.
상기 플로우 필 물질을 이용한 제 1 층간 절연막은 LP CVD(low pressure-chemical vapor deposition) 방법으로로 형성되는데, 구체적으로 약 0.1∼3 torr의 반응기 압력과 -20∼+20℃의 기판 분위기하에서 10∼300sccm 유량의 SiH4와 0.1∼3g/min 유량의 H2O2 가스를 혼합한 SiH4+H2O2의 혼합 기체를 가하여 Si(OH)4 상태로 웨이퍼에 흡착시킨다.The first interlayer insulating film using the flow fill material is formed by a low pressure-chemical vapor deposition (LP CVD) method. Specifically, the first interlayer insulating film is formed by a low pressure-chemical vapor deposition (LP CVD) method. A mixed gas of SiH 4 + H 2 O 2 mixed with SiH 4 at a flow rate of 300 sccm and H 2 O 2 gas at a flow rate of 0.1 to 3 g / min is added and adsorbed onto the wafer in a Si (OH) 4 state.
그리고, 300∼400℃의 베이킹 공정으로 젤(gel) 상태의 SiOx를 형성하여, 패턴 사이의 좁은 공간을 매립한다.Then, SiO x in a gel state is formed by a baking process at 300 to 400 ° C. to fill a narrow space between the patterns.
이때, 상기 베이킹 공정은 종래 BPSG막을 형성할 때 수행하던 어닐링 공정에 비하여 대략 200℃ 이상 낮은 온도에서 수행되는 것이 바람직하다. 또한, 종래 수행되던 어닐링 공정을 수행하지 않고 베이킹 공정만을 수행하여 제 1 층간 절연막을 형성하므로, 하드마스크 질화막 패턴에 대한 연마 선택비를 높일 수 있다.At this time, the baking process is preferably performed at a temperature lower than about 200 ℃ compared to the annealing process that was performed when the conventional BPSG film is formed. In addition, since the first interlayer insulating film is formed by performing only the baking process without performing the annealing process, which is conventionally performed, the polishing selectivity for the hard mask nitride layer pattern may be increased.
상기 플로우 필 물질을 이용한 제 1 층간 절연막은 게이트 전극이 완전히 매립되도록 하드마스크 질화막 패턴(29a) 상부로부터 3000∼7000Å, 바람직하게는 3000∼5000Å의 두께로 형성한다.The first interlayer insulating film using the flow fill material is formed to have a thickness of 3000 to 7000 kPa, preferably 3000 to 5000 kPa from the top of the hard mask nitride film pattern 29a so as to completely fill the gate electrode.
도 2d를 참조하면, 하드마스크 질화막을 식각 방지막으로 제 1 층간 절연막(33)에 대한 CMP 공정을 수행한다. Referring to FIG. 2D, a CMP process is performed on the first interlayer insulating layer 33 using the hard mask nitride layer as an etch stop layer.
이때, 상기 CMP 공정은 산화막에 대해 높은 연마 선택비를 가지는 산화막용 CMP 슬러리를 사용해야 하드마스크 질화막의 손상이 적다.In this case, in the CMP process, the damage of the hard mask nitride film is less when the CMP slurry for oxide film having a high polishing selectivity with respect to the oxide film is used.
즉, 상기 산화막용 CMP 슬러리는 연마제로 세리아(CeO2)를 사용하고, 첨가제로 폴리카르복실레이트(polycarboxylate), 폴리아크릴산염(polyacryllic acid salt) 또는 폴리아미드(polyamide) 계의 유기물을 포함하는 pH 6∼8의 슬러리인 것이 바람직한데, 이때, 상기 슬러리의 산화막 : 질화막의 연마 선택비는 40 : 1 ∼ 200 : 1이므로, 하드마스크 질화막 상부의 손실을 최소화 할 수 있다.That is, the CMP slurry for the oxide film uses ceria (CeO 2 ) as an abrasive and a pH including polycarboxylate, polyacryllic acid salt, or polyamide-based organic material as an additive. It is preferable that the slurry is 6 to 8, wherein the polishing selectivity of the oxide film to the nitride film is 40: 1 to 200: 1, so that the loss of the upper portion of the hard mask nitride film can be minimized.
또한, 상기 CMP 공정 후, 연마 잔여물을 제거하기 위하여 HF를 이용한 습식 세정 공정을 스크러빙(scrubbing) 방식으로 수행하는 것이 바람직하다. In addition, after the CMP process, it is preferable to perform a scrubbing method of the wet cleaning process using HF to remove the polishing residue.
도 2e를 참조하면, 노출된 하드마스크 질화막 패턴(29a) 상부 및 제 1 층간 절연막(33)에 대한 어닐링 공정을 수행하여 제 1 층간 절연막(33)의 밀도를 높인다.Referring to FIG. 2E, an annealing process is performed on the exposed hard mask nitride layer pattern 29a and the first interlayer insulating layer 33 to increase the density of the first interlayer insulating layer 33.
상기 어닐링 공정은 N2 분위기의 로(furnace)에서 450∼750℃의 온도로 20∼40분 수행하는 것이 바람직한데, 이때, 상기 도 2d에 도시한 바와 같이 하드마스크 질화막 패턴(29a)이 노출될 때까지, CMP 공정을 수행하기 때문에, 후속 어닐링 공정 시에 제 1 층간 절연막(33) 내부에 잔존하던 수분이 마저 제거되면서 여전히 Si(OH)4 상태로 존재하던 플로우 필 물질이 SiO x 상태로 산화(oxidation)되면서 제 1 층간 절연막의 부피가 대략 10% 이상 수축하여 고밀도화(densification) 된다.The annealing process is preferably performed at a temperature of 450 to 750 ° C. for 20 to 40 minutes in a furnace of N 2 atmosphere. At this time, as shown in FIG. 2D, the hard mask nitride layer pattern 29a may be exposed. Until the CMP process is performed, the flow fill material, which is still present in the Si (OH) 4 state, is oxidized to the SiO x state while the moisture remaining in the first interlayer insulating layer 33 is removed even during the subsequent annealing process. During the oxidation, the volume of the first interlayer insulating film shrinks by about 10% or more, thereby densification.
또한, 본 발명의 어닐링 공정은 종래 BPSG막을 형성할 때 수행하던 어닐링 공정에 비하여 대략 200℃ 이상 낮은 온도에서 수행되기 때문에, 종래 발생되던 서머 버짓의 영향을 방지할 수 있다. In addition, since the annealing process of the present invention is performed at a temperature lower than approximately 200 ° C. as compared with the annealing process performed when the conventional BPSG film is formed, it is possible to prevent the influence of the thermal budget generated conventionally.
도 2f를 참조하면, 노출된 하드마스크 질화막 패턴(29a) 상부 및 제 1 층간 절연막(33) 전면에 대하여 제 2 층간 절연막(35)을 형성한 다음, CMP 공정을 수행하여 평탄화 한다.Referring to FIG. 2F, the second interlayer insulating layer 35 is formed on the exposed hard mask nitride layer pattern 29a and the entire surface of the first interlayer insulating layer 33, and then planarized by performing a CMP process.
상기 제 2 층간 절연막은 고밀도 플라즈마(high density plasma; HDP) 산화막으로 이루어지면, 하드마스크 질화막 패턴(29a) 상부로부터 500∼3000Å, 바람직하게는 500∼2000Å의 두께로 형성하는 것이 바람직하다.When the second interlayer insulating film is made of a high density plasma (HDP) oxide film, the second interlayer insulating film is preferably formed to have a thickness of 500 to 3000 mW, preferably 500 to 2000 mW from the top of the hard mask nitride film pattern 29a.
이때, 상기 제 2 층간 절연막 형성 과정은 SiH4 및 O2가스를 이용한 증착 공정과 Ar 식각 가스를 이용한 이방성(anisotropic) 식각 공정을 반복하면서 평탄화된 실리콘(SiO2)막이 형성되도록 하는 것이 바람직하다.In this case, the forming of the second interlayer insulating film may be performed such that the planarized silicon (SiO 2 ) film is formed while repeating the deposition process using SiH 4 and O 2 gas and the anisotropic etching process using Ar etching gas.
또한, 상기 방법으로 형성된 제 2 층간 절연막은 후속 공정인 랜딩 플러그 콘택 식각 공정이나, LPP를 형성하기 위한 식각 공정 시에 발생할 수 있는 게이트 옥사이드의 디싱(dishing) 형상을 감소시키기에 충분한 마진의 두께를 갖는다. In addition, the second interlayer insulating film formed by the above method has a margin thickness sufficient to reduce the dishing shape of the gate oxide that may occur during the subsequent landing plug contact etching process or the etching process for forming LPP. Have
이상에서 살펴본 바와 같이, 본 발명은 게이트 전극 사이의 갭을 매립하기 위하여 갭 필 특성이 높은 플로우 필 물질을 이용하여 제 1 층간 절연막을 형성한 다음, 어닐링 공정 없이 제 1 층간 절연막 상부에 제 2 층간 절연막을 형성함으로써, 층간 절연막 내부에 보이드가 발생되는 것을 막고, 후속 랜딩 플러그 폴리 형성 시에 브리지를 방지할 수 있어 안정한 반도체 소자를 형성할 수 있다.As described above, in order to fill the gap between the gate electrodes, the present invention forms a first interlayer insulating film using a flow fill material having a high gap fill property, and thereafter, a second interlayer is formed on the first interlayer insulating film without an annealing process. By forming the insulating film, it is possible to prevent the generation of voids in the interlayer insulating film and to prevent the bridge during the subsequent landing plug poly formation, thereby forming a stable semiconductor element.
도 1a 내지 도 1d는 종래 반도체 소자의 층간 절연막 형성 방법에 따른 공정도.1A to 1D are flowcharts illustrating a method of forming an interlayer insulating film of a conventional semiconductor device.
도 2a 내지 도 2f는 본 발명의 반도체 소자의 층간 절연막 형성 방법에 따른 공정도.2A to 2F are flowcharts illustrating a method for forming an interlayer insulating film of a semiconductor device of the present invention.
< 도면의 주요 부분에 대한 간단한 설명 ><Brief description of the main parts of the drawing>
1, 21 : 실리콘 기판 3, 23 : 소자분리막1, 21: silicon substrate 3, 23: device isolation film
5, 25 : 다결정 실리콘층 5a, 25a : 다결정 실리콘 패턴5, 25 polycrystalline silicon layer 5a, 25a: polycrystalline silicon pattern
7, 27 : 도전체층 7a, 27a : 도전체 패턴7, 27: conductor layer 7a, 27a: conductor pattern
9, 29 : 하드마스크 질화막 9a, 29 : 하드마스크 질화막 패턴9, 29: hard mask nitride film 9a, 29: hard mask nitride film pattern
10, 30 : 게이트 전극 11, 31 : 스페이서10, 30: gate electrode 11, 31: spacer
15 : BPSG막을 이용한 층간 절연막15: interlayer insulation film using BPSG film
17 : 보이드(void)17: void
33 : 플로우 필(flow-fill)을 이용한 제 1 층간 절연막33: first interlayer insulating film using flow-fill
35 : 제 2 층간 절연막35: second interlayer insulating film
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