KR100673772B1 - Method of forming a bit line contact plug using an insulation spacer - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 31
- 125000006850 spacer group Chemical group 0.000 title claims abstract description 17
- 238000009413 insulation Methods 0.000 title 1
- 239000002184 metal Substances 0.000 claims abstract description 37
- 229910052751 metal Inorganic materials 0.000 claims abstract description 37
- 238000000151 deposition Methods 0.000 claims abstract description 24
- 150000004767 nitrides Chemical class 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 12
- 238000009792 diffusion process Methods 0.000 claims abstract description 12
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 12
- 239000010703 silicon Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 230000004888 barrier function Effects 0.000 claims abstract description 6
- 239000004065 semiconductor Substances 0.000 claims abstract description 3
- 238000004544 sputter deposition Methods 0.000 claims description 7
- DASQIKOOFDJYKA-UHFFFAOYSA-N CCIF Chemical compound CCIF DASQIKOOFDJYKA-UHFFFAOYSA-N 0.000 claims description 3
- 229910020776 SixNy Inorganic materials 0.000 claims description 3
- 229910008482 TiSiN Inorganic materials 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 230000002265 prevention Effects 0.000 claims 1
- 230000008021 deposition Effects 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000007517 polishing process Methods 0.000 description 3
- 239000011800 void material Substances 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 229910008484 TiSi Inorganic materials 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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Abstract
본 발명에 따른 절연막 스페이서를 이용한 비트라인 콘택 플러그 형성 방법은 비트라인과 같은 반도체 요소가 형성된 실리콘 기판상의 절연막의 일부를 제거하여 비트라인 콘택을 형성하는 단계; LP CVD 계열 산화막 또는 질화막을 전체 구조 상부에 증착한 다음, 전면 에치하는 단계; 전체 구조 상부에 확산 방지 금속막을 증착하는 단계; 상기 금속막 상부에 금속 플러그막을 증착하고 전면 에치하여 보이드 없는 콘택 플러그를 형성하는 단계를 포함하여 이루어진다.
A method of forming a bit line contact plug using an insulating film spacer according to the present invention includes forming a bit line contact by removing a portion of an insulating film on a silicon substrate on which a semiconductor element such as a bit line is formed; Depositing an LP CVD-based oxide film or nitride film over the entire structure, and then etching the entire surface; Depositing a diffusion barrier metal film over the entire structure; And depositing a metal plug layer on the metal layer and etching the entire surface to form a void-free contact plug.
콘택 플러그Contact plug
Description
도 1a 내지 도 1d는 종래 콘택플러그 형성방법을 설명하기 위한 단면도.1A to 1D are cross-sectional views illustrating a conventional method for forming a contact plug.
도 2a 내지 도 2d는 본 발명에 따른 절연막 스페이서를 이용한 비트라인 콘택 플러그 형성 방법을 설명하기 위한 단면도.2A to 2D are cross-sectional views illustrating a method of forming a bit line contact plug using an insulating film spacer according to the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
10: 실리콘 기판 1: 게이트 산화막10: silicon substrate 1: gate oxide film
2: 게이트 배선막 3: 버퍼 옥사이드 막2: gate wiring film 3: buffer oxide film
4: 마스크 질화막
4: mask nitride film
본 발명은 절연막 스페이서를 이용한 비트라인 콘택 플러그 형성 방법에 관한 것으로, 특히 0.13㎛ 기술(technology)이하의 디바이스에서 산화막 또는 질화막 스페이서를 이용한 비트라인 콘택 금속 플러그 형성을 가능하게 한 절연막 스페이서를 이용한 비트라인 콘택 플러그 형성 방법에 관한 것이다. The present invention relates to a method for forming a bit line contact plug using an insulating film spacer, and more particularly, to a bit line using an insulating film spacer enabling the formation of a bit line contact metal plug using an oxide film or a nitride film spacer in a device having a technology of 0.13 µm or less. A method for forming a contact plug.
종래의 일반적인 비트라인 콘택 금속 플러그 형성 방법은 도 1a 내지 도 1d에서와 같이 랜딩 플러그 폴리(Landing Plug Poly) 연마후 워드라인 배선간 공간이 좁은 부분에 갭 파일 층(gap-fill layer)(비트라인 콘택 절연막)을 증착한 다음, 비트라인 콘택 마스크를 이용하여 실리콘 기판(silicon substrate)과 워드라인 배선으로 연결되도록 콘택 에치한 후, 실리콘 기판에 잔류하는 불순물을 제거하는 세정 공정을 진행하면, gap-fill layer에 비해 워드라인 절연막이 식각 속도가 더 빠르기 때문에 네가티브 슬로프(negative slope)가 형성되며, 이는 후속 확산 방지 금속막과 콘택 금속 플러그막 증착시 보이드(void)를 유발하여 소자 특성을 악화시킨다. A conventional method for forming a bit line contact metal plug is a gap-fill layer (bit line) in a narrow space between word lines after a landing plug poly polishing, as shown in FIGS. 1A to 1D. Contact insulating layer), and then contact etched using a bit line contact mask to connect the silicon substrate to the word line wiring, and then a cleaning process for removing impurities remaining in the silicon substrate is performed. Since the word line insulating layer has a faster etching rate than the fill layer, a negative slope is formed, which causes voids during subsequent diffusion preventing metal layer and contact metal plug layer deposition, thereby deteriorating device characteristics.
도 1a 내지 도 1d 는 종래 기술을 설명하기 위한 단면도이다. 1A to 1D are cross-sectional views for explaining the prior art.
도 1a 에 도시한 바와 같이, 실리콘 기판(10)상에 게이트 산화막(1), 게이트 배선막(2), 버퍼 옥사이드막(3) 및 마스크 질화막(4)이 형성된다. 전체 구조 상부에 절연막이 증착된 후 연마공정을 실시한다. 비트라인 및 캐패시터 하부 플러그를 형성하기 위한 랜딩 플러그 폴리(Landing Plug Poly) 연마 공정시 워드라인 배선간 공간이 좁은 지역에서 연마 공정 및 후세정 공정으로 인한 워드라인 절연막의 손실이 도 1a 의 (5)와 같이 매우 크게 발생하며, 이러한 국부 손실은 후속 콘택 금속 플러그막 에치백(etchback) 공정 및 비트라인 배선 패터닝 공정에서 불순물을 국부적으로 잔류시키는 역할을 하여 소자 결함(fail)을 유도하므로 반드시 제거되어야만 하는데, 이를 위하여 갭 파일 특성이 우수하고, 실리콘 기판(silicon substrate)에 열 버짓(thermal budget)이 작은 조건을 만족하는 저농도 BPSG를 증착한 다음, 780℃ 이하에서 열처리하면 도 1b 의 (7)과 같이 비트라인 콘택 절연막이 형성된다. 도 1c를 참조하면 비트라인 콘택 마스크를 이용하여 주변회로 지역의 실리콘 기판과 워드라인 배선으로 에치하여 콘택홀을 형성한다. 이때 워드라인 절연막과 비트라인 콘택 절연막간 식각 속도 차이로 인하여 비트라인 콘택 절연막보다 워드라인 절연막이 더 식각되어 콘택홀의 상부폭보다 하부 폭이 넓게 형성된다. 그리고 비트라인 콘택 플러그 형성 물질로 확산방지 금속막과 금속 플러그막을 증착하면 도 1d 의 (12)와 같은 보이드가 발생하며, 이와같은 보이드는 콘택 플러그의 저항을 증가시켜 소자 특성을 크게 악화시키는 역할을 한다.As shown in FIG. 1A, a gate oxide film 1, a gate wiring film 2, a buffer oxide film 3, and a mask nitride film 4 are formed on the
따라서 본 발명은 상기와 같은 비트라인 콘택 금속 플러그 형성 공정에서 발생하는 금속 플러그막 증착시 보이드 문제를 해결하기 위해 랜딩 플러그 폴리(L anding Plug Poly) 연마후, 워드라인 절연막과 배선 상부에서 비트라인 콘택 마스크/에치하여 실리콘 기판과 워드라인 배선을 오픈(open)시키고, 갭 파일 및 스텝 커버리지(step coverage) 특성이 우수한 LP CVD 계열 산화막 또는 질화막을 증착하고 에치하여 워드라인 배선간 공간이 좁은 지역에는 갭필(gap-fill)이 이루어지면서 콘택내 스페이서를 형성함으로써 워드라인 절연막과 갭필 층간 식각 속도 차이로 인한 네가티브 슬로프(negative slope) 문제를 근본적으로 해결함으로써 후속 금속 플러그막 증착시 보이드 없는 콘택 플러그를 형성 하는 방법을 제공하는데 그 목적이 있다. Therefore, the present invention is to solve the void problem in the deposition of the metal plug film generated in the bit line contact metal plug forming process as described above, after grinding the landing plug poly (Pond), the bit line contact on the word line insulating film and the wiring Open the silicon substrate and word line wiring by mask / etching, and deposit and etch an LP CVD-based oxide or nitride film having excellent gap pile and step coverage characteristics and gap fill in the area where the space between word lines is small (gap-fill) forms an in-contact spacer to fundamentally solve the negative slope problem caused by the difference in etch rate between the wordline insulating layer and the gapfill layer, thereby forming void-free contact plugs during subsequent metal plug film deposition. The purpose is to provide a method.
상술한 목적을 달성하기 위한 본 발명에 따른 절연막 스페이서를 이용한 비트라인 콘택 플러그 형성 방법은 비트라인과 같은 반도체 요소가 형성된 실리콘 기판상의 절연막의 일부를 제거하여 비트라인 콘택홀을 형성하는 단계;According to an aspect of the present invention, there is provided a method of forming a bit line contact plug using an insulating layer spacer, the method including: forming a bit line contact hole by removing a portion of an insulating layer on a silicon substrate on which a semiconductor element such as a bit line is formed;
LP CVD 계열 산화막 또는 질화막을 전체 구조 상부에 증착한 다음, 전면 에치하여 상기 콘택홀의 측벽에 스페이서를 형성하여 상기 콘택홀의 상부폭이 하부폭보다 넓도록 형성하는 단계;Depositing an LP CVD-based oxide film or nitride film over the entire structure, and then etching the entire surface to form a spacer on the sidewall of the contact hole so that the upper width of the contact hole is wider than the lower width;
전체 구조 상부에 확산 방지 금속막을 증착하는 단계;Depositing a diffusion barrier metal film over the entire structure;
상기 금속막 상부에 금속 플러그막을 증착하고 전면 에치하여 보이드 없는 한 콘택 플러그를 형성하는 단계를 포함하여 이루어진다.And depositing a metal plug layer on the metal layer and etching the entire surface to form a contact plug as long as there is no void.
상기 LP CVD 계열 산화막은 TEST,SiH4 base oxide를 300-800℃에서 200-800Å 두께로 증착하여 형성된다.The LP CVD-based oxide film is formed by depositing TEST, SiH 4 base oxide at a thickness of 200-800 Pa at 300-800 ° C.
상기 산화막은 CF4, CHF3, C2F6, C3F8 중 어느 한 식각제를 이용하여 에치된다. 상기 LP CVD 계열 질화막은 SixNy, SiON, Si-rich nitride와 같은 질화막을 300-800℃에서 200-800Å 두께로 증착하여 형성된다.The oxide film is etched using an etchant of CF 4 , CHF 3 , C 2 F 6 , C 3 F 8 . The LP CVD-based nitride film is formed by depositing a nitride film such as SixNy, SiON, or Si-rich nitride at a thickness of 200-800 Å at 300-800 ° C.
상기 질화막은 CH4,CFH3,C2F6,SF6 중 어느 한 식각제를 이용하여 전면 에치되며상기 확산방지 금속막은 Ti,TiN,Tisi2,WN,TaN,TiSiN,TiAIN을 CDV 또는 스퍼터링(sputtering) 방법으로 300-600℃에서 100-500Å 두께로 단독으로 또는 이를 조합하여 증착하여 형성된다.The nitride layer is entirely etched using an etchant of CH 4 , CFH 3 , C 2 F 6 , SF 6 , and the diffusion barrier metal layer is formed by CDV or sputtering Ti, TiN, Tisi 2 , WN, TaN, TiSiN, TiAIN. (sputtering) is formed by depositing alone or in combination to a thickness of 100-500- at 300-600 ℃.
상기 콘택 금속 플러그막은 W 또는 Cu를 CDV 또는 스퍼터링 방법으로 300- 600℃에서 500-2000Å 두께로 증착하여 형성되며, 상기 증착된 금속 플러그막을 CI2,BCI3,CBrF3 중 어는 한 식각제를 이용하여 전면 에치한 후 CF4,CCIF3,C2CI2F4,CBrF3 중 어느 한 식각제를 이용하여 상기 확산방지 금속막을 전면 에치한다.The contact metal plug layer is formed by depositing W or Cu at a thickness of 500-2000 μs at 300-600 ° C. by CDV or sputtering, and using the etchant using one of CI 2 , BCI 3 , and CBrF 3 . After etching the entire surface by using an etchant of CF 4 , CCIF 3 , C 2 CI 2 F 4 , CBrF 3 to the entire surface of the diffusion preventing metal film.
본 발명에 따른 산화막 또는 질화막 스페이서를 이용한 비트라인 콘택 플러 그 형성방법은 비트라인 콘택 마스크/에치하는 공정과 LP CVD 계열 산화막 또는 질화막을 증착한 다음, 전면 에치하는 공정과 확산 방지 금속막을 증착하는 공정과 금속 플러그막을 증착하고 전면 에치하여 보이드 없는 콘택 플러그를 형성할 수 있는 공정으로 구성된다. The method of forming a bit line contact plug using an oxide film or nitride spacer according to the present invention is a process of forming a bit line contact mask / etch, depositing an LP CVD-based oxide film or nitride film, and then etching the entire surface and depositing a diffusion preventing metal film. And a process of depositing a metal plug film and etching the entire surface to form a void-free contact plug.
이하 본 발명에 따라 산화막 또는 질화막 스페이서를 이용한 비트라인 콘택 플러그 형성 공정에서 금속 플러그막 증착시 발생하는 보이드 문제를 방지할 수 있는 방법을 첨부 도면을 참고하여 설명하고자 한다. Hereinafter, a method for preventing a void problem occurring during deposition of a metal plug layer in a bit line contact plug forming process using an oxide layer or a nitride layer spacer according to the present invention will be described with reference to the accompanying drawings.
도 2a 에서와 같이 워드라인 절연막과 배선 상부에 비트라인 콘택 마스크(13)를 이용하여 먼저 실리콘 기판(10)과 워드라인 배선을 선택적으로 오픈하는 에치 공정을 진행하여 콘택홀(14)을 형성한다. As shown in FIG. 2A, the contact hole 14 is formed by performing an etch process of selectively opening the
마스크(13)를 제거하고 갭필 특성과 사이드월 스텝 커버리지(sidewall step coverage) 특성이 우수한 LP(Low Pressure) CVD 방법으로 TEOS,SiH4 base oxide와 같은 산화막(15)을 300-800℃에서 200-800Å 두께로 증착한다(도 2b). CF4,CHF3,C2F6,C3F8과 같은 식각제를 이용하여 전면 에치하거나 또는 SixNy, SiON, Si-rich nitride와 같은 질화막을 300-800℃에서 200-800Å두께로 증착한 다음, CF4,CFH3,C2F6,SF6와 같은 불소 계열의 식각제를 이용하여 전면 에치 함으로써 도 2c 의 (17)과 같이 워드라인 배선간 공간이 좁은 지역의 갭을 채우면서 (18)과 같이 스페이서를 형성하여 콘택홀의 상부폭이 하부폭보다 넓도록 형성하면 네가티브 슬로프(negative slope)의 발생을 근본적으로 방지할 수 있으며, 이후 확산방지 금속막으로 Ti,TiN, TiSi2,WN,TaN,TiSiN,TiAIN을 CVD 또는 스퍼터링 방법으로 300-600℃에서 100-500Å 두께로 단독으로 또는 이를 조합하여 증착하고, 비트라인 배선 금속막으로 W 또는 Cu를 CVD 또는 스퍼터링 방법으로 300-600℃에서 500-2000Å 두께로 증착한 다음, 먼저 C12, BC13,CBrF3와 같은 식각제를 이용하여 콘택 금속 플러그막을 전면 에치하고나서 CF4,CCIF3, C2CI2F4, CBrF3와 같은 식각제를 이용하여 확산방지 금속막을 전면 에치하여 비트라인 금속 플러그를 형성하면 도 2d도의 (20)과 같이 보이드가 발생하지 않는 안정된 금속 플러그막 형상을 얻을 수 있어 금속 플러그의 저항을 안정화시켜 소자 특성을 향상시킬 수 있다. The oxide film 15, such as TEOS, SiH 4 base oxide, was removed at 300-800 ° C. by the LP (Low Pressure) CVD method with the mask 13 removed and excellent gap fill and sidewall step coverage characteristics. Deposited at 800 mm thick (FIG. 2B). Etching such as CF 4 , CHF 3 , C 2 F 6 , C 3 F 8 , or etched a nitride film such as SixNy, SiON, Si-rich nitride at a thickness of 200-800Å at 300-800 ℃ Next, by using a fluorine-based etchant such as CF 4 , CFH 3 , C 2 F 6 , SF 6 to etch the entire surface while filling the gap of the narrow space between the word line wiring as shown in (17) of FIG. If the upper width of the contact hole is formed to be wider than the lower width by forming a spacer as shown in 18), it is possible to fundamentally prevent the occurrence of negative slope, and then use Ti, TiN, TiSi 2 , WN as a diffusion preventing metal film. , TaN, TiSiN, TiAIN are deposited alone or in combination with a thickness of 100-500Å at 300-600 ° C by CVD or sputtering method, and W or Cu is 300-600 ° C by CVD or sputtering method as bit line wiring metal film. At a thickness of 500-2000 Å at, then C1 2 , BC1 3 , CBrF 3 After the contact metal plug layer is etched using the respective agents, the anti-diffusion metal layer is etched using the etchant such as CF 4 , CCIF 3 , C 2 CI 2 F 4 , and CBrF 3 to form the bit line metal plug. As shown in FIG. 20, a stable metal plug film shape in which voids do not occur can be obtained, thereby stabilizing the resistance of the metal plug to improve device characteristics.
상술한 바와 같이 본 발명에 의하면 워드라인 절연막과 갭 파일(gap-fill) 막간 식각 속도 차이로 인한 내가티브 슬로프의 발생을 근본적으로 방지할 수 있으며, 갭 파일 막의 열처리로 인한 실리콘 기판의 열 버짓(thermal budget)을 억제할 수 있어 콘택 저항을 크게 감소시킬 수 있다. As described above, according to the present invention, it is possible to fundamentally prevent the occurrence of the negative slope due to the difference in the etching rate between the word line insulating film and the gap-fill film, and the thermal budget of the silicon substrate due to the heat treatment of the gap file film ( The thermal budget can be suppressed, which greatly reduces the contact resistance.
본 발명에서의 비트라인 콘택 금속 플러그 형성 방법은 갭 파일 및 스텝 커버리지(step coverage) 특성이 우수한 LP CVD 계열 산화막 또는 질화막을 증착한 다음, 전면 에치하여 워드라인간 갭을 채우면서 비트라인 콘택내 스페이서를 형성함으로써 네가티브 슬로프 문제를 해결 할 수 있다.In the method of forming a bit line contact metal plug according to the present invention, an LP CVD-based oxide film or nitride film having excellent gap pile and step coverage characteristics is deposited, and then etched on the entire surface to fill a gap between word lines, thereby filling a spacer in the bit line contact The negative slope problem can be solved by forming
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