KR20030023844A - Ferroelectric Random access memory and fabricating method of the same - Google Patents

Abstract

PURPOSE: A ferroelectric random access memory and fabrication method thereof are provided to prevent decrease of the capacitance caused by the size limit of an upper electrode and a short circuit between an upper and lower electrode. CONSTITUTION: Two neighboring transistors are formed on a semiconductor substrate(31). The first isolation layer(35) and second one(42) with openings to expose a portion of the first one are formed on the substrate. Two lower electrodes(41) are filled inside the openings. Two upper electrodes(44) are formed on a ferroelectric layer(43) with the same width as the lower ones. A portion of the upper electrodes is exposed to be connected to a plate line(47) through the third isolation layer(45). A word line(32), source(34b) and common drain(34a) of a transistor are connected to a bit line(37) and isolated from each other by the first isolation layer(35). Poly silicon layers are used to connect the lower electrodes of a capacitor to the source. Ti nitride layers(40) and Ti silicide layers(39) are used as a diffusion barrier and an ohmic contact layer respectively.

Description

Ferroelectric memory device and method of manufacturing the same {Ferroelectric Random access memory and fabricating method of the same}

TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a ferroelectric memory device and a method for manufacturing the same.

In general, by using a ferroelectric thin film in a ferroelectric capacitor in a semiconductor memory device, the development of a device capable of using a large-capacity memory while overcoming the limitation of refresh required in a DRAM (Dynamic Random Access Memory) device is in progress. come. Ferroelectric Random Access Memory (hereinafter referred to as 'FeRAM') device using the ferroelectric thin film is a kind of nonvolatile memory device that has the advantage of storing the stored information even when the power is cut off. In addition, the operating speed is comparable to DRAM, and is becoming the next generation memory device.

Ferroelectric thin films such as SrBi ₂ Ta ₂ O ₉ (hereinafter abbreviated as 'SBT') and Pb (Zr, Ti) O ₃ (hereinafter abbreviated as 'PZT') are mainly used as storage materials for such FeRAM devices. Ferroelectric thin films have dielectric constants ranging from hundreds to thousands at room temperature, and have two stable Remnant polarization (Pr) states.

Non-volatile memory devices using ferroelectric thin films store the digital signals '1' and '0' by controlling the direction of polarization in the direction of the applied electric field and inputting the signal, and the residual polarization remaining when the electric field is removed. The hysteresis characteristic is used.

When using a ferroelectric thin film such as Sr _x Bi _y (Ta _i Nb _j ) ₂ O ₉ (hereinafter referred to as SBTN) having a perovskite structure in addition to the above-described PZT and SBT as a ferroelectric thin film of a ferroelectric capacitor in a FeRAM device In general, upper and lower electrodes are formed by using metals such as platinum (Pt), iridium (Ir), ruthenium (Ru), iridium oxide (IrO), ruthenium oxide (RuO), and platinum alloy (Pt-alloy). .

1 is an equivalent circuit diagram of a FeRAM having a general 1T / 1C structure, in which 'C' is a ferroelectric capacitor, 'Q' is a MOS transistor, 'WL ₁ , WL ₂ ' is a word line connected to a gate of a MOS transistor, and 'BL''Indicates a bit line connected to the source / drain of the MOS transistor, and' PL 'indicates a plate line connected to the upper electrode of the capacitor.

FIG. 2 is a structural cross-sectional view showing a prior art FeRAM cell according to FIG. 1.

Referring to FIG. 2, planarization is performed on a semiconductor substrate 11 having two adjacent transistors formed thereon, and a device isolation film 12 formed on a predetermined portion of the semiconductor substrate 11 for isolation between two transistors and another transistor. The lower insulator 19 and the ferroelectric film 20 are stacked on the first insulator 15 and the first insulator 15 having the same width, and have a width smaller than that of the lower electrode 19 on the ferroelectric film 20. A ferroelectric capacitor having an upper electrode 21 having an upper portion thereof, an opening for exposing a predetermined surface of the upper electrode 21, and having an upper portion through the openings of the second insulator 22 and the second insulator 22 that are planarized while covering the ferroelectric capacitor. Plate line 23 connected to the electrode 21.

The transistor is formed according to a conventional CMOS process, in which a gate electrode (word line) 13 is formed on a semiconductor substrate 11, and two transistors adjacent to each other in the semiconductor substrate 11 on both sides of the gate electrode 13 are formed. The common connection drain (hereinafter abbreviated as 'common drain') 14a and the source 14b of each transistor are formed.

The first insulator 15 is an insulator in which the first and second interlayer insulating layers 15a and 15b are sequentially formed, and is formed through the first contact plug 16 embedded through the first interlayer insulating layer 15a. The bit line 17 is connected to 14a, and the bit line 17 is insulated by the second interlayer insulating film 15b.

The second contact plug 18 embedded through the first insulator 15 made of the insulator of the first and second interlayer insulating films 15a and 15b is embedded in the source 14b of each transistor and the first electrode of the ferroelectric capacitor. (19) is connected.

In the conventional FeRAM cell illustrated in FIG. 2, when the ferroelectric capacitor is formed, the lower electrode 19, the ferroelectric film 20, and the upper electrode 21 are sequentially formed, and then the upper electrode 21 is first etched and the other is formed. The ferroelectric film 20 and the lower electrode 19 are sequentially etched using a mask.

However, in the prior art, it is difficult to bring the upper electrode to the size of the lower electrode, because if the size of the lower electrode and the upper electrode are the same, the lower electrode and the upper electrode are short-circuited and it is difficult to secure process stability.

For this reason, it is difficult to secure a sufficient amount of charge because the size of the upper electrode, which determines the charge storage capability of the capacitor, is limited to the size of the lower electrode or less.

In addition, in the prior art, since the ferroelectric film must be etched in order to pattern the lower electrode immediately after forming the lower electrode, the ferroelectric film is exposed to plasma, which is an etching gas, during the etching process. There is a problem that a recovery heat treatment process must be performed to restore the characteristics of the ferroelectric film.

That is, when the upper electrode is etched, the ferroelectric film around the outer side of the upper electrode is inevitably exposed to the plasma, and the ferroelectric film is exposed to the plasma. Thus, the polarization does not have a positive (+) and (-) value and the plasma Depending on the situation at the time of exposure to (+) or (-) is fixed (this is called a pinning phenomenon), the amount of charge that can be used is greatly limited.

In order to solve this problem, a method of coating a ferroelectric film by applying spin coating or LSMCD method, which is widely used now, has been proposed, but it is difficult to secure the uniformity of the ferroelectric film due to the topology of the lower film formed before the lower electrode and the lower electrode. There is a disadvantage in that the ferroelectric film is easily cracked in a portion without the lower electrode.

In addition, in the case of forming a capacitor in the prior art, when patterning both the lower electrode / ferroelectric film / upper electrode, the step of the capacitor is more than 5500Å, and this step is burdened during the masking operation, and the capacitor must be filled with an interlayer insulating film. As the area shrinks, filling becomes increasingly difficult, which makes it difficult to flatten.

On the other hand, as the cell area is reduced, it is difficult to form a contact hole between the plate line and the capacitor, which is a metal wiring, and a method of directly connecting the upper electrode to the plate line by removing the interlayer insulating layer by front etching or CMP method has been proposed. In this case, when the ferroelectric film and the lower electrode are etched as in the aforementioned method, the interlayer insulating film is thin and there is a possibility that the plate line and the lower electrode are short-circuited.

This problem also occurs in DRAMs to which high ferroelectric films are applied.

The present invention has been made to solve the problems of the prior art, and an object of the present invention is to provide a ferroelectric memory device having a capacitor suitable for preventing the lowering of the charge storage capacity due to the size limitation of the upper electrode and its manufacturing method.

Another object of the present invention is to provide a method of manufacturing a ferroelectric memory device suitable for preventing the burden of the masking operation due to the step of the capacitor, difficulty in planarization, and short circuit between the upper and lower electrodes.

It is still another object of the present invention to provide a ferroelectric memory device having a ferroelectric film suitable for suppressing deterioration of characteristics of a ferroelectric film due to etching of a ferroelectric film, and a manufacturing method thereof.

1 is an equivalent circuit diagram of a FeRAM having a general 1T / 1C structure,

2 is a structural cross-sectional view showing a FeRAM manufactured according to the prior art;

3 is a structural cross-sectional view showing a FeRAM according to an embodiment of the present invention;

4A to 4D are cross-sectional views illustrating a method of manufacturing a FeRAM according to a first embodiment of the present invention.

5A is an equivalent circuit diagram of a FeRAM according to a second embodiment of the present invention;

5b is a layout according to FIG. 5a,

6A through 6D are cross-sectional views illustrating a method of manufacturing a FeRAM according to a second embodiment of the present invention.

7 is a layout diagram of a FeRAM according to a third embodiment of the present invention;

8A to 8D are cross-sectional views illustrating a method of manufacturing a FeRAM according to a third embodiment of the present invention.

9 is a layout diagram of a FeRAM according to a fourth embodiment of the present invention;

10A to 10D are cross-sectional views illustrating a method of manufacturing a FeRAM according to a fourth embodiment of the present invention.

10E is a cross-sectional view taken along line x-x 'of FIG. 10D;

11A to 11D are cross sectional views showing a method of manufacturing a FeRAM according to a fifth embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

31 semiconductor substrate 35 first insulating material

41: lower electrode 42: second insulator

43 ferroelectric film 44 upper electrode

45: third insulator 47: plate line

A ferroelectric memory device of the present invention for achieving the above object is a substrate in which a cell region and a peripheral circuit region is defined, a plurality of lower electrodes formed on the cell region, the plurality of lower electrodes are insulated from each other and the plurality of lower electrodes A first insulator formed over the entire area of the substrate, the first insulator including the plurality of lower electrodes, the ferroelectric layer formed only on the cell region, and at least the plurality of lower parts; It is characterized in that it comprises a plurality of upper electrodes on the ferroelectric film having a larger size than the electrode and in one direction are opposed to the plurality of lower electrodes, respectively, and the other direction in common to the plurality of lower electrodes. .

The method of manufacturing a ferroelectric memory device of the present invention includes forming a plurality of lower electrodes on an upper portion of the cell region of a substrate in which a cell region and a peripheral circuit region are defined, and forming a first insulator on the front surface including the plurality of lower electrodes. Forming a surface of the plurality of lower electrodes by planarizing the first insulator, forming a ferroelectric layer on the first insulator including the plurality of lower electrodes, and selectively etching the ferroelectric layer. Remaining only in the cell region, and having a size larger than at least the plurality of lower electrodes on the remaining ferroelectric film and opposing the plurality of lower electrodes in one direction and being common to the plurality of lower electrodes in the other direction, respectively. And forming a plurality of upper electrodes facing each other.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

FIG. 3 is a cross-sectional view illustrating a FeRAM cell according to a first embodiment of the present invention, in which a top electrode of two capacitors is simultaneously connected to one plate line shown in FIG. 1.

As shown in FIG. 3, a semiconductor substrate 31 having two adjacent transistors formed thereon, a first planarized first insulator 35 on the semiconductor substrate 31, and a first opening having a predetermined width exposing the first insulator 35. Ferroelectric film formed on the planarized second insulator 42 on the insulator 35, the lower electrode BE 41 filled in the opening of the second insulator 42, the lower electrode 41, and the second insulator 42. (43), the upper electrode (44) having at least an opening for exposing a predetermined top surface of the upper electrode (TE) 44 on the ferroelectric film 43 of the same size as the lower electrode (41). The plate line PL 47 is connected to the upper electrode 44 through an opening of the third insulator 45 and the third insulator 45 covering the ferroelectric layer 43.

And a bit line 37 connected to a transistor adjacent to each other including a word line 32 on the semiconductor substrate 31, a source 34b in the semiconductor substrate 31, and a common drain 34a, and a common drain 34a. ) Is insulated by the first insulator 35.

The first insulator 35 is formed of a first and second interlayer dielectric layers 35a and 35b having a multilayer structure, and a tungsten plug (a) is formed in the common drain 34a through a contact hole penetrating through the first interlayer dielectric layer 35a. 36 is connected, and a bit line 37 connected to the tungsten plug 36 is formed on the first interlayer insulating film 35a, and the first insulating material 35 exposes a predetermined portion of each source 34b. And a laminated film of the polysilicon plug 38, the titanium silicide 39, and the titanium nitride film 40 is embedded in the contact hole.

Here, the tungsten plug 36 is a contact plug for connecting the bit line 37 to the transistor, and the polysilicon plug 38 is a contact plug for connecting the lower electrode 42 of the capacitor to the transistor, and the lower electrode 42 ) And the titanium nitride film 40 inserted between the polysilicon plug 38 is a diffusion barrier film, and the titanium silicide 39 is an ohmic contact layer.

The ferroelectric film 43 is composed of SBT, BLT, PZT, doped SBT, doped BLT, doped PZT, perovskite-structured ferroelectric film and layered perovskite-structured ferroelectric film. It includes any one selected.

The lower electrode 41 and the upper electrode 44 may include any one selected from platinum, iridium, iridium oxide, ruthenium, ruthenium oxide, Re, Rh, and a composite structure thereof.

The first, second, and third insulators 35, 42, and 45 may be any one selected from oxides, nitrides, and complex structures thereof. In particular, the second insulators 42 may be formed of silicon oxide based oxides such as TEOS, PSG, and BPSG. , Silicon nitride film nitride and a composite structure thereof.

The second insulator 42 is a third interlayer insulating film, and the third insulator 45 is a fourth interlayer insulating film.

4A through 4D are cross-sectional views illustrating a method of manufacturing the ferroelectric memory device according to the first embodiment of the present invention.

As shown in FIG. 4A, after forming an isolation layer 32 for isolation between devices on the semiconductor substrate 31, and forming a plurality of word lines 33 on the semiconductor substrate 31, a word line ( 33) Source / drain 34a and 34b of the transistor are formed in the semiconductor substrate 31 on both sides by an ion implantation process.

Here, one source / drain 34a among the sources / drains 34a and 34b serves as a common junction region of two transistors connected to one subsequent bit line (hereinafter, abbreviated as 'common drain'). Therefore, the other source / drain 34b becomes a source of each transistor.

After the deposition and planarization of the first interlayer insulating film 35a on the entire surface including the two adjacent transistors formed by the above-described process, the first interlayer insulating film 35a is selectively etched to expose the common drain 34a. A first contact hole (not shown) is formed, and the tungsten plug 36 is embedded in the first contact hole.

Next, after depositing a first conductive film for forming a bit line on the first interlayer insulating film 35a in which the tungsten plug 36 is embedded, the first conductive film is selectively patterned to be common through the tungsten plug 36. The bit line 37 connected to the drain 34a is formed.

Next, after depositing and planarizing the second interlayer insulating film 35b on the first interlayer insulating film 35a including the bit line 37, the second interlayer insulating film 35b and the first interlayer insulating film 35a are sequentially formed. Etching to form a second contact hole (not shown) exposing the source 34b of each transistor.

Here, the first interlayer insulating film 35a and the second interlayer insulating film 35b are first insulating materials 35 for insulating the lower films formed before the formation of the ferroelectric capacitor.

Subsequently, polysilicon is deposited on the entire surface including the second contact hole, and the polysilicon plug 38 is partially embedded in the second contact hole through an etch back process, and then titanium silicide 39 is deposited on the polysilicon plug 38. ).

Here, the titanium silicide 39 is formed through titanium deposition and heat treatment, and an etching process for removing unreacted titanium is performed after the heat treatment.

The above-mentioned polysilicon plug / titanium silicide 38/39 is all connected to the transistor and is formed in a structure partially buried in the second contact hole.

Next, after depositing a titanium nitride film (TiN) 40 on the entire surface including the titanium silicide 39, the titanium nitride film on the second interlayer insulating film 35b is removed by etching back or chemical mechanical polishing. 2 It is left only in the contact hole.

Here, the titanium nitride film 40 is a barrier film for preventing oxygen from diffusing into the polysilicon plug 38 through the lower electrode during the heat treatment of the subsequent ferroelectric film. Such a barrier film may include TiAlN, in addition to the titanium nitride film 40. Any one selected from TiSiN and composites thereof (eg TiSiN / TiN) can be used.

In addition, the barrier layer including the titanium nitride layer 40 may be patterned at the same time during subsequent lower electrode patterning so that its width is the same as that of the lower electrode.

The laminated film of the polysilicon plug 38, the titanium silicide 39, and the titanium nitride film 40 is referred to as a storage node contact (SNC).

Next, after depositing a second conductive film for forming a lower electrode on the second interlayer insulating film 35b, the second conductive film is selectively patterned and connected to the source 34b of the transistor through the polysilicon plug 38. The lower electrode 41 is formed.

Here, the second conductive film forming the lower electrode 41 includes any one selected from platinum (Pt), iridium (Ir), iridium oxide (IrO _x ), ruthenium (Ru), Re, Rh, and a composite structure thereof. For example, a laminated film (Ir / IrO _x / Pt) laminated in the order of iridium, iridium oxide and platinum is used.

The second conductive film constituting the lower electrode 41 is deposited by one deposition method selected from chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

Next, a third interlayer insulating film 42 is deposited on the entire surface including the lower electrode 41.

As shown in FIG. 4B, the lower electrode 41 is formed in the third interlayer insulating film 42 by planarizing the third interlayer insulating film 42 by chemical mechanical polishing or etching back until the surface of the lower electrode 41 is exposed. To form a buried structure.

Here, as another method of embedding the lower electrode 41 in the third interlayer insulating film 42, first, the third interlayer insulating film 42 is formed, and then the third interlayer insulating film 42 is selectively etched to form the lower electrode ( 41) may be formed by exposing a portion to be formed, depositing a second conductive film on the entire surface, and then etching back or chemical mechanical polishing.

Meanwhile, the third interlayer insulating film 42 may be any one selected from silicon oxide based oxides such as TEOS, PSG, and BPSG, silicon nitride based nitrides, and composite structures thereof, and the first and second interlayer insulating films 35a and 35b. ) May also use an insulator applied to the third interlayer insulating film 42.

As shown in FIG. 4C, after the ferroelectric film 43 is deposited on the planarized third interlayer insulating film 42, a third conductive film for forming the upper electrode is deposited on the ferroelectric film 43. Subsequently, the third conductive film is selectively patterned to form an upper electrode 44 that is the same size or larger than the lower electrode 41.

Here, the ferroelectric film 43 is composed of SBT, BLT, PZT, doped SBT, doped BLT, doped PZT, doped PZT, perovskite-structured ferroelectric film and ferroelectric film of layered perovskite structure. It includes any one selected, and is deposited by one deposition method selected from chemical vapor deposition (CVD), spin coating and Liquid Source Misted Chemical Deposition (LSMCD) method.

The third conductive film forming the upper electrode 44 includes any one selected from platinum (Pt), iridium (Ir), iridium oxide (IrO _x ), ruthenium (Ru), Re, Rh, and a composite structure thereof. In addition, it is deposited by one deposition method selected from chemical vapor deposition (CVD), physical vapor deposition (PVD) and atomic layer deposition (ALD).

As described above, since the lower electrode 41 and the upper electrode 44 are completely isolated by the ferroelectric film 43, the size of the upper electrode 44 is not limited.

In addition, since the upper electrode 44 may be patterned to have the same size as the lower electrode 41, a mask applied when the lower electrode 41 is patterned may be applied, thereby reducing the number of masks.

As shown in FIG. 4D, after depositing and planarizing the fourth interlayer insulating layer 45 on the entire surface including the upper electrode 44, the fourth interlayer insulating layer 45 is selectively etched to predetermined the upper electrode 44. A capacitor contact hole (not shown) is formed to expose the surface.

Subsequently, after depositing and patterning a diffusion barrier film 46 for preventing diffusion of impurities in subsequent plate lines on the front surface including the capacitor contact hole, a metal film for forming the plate line is deposited on the front surface.

Here, the diffusion barrier film 46 uses one selected from TiN, Ti, and Ti / TiN.

Next, the metal film is selectively patterned to form plate lines 47 for connecting adjacent upper electrodes 44 to each other.

FIG. 5A is an equivalent circuit diagram of a ferroelectric memory device according to the second embodiment of the present invention, and FIG. 5B is a layout diagram showing the ferroelectric memory device according to the second embodiment.

Referring to 'A' of FIG. 5A, unlike FIG. 1, one ferroelectric memory cell is connected to different plate lines PL1 and PL2, respectively.

That is, one bit line BL1 and two word lines WL1 and WL2 intersect each other, and one cell has a drain connected to the bit line BL1 and a gate connected to the first word line WL1. It consists of a first ferroelectric capacitor FC1 connected between the connected first transistor MN1 and the source of the first transistor MN1 and the first plate line PL1, and the other cell is drained to the bit line BL1. The second ferroelectric capacitor FC1 connected between the third transistor MN3 and the source of the third transistor MN3 and the second plate line PL2 connected to each other and the gate connected to the second word line WL2. Is done.

Referring to FIG. 5B, which shows the equivalent circuit of FIG. 5A as a layout, a direction in which two word lines WL1 and WL2 and two bit lines BL1 and BL2 cross each other (eg, a word line in a Y-axis direction). And bit lines arranged in the X-axis direction), and bit line contacts BLC1 and BLC2 for contacting the bit lines BL1 and BL2 with a semiconductor substrate (not shown) between the word lines WL1 and WL2. ) Is disposed, the first capacitor module CM1 is disposed in parallel along one word line WL1, and the second capacitor module CM2 is disposed in parallel along the other word line WL2. Is placed.

Here, the first and second capacitor modules CM1 and CM2 are disposed on the other side of the word lines WL1 and WL2 so as not to be connected to the bit line contacts BLC1 and BLC2 disposed on one side of the word lines WL1 and WL2. Is placed.

Meanwhile, the first capacitor module CM1 is connected to the storage node contacts SNC1 and SNC2 and the lower electrodes BE1 and BE2 connected to the storage node contacts SNC1 and SNC2. ), One upper electrode TE1 covering all of the lower electrodes BE1 and BE2, and one plate line PL1 is disposed while overlapping in the same direction as the upper electrode TE1 and the upper electrode TE1. A capacitor contact (CAPC1) for connecting the plate line (PL1) and the upper electrode (TE1) is disposed only at one end of the.

The second capacitor module CM2 includes a lower electrode BE3 and a BE4 and a lower electrode connected to the storage node contacts SNC3 and SNC4, the storage node contacts SNC3 and SNC4, which are in contact with the semiconductor substrate (not shown). It consists of one upper electrode (TE2) covering both BE3, BE4, one plate line (PL2) is disposed while overlapping in the same direction as the upper electrode (TE2) and plate line only at one end of the upper electrode (TE2) A capacitor contact (CAPC2) for connecting the PL2 and the upper electrode TE2 is disposed.

In the first capacitor module CM1 and the second capacitor module CM2, the capacitors share one ferroelectric film F, and the upper electrodes TE1 and TE2 are formed by the plate lines PL1 and PL2. It has a structure.

6A through 6D are cross-sectional views illustrating a method of manufacturing the ferroelectric memory device according to the second embodiment of the present invention. Here, the left side of each figure is a sectional view along the line y-y 'of FIG. 5B, and the right side of the figure is a sectional view along the line x-x' of FIG. 5B.

Hereinafter, the cross-sectional view along the line y-y 'will be described, and the cross-sectional view along the line x-x' will be additionally described.

As shown in FIG. 6A, a field oxide film 52 is formed on the semiconductor substrate 51 for isolation between devices, and word lines 53 are arranged on the semiconductor substrate 51 and arranged side by side at a predetermined distance. Thereafter, source / drain 54a and 54b of the transistor are formed in the semiconductor substrate 51 on both sides of the word line 53 by an ion implantation process.

Here, one source / drain 54a among the sources / drains 54a and 54b serves as a common junction region of two transistors connected to one subsequent bit line BL1 (hereinafter, abbreviated as 'common drain'). Therefore, the other source / drain 54b becomes a source (hereinafter, referred to as a 'source') of each transistor.

Next, after depositing and planarizing the first interlayer insulating film 55a on the entire surface including the transistor formed by the above-described process, the first interlayer insulating film 55a is selectively etched to expose the common drain 54a. A contact hole (not shown) is formed, and the tungsten plug 56 is embedded in the first contact hole.

Next, after depositing a first conductive film for forming a bit line on the first interlayer insulating film 55a in which the tungsten plug 56 is embedded, the first conductive film is selectively patterned to be common through the tungsten plug 56. A bit line 57 is formed to be connected to the drain 54a.

Next, after depositing and planarizing the second interlayer insulating film 55b on the first interlayer insulating film 55a including the bit line 57, the second interlayer insulating film 55b and the first interlayer insulating film 55a are sequentially formed. Etching to form a second contact hole (not shown) exposing the source 54b of each transistor.

Subsequently, polysilicon is deposited on the entire surface including the second contact hole, and the polysilicon plug 58 is partially embedded in the second contact hole through an etchback process, and then titanium silicide 59 is deposited on the polysilicon plug 58. ).

Here, the titanium silicide 59 is formed through titanium deposition and heat treatment, and an etching process for removing unreacted titanium is performed after the heat treatment.

The above-mentioned polysilicon plug / titanium silicide 58/59 is all connected to the source 54b of the transistor and is formed in a structure partially buried in the second contact hole.

Next, after depositing a titanium nitride film (TiN) 60 as a barrier film on the entire surface including the titanium silicide 59, the titanium nitride film on the second interlayer insulating film 55b is removed by etch back or chemical mechanical polishing. 2 It is left only in the contact hole.

Herein, the titanium nitride film 60 is a barrier film for preventing oxygen from diffusing into the polysilicon plug 58 through the lower electrode during the heat treatment of the subsequent ferroelectric film. The barrier film may include TiAlN, in addition to the titanium nitride film 60. Any one selected from TiSiN and composites thereof (eg TiSiN / TiN) can be used.

In addition, the barrier layer including the titanium nitride layer 60 may be patterned at the same time during subsequent lower electrode patterning to have the same width as the lower electrode.

As described above, the laminated film of the polysilicon plug 58, the titanium silicide 59, and the titanium nitride film 60 embedded in the second contact hole is referred to as a storage node contact (SNC).

Next, after depositing a second conductive film for forming the lower electrode on the second interlayer insulating film 55b, the second conductive film is selectively patterned to be connected to the source 54b of the transistor through the storage node contact. The electrode 61 is formed.

The second conductive layer forming the lower electrode 61 may include any one selected from platinum (Pt), iridium (Ir), iridium oxide (IrO _x ), ruthenium (Ru), Re, Rh, and a composite structure thereof. For example, a laminated film (Ir / IrO _x / Pt) laminated in the order of iridium, iridium oxide and platinum is used. The second conductive film constituting the lower electrode 61 is deposited by one deposition method selected from chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

On the other hand, looking at the cross-sectional view along the x-x 'line, the two lower electrodes 61 arranged along one word line 53 are formed while being separated by the field oxide film 52 at a predetermined distance from each other. That is, the two lower electrodes 61 are not formed on the same active region.

As shown in FIG. 6B, after the third interlayer insulating film 62 is deposited on the entire surface including the lower electrode 61, the third interlayer insulating film 62 is chemically mechanically disposed until the surface of the lower electrode 61 is exposed. Planarization is performed by polishing or etch back to form a structure in which the lower electrode 61 is embedded in the third interlayer insulating film 62, respectively.

For example, in the case of chemical mechanical polishing of the third interlayer insulating layer 62, the loss of the upper surface of the lower electrode 61 is insignificant, and in the case of the cell region, the dishing phenomenon that is pitted by the loss in a wide region is also short. Because it is small, flattening is possible.

As another method of embedding the lower electrode 61 in the third interlayer insulating film 62, first, the third interlayer insulating film 62 is formed, and then the third interlayer insulating film 62 is selectively etched to form the lower electrode ( 61) may be formed by exposing a portion to be formed, depositing a second conductive film on the entire surface, and then etching back or chemical mechanical polishing.

Meanwhile, the third interlayer insulating layer 62 may be any one selected from silicon oxide based oxides such as TEOS, PSG, and BPSG, silicon nitride based nitrides, and composite structures thereof, and the first and second interlayer insulating films 55a and 55b. ) May also use an insulator applied to the third interlayer insulating film 62.

As shown in FIG. 6C, after the ferroelectric layer 63 is deposited on the planarized third interlayer dielectric layer 62, a third conductive layer for forming the upper electrode is deposited on the ferroelectric layer 63.

Subsequently, the third conductive film is selectively patterned to form an upper electrode 64 having a size equal to or larger than that of the lower electrode 61 and arranged in a direction crossing the bit line 57.

On the other hand, looking at the cross-sectional view along the X axis, the upper electrode 64 is formed on the lower electrode 61 and the common ferroelectric film 63 on the lower electrode 61 arranged along one word line, respectively.

Here, the ferroelectric film 63 is composed of SBT, BLT, PZT, doped SBT, doped BLT, doped PZT, perovskite-structured ferroelectric film and layered perovskite-structured ferroelectric film. It includes any one selected, and is deposited by one deposition method selected from chemical vapor deposition (CVD), spin coating and LSMCD method.

The third conductive film forming the upper electrode 64 includes any one selected from platinum (Pt), iridium (Ir), iridium oxide (IrO _x ), ruthenium (Ru), Re, Rh, and a composite structure thereof. In addition, it is deposited by one deposition method selected from chemical vapor deposition (CVD), physical vapor deposition (PVD) and atomic layer deposition (ALD).

As described above, since the lower electrode 61 and the upper electrode 64 are completely isolated by the ferroelectric film 63, the size of the upper electrode 64 is not limited.

As shown in FIG. 6D, after depositing and planarizing the fourth interlayer insulating film 65 on the entire surface including the upper electrode 64, referring to the cross-sectional view along the x-x 'line, the fourth interlayer insulating film 65 is referred to. A third contact hole (not shown) for selectively forming a capacitor contact (CAPC1 / CAPC2 (shown in FIG. 5B)) exposing one end of the upper electrode 64 is selectively formed by etching.

Subsequently, after the diffusion barrier film 66 is deposited on the entire surface including the third contact hole to prevent diffusion of impurities in the subsequent plate line, the diffusion barrier film 66 is selectively patterned to remain only in the third contact hole. Let's do it.

Here, as the diffusion barrier film 66, one selected from TiN, Ti, and Ti / TiN is used.

Next, after depositing a metal film for forming a plate line on the front surface including the diffusion barrier film 66, the metal film is selectively patterned to be arranged in a direction crossing the bit line 57 and side by side in the word line 53. The plate lines 67 arranged in the order of TiN / Ti / Al / TiN covering the upper electrode 64 are formed.

On the other hand, looking at the cross-sectional view along the line x-x ', the plate line 67 is formed in the same direction as the upper electrode 64 through the third contact hole formed at one end of the common upper electrode 64.

As such, since the third contact hole is formed only at the end of the plate line 67, the third contact hole may be formed as large as necessary without burdening the cell area even when the cell area is reduced.

In the above-described second embodiment, since the contact is formed only at one end of the plate line 67 without forming the capacitor contact in each capacitor, it is possible to avoid the difficulty of forming the contact in each capacitor during the cell area accumulation.

In addition, since the entire step by the capacitor is reduced only by the step of the upper electrode, the burden of mask work due to the step can be reduced, so that the flattening is easy.

In addition, since the short circuit between the upper electrode 64 and the lower electrode 61 is fundamentally prevented and the ferroelectric layer 63 is not etched, the ferroelectric layer 63 is prevented from being exposed to plasma and deteriorated during the etching process.

On the other hand, in the second embodiment, a diffusion barrier film is used to prevent diffusion of titanium in the plate line. However, a capacitor contact in which the diffusion barrier film is formed is formed at the end of the plate line, and titanium diffused directly from the plate line is ferroelectric. The diffusion barrier film may be omitted because it does not affect the film.

That is, in the case of applying the diffusion barrier layer, the wet etching of the contact hole for exposing the bit line of the peripheral circuit region is difficult due to the modification of the film quality of the lower third interlayer dielectric layer during the etching of the diffusion barrier layer, but the diffusion barrier layer is omitted. In this case, since the wet etching is possible, the contact form of the metal wiring is formed in the form of wine glass, and the contact resistance and the filling are easy even when the size of the contact is reduced.

7 is a layout diagram illustrating cells of a ferroelectric memory device according to a third embodiment of the present invention. For reference, the third embodiment is composed of the same equivalent circuit as the second embodiment.

FIG. 7 is another layout diagram according to the equivalent circuit of FIG. 5A, in which all capacitors share one ferroelectric film F and the upper electrodes TE1 and TE2 arranged in the y-axis direction have a plurality of lower electrodes BE1 and BE2. 5B is the same as that of FIG. 5B, but a capacitor contact for connecting the plate lines PL ₁ and PL ₂ and the upper electrodes TE1 and TE2 is independently independent on the ferroelectric layer F in advance. One provided per BE1, BE2, BE3, BE4) is different from FIG. 5B.

That is, the two word lines WL1 and WL2 and the two bit lines BL1 and BL2 cross each other (for example, the word lines are arranged in the y-axis direction and the bit lines are arranged in the x-axis direction). The bit line contacts BLC1 and BLC2 for contacting the bit lines BL1 and BL2 with the semiconductor substrate (not shown) are disposed between the word lines WL1 and WL2, and along one word line WL1. The first capacitor module CM1 is disposed in parallel, and the second capacitor module CM2 is disposed in parallel along the other word line WL2.

Here, the first and second capacitor modules CM1 and CM2 are disposed at the other side of the word lines so as not to be connected to the bit line contacts BLC1 and BLC2 disposed at one side of the word lines WL1 and WL2.

On the other hand, the first capacitor module (CM1) is a lower electrode (BE1, BE2), the lower electrode connected to the storage node contacts (SNC1, SNC2), the storage node contacts (SNC1, SNC2) that are in contact with the semiconductor substrate (not shown) It consists of one upper electrode TE1 covering BE1 and BE2 at the same time. One plate line PL1 is disposed while overlapping in the same direction as the upper electrode TE1. The upper electrode TE1 and the ferroelectric film F are disposed. One capacitor contact (CAPC1, CPAC2) is disposed for each lower electrode (BE1, BE2).

The second capacitor module CM2 includes a lower electrode BE3 and a BE4 and a lower electrode connected to the storage node contacts SNC3 and SNC4, the storage node contacts SNC3 and SNC4, which are in contact with the semiconductor substrate (not shown). It consists of one upper electrode TE2 covering BE3 and BE4 at the same time. One plate line PL2 is disposed while overlapping in the same direction as the upper electrode TE2. The upper electrode TE2 and the ferroelectric film F are disposed. One capacitor contact (CAPC3, CAPC4) is disposed for each lower electrode (BE3, BE4) between.

In the first capacitor module CM1 and the second capacitor module CM2, the capacitors share one ferroelectric film F.

8A to 8D are cross-sectional views illustrating a method of manufacturing a ferroelectric memory device according to a third embodiment of the present invention. 7 is a cross-sectional view taken along the line y-y 'of FIG. 7.

As shown in FIG. 8A, a field oxide film 52 is formed on the semiconductor substrate 51 for isolation between devices, and word lines 53 are arranged on the semiconductor substrate 51 to be arranged side by side at a predetermined distance. Thereafter, source / drain 54a and 54b of the transistor are formed in the semiconductor substrate 51 on both sides of the word line 53 by an ion implantation process.

Here, one source / drain 54a among the sources / drains 54a and 54b serves as a common junction region of two transistors connected to one subsequent bit line (hereinafter, abbreviated as 'common drain'). Therefore, the other source / drain 54b becomes a source (hereinafter, referred to as a 'source') of each transistor.

Next, after depositing and planarizing the first interlayer insulating film 55a on the entire surface including the transistor formed by the above-described process, the first interlayer insulating film 55a is selectively etched to expose the common drain 54a. A contact hole (not shown) is formed, and the tungsten plug 56 is embedded in the first contact hole.

Next, after depositing a first conductive film for forming a bit line on the first interlayer insulating film 55a in which the tungsten plug 56 is embedded, the first conductive film is selectively patterned to be common through the tungsten plug 56. A bit line 57 is formed to be connected to the drain 54a.

Next, after depositing and planarizing the second interlayer insulating film 55b on the first interlayer insulating film 55a including the bit line 57, the second interlayer insulating film 55b and the first interlayer insulating film 55a are sequentially formed. Etching to form a second contact hole (not shown) exposing the source 54b of each transistor.

Subsequently, polysilicon is deposited on the entire surface including the second contact hole, and the polysilicon plug 58 is partially embedded in the second contact hole through an etchback process, and then titanium silicide 59 is deposited on the polysilicon plug 58. ).

Here, the titanium silicide 59 is formed through titanium deposition and heat treatment, and an etching process for removing unreacted titanium is performed after the heat treatment.

The above-mentioned polysilicon plug / titanium silicide 58/59 is all connected to the source 54b of the transistor and is formed in a structure partially buried in the second contact hole.

Next, after depositing a titanium nitride film (TiN) 60 as a barrier film on the entire surface including the titanium silicide 59, the titanium nitride film on the second interlayer insulating film 55b is removed by etch back or chemical mechanical polishing. 2 It is left only in the contact hole.

Herein, the titanium nitride film 60 is a barrier film for preventing oxygen from diffusing into the polysilicon plug 58 through the lower electrode during the heat treatment of the subsequent ferroelectric film. The barrier film may include TiAlN, in addition to the titanium nitride film 60. Any one selected from TiSiN and composites thereof (eg TiSiN / TiN) can be used.

In addition, the barrier layer including the titanium nitride layer 60 may be patterned at the same time during subsequent lower electrode patterning to have the same width as the lower electrode.

As described above, the laminated film of the polysilicon plug 58, the titanium silicide 59, and the titanium nitride film 60 embedded in the second contact hole is referred to as a storage node contact.

Next, after depositing a second conductive film for forming the lower electrode on the second interlayer insulating film 55b, the second conductive film is selectively patterned to be connected to the source electrode 54b of the transistor through the storage node contact. Form 61.

The second conductive layer forming the lower electrode 61 may include any one selected from platinum (Pt), iridium (Ir), iridium oxide (IrO _x ), ruthenium (Ru), Re, Rh, and a composite structure thereof. For example, a laminated film (Ir / IrO _x / Pt) laminated in the order of iridium, iridium oxide and platinum is used. The second conductive film constituting the lower electrode 41 is deposited by one deposition method selected from chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

As shown in FIG. 8B, after the third interlayer insulating film 62 is deposited on the entire surface including the lower electrode 61, the third interlayer insulating film 62 is chemically mechanically disposed until the surface of the lower electrode 61 is exposed. Planarization is performed by polishing or etch back to form a structure in which the lower electrode 61 is embedded in the third interlayer insulating film 62, respectively.

For example, in the case of chemical mechanical polishing of the third interlayer dielectric layer 62, the loss of the upper surface of the lower electrode 61 is insignificant. Because it is small, flattening is possible.

As another method of embedding the lower electrode 61 in the third interlayer insulating film 62, first, the third interlayer insulating film 62 is formed, and then the third interlayer insulating film 62 is selectively etched to form the lower electrode ( 61) may be formed by exposing a portion to be formed, depositing a second conductive film on the entire surface, and then etching back or chemical mechanical polishing.

Meanwhile, the third interlayer insulating layer 62 may be any one selected from silicon oxide based oxides such as TEOS, PSG, and BPSG, silicon nitride based nitrides, and composite structures thereof, and the first and second interlayer insulating films 55a and 55b. ) May also use an insulator applied to the third interlayer insulating film 62.

As shown in FIG. 8C, a ferroelectric film 63 is deposited on the planarized third interlayer insulating film 62. Here, the ferroelectric film 63 is composed of SBT, BLT, PZT, doped SBT, doped BLT, doped PZT, perovskite-structured ferroelectric film and layered perovskite-structured ferroelectric film. It includes any one selected, and is deposited by one deposition method selected from chemical vapor deposition (CVD), spin coating and LSMCD method.

Next, after the fourth interlayer insulating film 65 and the adhesive layer 68 are sequentially formed on the ferroelectric film 63, the adhesive layer 68 and the fourth interlayer insulating film 65 are selectively etched to form the ferroelectric film 63. A contact hole 69 is formed for a capacitor contact (CAPC) exposing a predetermined surface of the capacitor.

Here, the contact hole 69 for the capacitor contact is a portion where the next upper electrode and the ferroelectric layer 63 are to be contacted, and TiO ₂ and Al ₂ O ₃ are used as the adhesive layer 68.

On the other hand, when forming the contact hole 69 for the capacitor contact, the etching of the fourth interlayer insulating film 65 and the adhesive layer 68 is wet etching, which means that the ferroelectric film 63 is degraded during dry etching using plasma. This is to prevent.

As shown in FIG. 8D, a third conductive film for forming the upper electrodes TE1 and TE2 and a metal film for forming the plate line are sequentially deposited on the front surface including the contact hole 69 for the capacitor contact.

Subsequently, the metal film and the third conductive film are selectively patterned to form an upper electrode 64 having the same or larger size as the lower electrode 61 and arranged in a direction crossing the bit line, and directly on the upper electrode. While connected, the plate line 67 is formed to be arranged in the same direction as the upper electrode 64.

Here, the upper electrode 64 includes any one selected from platinum (Pt), iridium (Ir), iridium oxide (IrO _x ), ruthenium (Ru), Re, Rh, and a composite structure thereof. CVD), physical vapor deposition (PVD) and atomic layer deposition (ALD).

The plate line 67 uses a metal film laminated in the order of TiN / Ti / Al / TiN.

In the above-described third embodiment, since the ferroelectric film is not directly exposed to the plasma through the entire process, the degradation of the ferroelectric film due to the plasma can be suppressed, and the size of the upper electrode and the lower electrode can be equally patterned, so that the size of the given capacitor can be reduced. More charge is available.

9 is a cell layout diagram of a ferroelectric memory device according to the fourth embodiment of the present invention.

FIG. 9 is another layout diagram of the equivalent circuit of FIG. 5A, in which all capacitors share one ferroelectric film F, and the upper electrodes TE1 and TE2 arranged in the y-axis direction have a plurality of lower electrodes BE1, Covering BE2, BE3, BE4 is the same as in the second and third embodiments, and the capacitor contacts (CAPC1, CPAC2, CPAC3, CACP4) for connecting the upper electrodes TE1, TE2 on the ferroelectric film F. The first and second ones are the same as those in the third embodiment, except that the plate lines PL1 and PL2 are connected to only one end of the upper electrodes TE1 and TE2 with a predetermined width. Is different from

That is, the two word lines WL1 and WL2 and the two bit lines BL1 and BL2 cross each other (for example, the word lines are arranged in the y-axis direction and the bit lines are arranged in the x-axis direction). Bit line contacts BLC1 and BLC2 for contacting the bit lines BL1 and BL2 with the semiconductor substrate (not shown) are disposed between the word lines WL1 and WL2, and along one word line WL1. The first capacitor module CM1 is disposed in parallel, and the second capacitor module CM2 is disposed in parallel along the other word line WL2.

Here, the first and second capacitor modules CM1 and CM2 are disposed at the other side of the word lines so as not to be connected to the bit line contacts BLC1 and BLC2 disposed at one side of the word lines WL1 and WL2.

On the other hand, the first capacitor module (CM1) is a lower electrode (BE1, BE2), the lower electrode connected to the storage node contacts (SNC1, SNC2), the storage node contacts (SNC1, SNC2) that are in contact with the semiconductor substrate (not shown) It consists of one upper electrode TE1 covering BE1 and BE2 at the same time, and capacitor contacts CACC1 and CPAC2 are disposed between the upper electrode TE1 and the ferroelectric film F, and one end of the upper electrode TE1 is disposed. One plate line PL1 is connected to it.

The second capacitor module CM2 includes a lower electrode BE3 and a BE4 and a lower electrode connected to the storage node contacts SNC3 and SNC4, the storage node contacts SNC3 and SNC4, which are in contact with the semiconductor substrate (not shown). Comprising one upper electrode (TE2) to cover the BE3, BE4 at the same time, the capacitor contacts (CAPC3, CPAC4) is disposed between the upper electrode (TE2) and the ferroelectric film (F), one end of the upper electrode (TE2) One plate line PL2 is connected to it.

In the first capacitor module CM1 and the second capacitor module CM2, the capacitors share one ferroelectric film F.

10A through 10D are cross-sectional views illustrating a method of manufacturing a ferroelectric memory device according to a fourth embodiment of the present invention.

Hereinafter, a cross-sectional view taken along the line y-y 'of FIG. 9 will be described.

As shown in FIG. 10A, a field oxide film 52 is formed on the semiconductor substrate 51 for isolation between devices, and word lines 53 are arranged on the semiconductor substrate 51 and arranged side by side at a predetermined distance. Thereafter, source / drain 54a and 54b of the transistor are formed in the semiconductor substrate 51 on both sides of the word line 53 by an ion implantation process.

Here, one source / drain 54a among the sources / drains 54a and 54b serves as a common junction region of two transistors connected to one subsequent bit line BL1 (hereinafter, abbreviated as 'common drain'). Therefore, the other source / drain 54b becomes a source (hereinafter, referred to as a 'source') of each transistor.

Next, after depositing and planarizing the first interlayer insulating film 55a on the entire surface including the transistor formed by the above-described process, the first interlayer insulating film 55a is selectively etched to expose the common drain 54a. A contact hole (not shown) is formed, and the tungsten plug 56 is embedded in the first contact hole.

Next, after depositing a first conductive film for forming a bit line on the first interlayer insulating film 55a in which the tungsten plug 56 is embedded, the first conductive film is selectively patterned to be common through the tungsten plug 56. A bit line 57 is formed to be connected to the drain 54a.

Next, after depositing and planarizing the second interlayer insulating film 55b on the first interlayer insulating film 55a including the bit line 57, the second interlayer insulating film 55b and the first interlayer insulating film 55a are sequentially formed. Etching to form a second contact hole (not shown) exposing the source 54b of each transistor.

Subsequently, polysilicon is deposited on the entire surface including the second contact hole, and the polysilicon plug 58 is partially embedded in the second contact hole through an etch back process, and then titanium silicide 59 is deposited on the polysilicon plug 58. ).

Here, the titanium silicide 59 is formed through titanium deposition and heat treatment, and an etching process for removing unreacted titanium is performed after the heat treatment.

The above-mentioned polysilicon plug / titanium silicide 58/59 is all connected to the source 54b of the transistor and is formed in a structure partially buried in the second contact hole.

Next, after depositing a titanium nitride film (TiN) 60 as a barrier film on the entire surface including the titanium silicide 59, the titanium nitride film on the second interlayer insulating film 55b is removed by etch back or chemical mechanical polishing. 2 It is left only in the contact hole.

Herein, the titanium nitride film 60 is a barrier film for preventing oxygen from diffusing into the polysilicon plug 58 through the lower electrode during the heat treatment of the subsequent ferroelectric film. The barrier film may include TiAlN, in addition to the titanium nitride film 60. Any one selected from TiSiN and composites thereof (eg TiSiN / TiN) can be used.

In addition, the barrier layer including the titanium nitride layer 60 may be patterned at the same time during subsequent lower electrode patterning to have the same width as the lower electrode.

As described above, the laminated film of the polysilicon plug 58, the titanium silicide 59, and the titanium nitride film 60 embedded in the second contact hole is referred to as a storage node contact.

Next, after depositing a second conductive film for forming the lower electrode on the second interlayer insulating film 55b, the second conductive film is selectively patterned to be connected to the source electrode 54b of the transistor through the storage node contact. Form 61.

The second conductive layer forming the lower electrode 61 may include any one selected from platinum (Pt), iridium (Ir), iridium oxide (IrO _x ), ruthenium (Ru), Re, Rh, and a composite structure thereof. For example, a laminated film (Ir / IrO _x / Pt) laminated in the order of iridium, iridium oxide and platinum is used. The second conductive film constituting the lower electrode 41 is deposited by one deposition method selected from chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

As shown in FIG. 10B, after depositing the third interlayer dielectric layer 62 on the entire surface including the lower electrode 61, the third interlayer dielectric layer 62 is chemically mechanically disposed until the surface of the lower electrode 61 is exposed. Planarization is performed by polishing or etch back to form a structure in which the lower electrode 61 is embedded in the third interlayer insulating film 62, respectively.

For example, in the case of chemical mechanical polishing of the third interlayer insulating layer 62, the loss of the upper surface of the lower electrode 61 is insignificant, and in the case of the cell region, the dishing phenomenon that is pitted by the loss in a wide region is also short. Because it is small, flattening is possible.

As another method of embedding the lower electrode 61 in the third interlayer insulating film 62, first, the third interlayer insulating film 62 is formed, and then the third interlayer insulating film 62 is selectively etched to form the lower electrode ( 61) may be formed by exposing a portion to be formed, depositing a second conductive film on the entire surface, and then etching back or chemical mechanical polishing.

Meanwhile, the third interlayer insulating layer 62 may be any one selected from silicon oxide based oxides such as TEOS, PSG, and BPSG, silicon nitride based nitrides, and composite structures thereof, and the first and second interlayer insulating films 55a and 55b. ) May also use an insulator applied to the third interlayer insulating film 62.

As shown in FIG. 10C, a ferroelectric film 63 is deposited on the planarized third interlayer insulating film 62. Here, the ferroelectric film 63 is composed of SBT, BLT, PZT, doped SBT, doped BLT, doped PZT, perovskite-structured ferroelectric film and layered perovskite-structured ferroelectric film. It includes any one selected, and is deposited by one deposition method selected from chemical vapor deposition (CVD), spin coating and LSMCD method.

Next, after the fourth interlayer insulating film 65 and the adhesive layer 68 are sequentially formed on the ferroelectric film 63, the adhesive layer 68 and the fourth interlayer insulating film 65 are selectively etched to form the ferroelectric film 63. A contact hole 69 is formed for a capacitor contact (CAPC) exposing a predetermined surface of the capacitor.

Here, the contact hole 69 for the capacitor contact is a portion where the next upper electrode and the ferroelectric layer 63 are to be contacted, and TiO ₂ and Al ₂ O ₃ are used as the adhesive layer 68.

On the other hand, when forming the contact hole 69 for the capacitor contact, the etching of the fourth interlayer insulating film 65 and the adhesive layer 68 is wet etching, which means that the ferroelectric film 63 is degraded during dry etching using plasma. This is to prevent.

As shown in FIG. 10D, after depositing a third conductive film for forming the upper electrode on the front surface including the contact hole 69 for the capacitor contact, the third conductive film is selectively etched to form the upper electrode 64. do.

At this time, the upper electrode 64 is the same as or larger than the lower electrode 61 and arranged in a direction crossing the bit line.

Here, the upper electrode 64 includes any one selected from platinum (Pt), iridium (Ir), iridium oxide (IrO _x ), ruthenium (Ru), Re, Rh, and a composite structure thereof. CVD), physical vapor deposition (PVD) and atomic layer deposition (ALD).

Next, as shown in FIG. 10E, after depositing a metal film for forming the plate line PL on the front surface including the upper electrode 64, the plate line 67 is formed only at one end of the upper electrode 64. Remain.

FIG. 10E is a cross-sectional view taken along the line XX 'of FIG. 10D, and the plate line 67 is connected to only one end of the upper electrode 64 covering the plurality of lower electrodes 61, and is connected to each lower electrode 61. The connected polysilicon plugs 52 are isolated from each other by the field oxide film 52 to isolate each lower electrode 61.

On the other hand, the plate line 67 uses a metal film laminated in the order of TiN / Ti / Al / TiN.

In the above-described fourth embodiment, the upper electrode 64 and the plate line 67 are not simultaneously patterned in addition to the effects of the third embodiment, and only the upper electrode 64 is patterned to be used as the plate line. Since the plate line 67 only needs to be formed at the end of 64, titanium in the plate line 67 is prevented from diffusing into the ferroelectric film 63 and deteriorating the ferroelectric properties. Since the burden is minimal, it is easy to secure contact resistance by embedding plate lines there.

11A to 11D are cross-sectional views illustrating a method of manufacturing the ferroelectric memory device according to the fifth embodiment of the present invention, and have the same equivalent circuit and layout as those of the third embodiment. The difference is that the capacitor contacts are configured between the top electrode and the plate line.

As shown in FIG. 11A, a field oxide film 72 is formed on the semiconductor substrate 71 in which the cell region I and the peripheral circuit region II are defined, for isolation between devices, and the cell on the semiconductor substrate 71 is formed. After forming the word lines 73 arranged side by side at a predetermined distance in the region I, the source / drains 74a, 74b of the transistor are formed through an ion implantation process in the semiconductor substrate 81 on both sides of the word line 73. 74c).

Here, one source / drain 74a among the sources / drains 74a, 74b, and 74c serves as a common junction region of two transistors connected to the bit line BL1 of a subsequent cell region (hereinafter, referred to as 'common drain'). box). Accordingly, the other source / drain 74b becomes a source (hereinafter, abbreviated as 'source') of each transistor, and the source / drain 74c formed in the peripheral circuit region II is a bit of the subsequent peripheral circuit region II. The line BL _p is to be connected.

Next, after depositing and planarizing the first interlayer insulating film 75a on the entire surface including the transistor formed by the above-described process, the first interlayer insulating film 75a is selectively etched to form the common drain 74a and the peripheral circuit region ( A first contact hole (not shown) exposing the source / drain 74c of II) is formed, and a tungsten plug 76 is embedded in the first contact hole.

Next, after depositing a first conductive film for forming a bit line on the first interlayer insulating film 75a in which the tungsten plug 76b is embedded, the first conductive film is selectively patterned to be common through the tungsten plug 76. The bit line 77 connected to the drain 74a and the source / drain 74c is formed.

Next, after depositing and planarizing the second interlayer insulating film 75b on the first interlayer insulating film 75a including the bit line 77, the second interlayer insulating film 75b and the first interlayer insulating film 75a are sequentially formed. Etching to form a second contact hole (not shown) exposing the source 74b of each transistor.

Subsequently, polysilicon is deposited on the entire surface including the second contact hole, and the polysilicon plug 78 is partially embedded in the second contact hole through an etch back process, and then titanium silicide 79 is deposited on the polysilicon plug 78. ).

Here, the titanium silicide 79 is formed through titanium deposition and heat treatment, and an etching process for removing unreacted titanium is performed after the heat treatment.

The above-mentioned polysilicon plug / titanium silicide 78/79 is all connected to the source 74b of the transistor, and is formed in a structure partially buried in the second contact hole.

Next, after depositing a titanium nitride film (TiN) 80 as a barrier film on the entire surface including the titanium silicide 79, the titanium nitride film on the second interlayer insulating film 75b is removed by etching back or chemical mechanical polishing. 2 It is left only in the contact hole.

Here, the titanium nitride film 80 is a barrier film for preventing oxygen from diffusing into the polysilicon plug 78 through the lower electrode during the heat treatment of the subsequent ferroelectric film. Such a barrier film may include TiAlN, in addition to the titanium nitride film 80. Any one selected from TiSiN and composites thereof (eg TiSiN / TiN) can be used.

In addition, the barrier layer including the titanium nitride layer 80 may be patterned at the same time during subsequent lower electrode patterning to have the same width as the lower electrode.

As described above, the laminated film of the polysilicon plug 78, the titanium silicide 79, and the titanium nitride film 80 embedded in the second contact hole is referred to as a storage node contact (SNC).

Next, after depositing a second conductive film for forming the lower electrode on the second interlayer insulating film 75b, the second conductive film is selectively patterned and connected to the source 74b of the transistor through the storage node contact (SNC). The lower electrode 81 is formed.

Here, the second conductive film forming the lower electrode 81 includes any one selected from platinum (Pt), iridium (Ir), iridium oxide (IrO _x ), ruthenium (Ru), Re, Rh, and a composite structure thereof. For example, a laminated film (Ir / IrO _x / Pt) laminated in the order of iridium, iridium oxide and platinum is used. The second conductive film constituting the lower electrode 41 is deposited by one deposition method selected from chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

As shown in FIG. 11B, after the third interlayer insulating film 82 is deposited on the entire surface including the lower electrode 81, the third interlayer insulating film 82 is chemically mechanically disposed until the surface of the lower electrode 81 is exposed. Planarization is performed by polishing or etch back to form a structure in which the lower electrode 81 is embedded in the third interlayer insulating film 82, respectively.

Here, as another method of embedding the lower electrode 81 in the third interlayer insulating film 82, first the third interlayer insulating film 82 is formed, and then the third interlayer insulating film 82 is selectively etched to form the lower electrode ( 81) may be formed by exposing a portion to be formed, depositing a second conductive film on the entire surface, and then etching back or chemical mechanical polishing.

Meanwhile, the third interlayer insulating film 82 may be any one selected from silicon oxide based oxides such as TEOS, PSG, and BPSG, silicon nitride based nitrides, and composite structures thereof, and the first and second interlayer insulating films 75a and 75b. ) May also use an insulator applied to the third interlayer insulating film 82.

As shown in FIG. 11C, after the ferroelectric film 83 is deposited on the planarized third interlayer insulating film 82, only the portions formed in the peripheral circuit region II are selectively removed to ferroelectric only in the cell region I. The film 83 is left.

Here, the ferroelectric film 83 is composed of SBT, BLT, PZT, doped SBT, doped BLT, doped PZT, doped PZT, perovskite structure and ferroelectric film having a layered perovskite structure. It includes any one selected, and is deposited by one deposition method selected from chemical vapor deposition (CVD), spin coating and LSMCD method.

Next, after depositing a third conductive film for forming the upper electrode TE on the entire surface including the ferroelectric film 83, the third conductive film is selectively patterned to sandwich the lower electrode 81 with the ferroelectric film 83 therebetween. ) And an upper electrode 84 forming a capacitor.

Next, a fourth interlayer insulating film 85 is deposited on the entire surface including the upper electrode 84.

Here, the upper electrode 84 includes any one selected from platinum (Pt), iridium (Ir), iridium oxide (IrO _x ), ruthenium (Ru), Re, Rh, and a composite structure thereof. CVD), physical vapor deposition (PVD) and atomic layer deposition (ALD).

As shown in FIG. 11D, after the fourth interlayer dielectric layer 85 is deposited, contact etching is performed to connect the plate lines. First, only the fourth interlayer dielectric layer 85 of the cell region I is selectively etched. After the capacitor contact hole is formed to expose a predetermined surface of the upper electrode 84, the fourth interlayer insulating film 84, the third interlayer insulating film 82, and the second interlayer insulating film 75b of the peripheral circuit region II are formed. Is selectively etched to form a metallization contact hole exposing a predetermined surface of the bit line 77.

Meanwhile, the metallization contact hole may be simultaneously formed when forming the capacitor contact hole.

Subsequently, after the diffusion barrier film 86 is deposited on the entire surface including the capacitor contact hole and the metal wiring contact hole, the diffusion barrier film 86 is selectively patterned so as to remain only in the capacitor contact hole.

Here, as the diffusion barrier film 86, one selected from TiN, Ti, and Ti / TiN is used.

Next, after depositing a metal film for forming metal wiring on the entire surface including the diffusion barrier film 86, the metal film is selectively patterned to form plate lines PL and 87 connected to the upper electrode 84. At the same time, the metal wiring 88 of the peripheral circuit region II is formed.

Since the ferroelectric layer 83 is not etched in the cell region I, the fifth embodiment suppresses deterioration due to the etching of the ferroelectric layer 83 and reduces the size of the upper electrode 84 and the lower electrode 81. The same patterning allows for more charge within a given capacitor size.

In addition, since the ferroelectric film 83 does not remain in the peripheral circuit region II, an etching process for forming a contact hole for metal wiring in the subsequent peripheral circuit region II is easy. That is, since only the interlayer insulating films remain, the etching may be performed in one step than when the ferroelectric film remains relatively.

In the above-described embodiment, the FeRAM cell using the ferroelectric film has been described, but as another embodiment, the present invention can also be applied to DRAM using a high dielectric material such as BST and Ta ₂ O ₅ .

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention as described above does not pattern the ferroelectric film, so that the size of the upper and lower electrodes can be the same without the risk of short circuit between the upper and lower electrodes, thereby increasing the amount of charge that can be stored in the capacitor, and the ferroelectric generated during the etching process of the ferroelectric film. Deterioration of the characteristics can be prevented, and thus the stability of the process can be improved.

In addition, the step difference caused by the capacitor can be reduced, thereby reducing the burden on the masking operation and improving the difficulty of flattening.

In addition, when a structure without contact between the upper electrode and the plate line is implemented, a short circuit risk between the plate line and the lower electrode may be prevented.

In addition, it is possible to apply only by changing the process while using the conventional layout, and to reduce the number of reticles, and to increase the storage node contact resistance between the lower electrode and the plug by using a silicon nitride film as an insulating film surrounding the lower electrode. It has an effect.

In addition, it is possible to form a capacitor contact only at one end of the plate line without forming a capacitor contact in each capacitor, thereby simplifying the process of avoiding the difficulty of forming a contact in each capacitor when the cell area is reduced. have.

Claims (14)

A substrate in which a cell region and a peripheral circuit region are defined; A plurality of lower electrodes formed on the cell region; A first insulator which insulates the plurality of lower electrodes from each other and has a surface that is planarized with the surfaces of the plurality of lower electrodes and formed over the entire area of the substrate; A ferroelectric film covering the first insulator including the plurality of lower electrodes and formed only on the cell region; And A plurality of upper electrodes on the ferroelectric film, each having a size larger than at least the plurality of lower electrodes and opposing the plurality of lower electrodes in one direction and respectively facing the plurality of lower electrodes in the other direction A ferroelectric memory device, characterized in that it comprises a. The method of claim 1, A second insulator having a plurality of contact holes exposing predetermined portions of the plurality of upper electrodes facing the plurality of lower electrodes and formed in an entire area including the plurality of upper electrodes; And And a plate line for simultaneously connecting the plurality of upper electrodes through the plurality of contact holes of the second insulator. The method of claim 1, A second insulator having one contact hole exposing one end of each of the plurality of upper electrodes and covering an entire area including the plurality of upper electrodes; And A plurality of plate lines connected to each of the plurality of upper electrodes through contact holes of the second insulator; A ferroelectric memory device, characterized in that consisting of. The method of claim 1, A plurality of plate lines stacked on the plurality of upper electrodes with the same width as the plurality of upper electrodes to form a first stacked film; And A second insulating film and a second insulating film of the adhesive layer to insulate the first laminated film from each other A ferroelectric memory device, characterized in that it comprises a. The method of claim 1, And each of the plurality of upper electrodes has a first portion commonly covering the plurality of lower electrodes in the other direction and a second portion extending from the first portion. The method of claim 5, Each of the plurality of upper electrodes includes a second insulator having a contact hole for opening a predetermined surface of the second portion and covering the plurality of upper electrodes; And A plate line having a smaller size than the second portion while being in contact with each of the plurality of upper electrodes through the contact hole A ferroelectric memory device, characterized in that it comprises a. The method of claim 5, Each of the plurality of upper electrodes is connected to the ferroelectric layer through the contact holes of the second insulator layer stacked in the order of a second insulator and an adhesive layer having a contact hole exposing a predetermined surface of the ferroelectric layer and the front surface of the second laminate layer. A ferroelectric memory device, characterized in that formed in. The method according to claim 4 or 7, The adhesive layer is a ferroelectric memory device, characterized in that one selected from TiO ₂ and Al ₂ O ₃ . Forming a plurality of lower electrodes on the cell region of the substrate where a cell region and a peripheral circuit region are defined; Forming a first insulator on the front surface including the plurality of lower electrodes; Planarizing the first insulator to expose surfaces of the plurality of lower electrodes; Forming a ferroelectric film on the first insulator including the plurality of lower electrodes; Selectively etching the ferroelectric film and remaining only in the cell region; And On the remaining ferroelectric film, a plurality of upper electrodes having a size larger than at least the plurality of lower electrodes and opposing the plurality of lower electrodes in one direction and respectively opposed to the plurality of lower electrodes in the other direction Forming steps Method of manufacturing a ferroelectric memory device, characterized in that it comprises a. The method of claim 9, Exposing the surfaces of the plurality of lower electrodes, A method of manufacturing a ferroelectric memory device, characterized in that the first insulating material is made by chemical mechanical polishing or etch back. The method of claim 9, In the step of forming a plurality of upper electrodes commonly opposed to the plurality of lower electrodes in the other direction, And each of the plurality of upper electrodes is formed on the ferroelectric film with a first portion commonly covering the plurality of lower electrodes and a second portion extending from the first portion. The method of claim 11, Forming a second insulator on the front surface including the plurality of upper electrodes; Selectively etching the second insulator to form a contact hole exposing the second portion of each of the plurality of upper electrodes; And Forming a plurality of plate lines overlapping each of the plurality of upper electrodes while contacting the second portion exposed by the contact hole on the second insulator. Method of manufacturing a ferroelectric memory device, characterized in that it comprises a. The method of claim 11, Forming a second insulator on the front surface including the plurality of upper electrodes; Selectively etching the second insulator to form a contact hole exposing the second portion of each of the plurality of upper electrodes; And Forming a plurality of plate lines having a smaller size than the second portion while being in contact with the second portion exposed by the contact hole on the second insulator. Method of manufacturing a ferroelectric memory device, characterized in that it comprises a. The method according to claim 12 or 13, And the second insulating material includes an adhesive layer adhered to the plurality of upper electrodes.