KR20050041185A - Method for fabricating ferroelectric random access memory having bottom electrode isolated by dielectric - Google Patents

Abstract

The present invention provides a method of manufacturing a ferroelectric memory device suitable for preventing the lower electrode surface from being damaged during the planarization of the isolation insulating film for separation between the lower electrodes, the present invention comprises the steps of forming an interlayer insulating film on the semiconductor substrate Forming a stacked layer stacked on the interlayer insulating layer in the order of a lower electrode and a hard mask; forming a separated insulating layer on the entire surface including the stacked layer; and planarizing the separated insulating layer until the surface of the hard mask is exposed. Removing the hard mask by wet etching; forming a ferroelectric film on the entire surface including the lower electrode exposed after removing the hard mask; and forming an upper electrode on the ferroelectric film. According to the present invention, the chemical mechanical polishing or etch back process of the isolation insulating film The surface of the lower electrode is very uniform By the hard mask protecting the damage to the electrode surface and can obtain a uniform performance of the capacitor to prevent subsequent non-uniform growth of the ferroelectric film.

Description

A method of manufacturing a ferroelectric memory device having a structure in which a lower electrode is separated by an insulating layer {METHOD FOR FABRICATING FERROELECTRIC RANDOM ACCESS MEMORY HAVING BOTTOM ELECTRODE ISOLATED BY DIELECTRIC}

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a ferroelectric memory device.

In general, by using a ferroelectric thin film in a ferroelectric capacitor in a semiconductor memory device, the development of a device capable of using a large-capacity memory while overcoming the limitation of refresh required in a DRAM (Dynamic Random Access Memory) device is in progress. come. A ferroelectric random access memory (FeRAM) device using such a ferroelectric thin film is a kind of nonvolatile memory device, which not only stores stored information even when power is cut off, but also operates at a speed of DRAM. It is comparable to the next generation memory device.

The ferroelectric memory device uses a material different from DRAM as a material of a storage node. That is, Y-1 or BLT is used as the ferroelectric thin film, and Pt, Ir, IrO ₂ , Ru, RuO ₂ are used as the material of the storage electrode. Such metal materials have difficulty in the deposition process and the etching process, thereby forming a storage electrode having a simple stack structure.

However, as ferroelectric memory devices are increasingly integrated, the storage electrodes of simple stacked structures have a limitation in improving the pattern density due to the planar structure. In particular, even in subsequent processes, short circuits due to severe topology problems, that is, poor planarization, are prevented. As a result, there is a need for a storage electrode having a new structure.

Techniques for ameliorating poor planarization in subsequent processes are illustrated in the accompanying drawings, FIGS. 1A-1C.

1A to 1C are cross-sectional views illustrating a method of manufacturing a ferroelectric memory device according to the prior art.

As shown in FIG. 1A, an isolation layer 12 defining an active region is formed on the semiconductor substrate 11, and a word line 13 is formed on the semiconductor substrate 11. Although not shown here, as is well known, a gate insulating film exists under the word line 13, and a source / drain region of a transistor may be formed in the semiconductor substrate 11 on both sides of the word line 13.

Next, after the first interlayer insulating film 14 is formed on the semiconductor substrate 11 including the word line 13, the bit is connected to a part of the semiconductor substrate 11 through the first interlayer insulating film 14. The line contact 15 and the bit line 16 are formed.

Subsequently, after the second interlayer insulating film 17 is formed on the entire surface including the bit line 16, the second interlayer insulating film 17 and the first interlayer insulating film 14 are simultaneously penetrated to rest the remaining portion of the semiconductor substrate 11. The storage node contact 18 is formed in contact with each other.

Thereafter, a lower electrode 19 having a stacked structure connected to the storage node contact 18 is formed.

Next, a separation insulating film 20 for isolation between lower electrodes is formed on the entire surface including the lower electrode 19.

As shown in FIG. 1B, the isolation insulating layer 20 is planarized by chemical mechanical polishing or etch back until the surface of the lower electrode 19 is exposed.

As shown in FIG. 1C, after the ferroelectric film 21 is formed on the planarized isolation insulating film 20 and the lower electrode 19, the upper electrode 22 is formed on the ferroelectric film 21.

The above-described prior art flattens the substructure before the formation of the ferroelectric film 21, thereby suppressing the short circuit of the subsequent metal wiring caused by the poor planarization.

However, in the chemical mechanical polishing (CMP) or etch back process to planarize the isolation insulating film 20, the surface of the lower electrode 19 is damaged by physical or plasma, resulting in a very uneven surface of the lower electrode. ) A problem of deterioration of the characteristics of the capacitor is caused by poor growth.

The present invention has been made to solve the above problems of the prior art, and provides a method of manufacturing a ferroelectric memory device suitable for preventing damage to the lower electrode surface during planarization of the isolation insulating film for separation between the lower electrodes. There is this.

According to another aspect of the present invention, there is provided a method of manufacturing a ferroelectric memory device, including forming an interlayer insulating layer on an upper surface of a semiconductor substrate, and forming a laminated film laminated on the interlayer insulating layer in the order of a lower electrode and a hard mask. Forming a separation insulating film on the entire surface including a film, planarizing the separation insulating film until the surface of the hard mask is exposed, removing the hard mask by wet etching, and removing the lower electrode exposed after removing the hard mask. Forming a ferroelectric film on the entire surface including, and forming an upper electrode on the ferroelectric film.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

2A to 2F are cross-sectional views illustrating a method of manufacturing a ferroelectric memory device according to an embodiment of the present invention.

As shown in FIG. 2A, an isolation layer 32 defining an active region is formed on the semiconductor substrate 31, and a word line 33 is formed on the semiconductor substrate 31. Although not shown, a gate insulating film is present under the word line 33 as is well known, and a source / drain region of a transistor may be formed in the semiconductor substrate 31 on both sides of the word line 33.

Next, after the first interlayer insulating film 34 is formed on the semiconductor substrate 31 including the word line 33, the bit is connected to a part of the semiconductor substrate 31 through the first interlayer insulating film 34. The line contact 35 and the bit line 36 are formed.

Subsequently, after the second interlayer insulating film 37 is formed on the entire surface including the bit line 36, the second interlayer insulating film 37 and the first interlayer insulating film 34 are simultaneously penetrated to rest the remaining portion of the semiconductor substrate 31. A storage node contact 38 is in contact with each other. Here, the storage node contact 38 is, for example, a structure laminated in the order of polysilicon plug, titanium silicide, and titanium nitride, and a method of forming them is omitted. Let's do it.

Next, the conductive layer 39 and the hard mask 40 that form the lower electrode are sequentially formed on the second interlayer insulating layer 37 including the storage node contact 38. The conductive film 39 constituting the lower electrode is a stacked structure, for example, a film laminated in the order of iridium (Ir), iridium oxide film (IrO ₂ ), and platinum (Pt). The hard mask 40 is used as a hard mask when patterning the lower electrode, and the hard mask 40 is formed of a titanium nitride film TiN. At this time, the titanium nitride film used as the hard mask 40 is deposited to a thickness of 50 kPa to 1000 kPa.

Next, after the photoresist pattern 41 is formed on the hard mask 40 to define the lower electrode, the hard mask 40 is etched using the photoresist pattern 41 as an etch barrier.

As shown in FIG. 2B, after removing the photoresist pattern 41, the conductive layer 39 is etched using the etched hard mask 40 as an etch barrier to form the lower electrode 39a.

As described above, when the lower electrode 39a is formed, the hard mask 40 is partially consumed and the thickness remains on the lower electrode 39a.

As shown in FIG. 2C, a separation insulating film 42 for separating between adjacent lower electrodes 39a is formed on the entire surface. At this time, the isolation insulating film 42 is formed of an HDP (High Density Plasma) oxide film, BPSG, SOG, or PSG, and has a thickness of 1000 kPa to 10,000 kPa.

As illustrated in FIG. 2D, the chemical insulating polishing (CMP) or etch back process is performed until the surface of the hard mask 40 is exposed to planarize the isolation insulating layer 42. At this time, since the hard mask 40 caps the upper portion of the lower electrode 39a, the surface of the lower electrode 39a is prevented from being lost during chemical mechanical polishing or etch back process.

As shown in FIG. 2E, the hard mask 40 remaining on the lower electrode 39a is removed. Here, the reason for removing the hard mask 40 is that when the hard mask 40 is left without being removed, the metal component of the hard mask 40 is oxidized during the subsequent ferroelectric film growth and heat treatment, thereby lifting and This is because the rapid deterioration of the polarization value leads to a decrease in reliability.

When the hard mask 40 is removed, a wet etching process using a wet etching solution such as SC-1 chemical is used, and when the hard mask 40 is removed, an oxide insulating separation layer 42 is easily removed, so that the lower electrode 39a is removed. A part of the isolation insulating film 42 is removed and planarized until the surface is exposed. As such, the wet etching solution used for removing the hard mask 40 uses a solution capable of etching the oxide layer while etching the metal layer.

SC-1 chemical used for removing the hard mask 40 as described above is a mixed solution of NH ₄ OH / H ₂ O ₂ / H ₂ O, which is used as the hard mask 40 because of excellent reactivity with the metal film. The titanium nitride film can be easily removed. In addition, since SC-1 chemical does not apply a plasma loss to the lower electrode 39a, the lower electrode 39a having a very uniform surface can be obtained.

By forming the lower electrode 39a in the form of being surrounded by the isolation insulating film 42 by a series of steps as described above, it is possible to prevent the burden and planarization of the mask work due to the step difference of the capacitor, and short circuit between the upper and lower electrodes. Has the advantage.

On the other hand, when the hard mask 40 is removed by a dry etching method using plasma, since the lower electrode 39a exposed after removing the hard mask 40 is damaged by plasma, a wet etching process is necessarily used.

As shown in FIG. 2F, after the hard mask 40 is removed, the ferroelectric film 43 is grown to a thickness of 50 Å to 3000 에 on the entire structure having the planarized structure, and the upper electrode 45 on the ferroelectric film 44. To form. Here, the ferroelectric film 43 is grown on the lower electrode 39a having a very uniform surface, thereby obtaining uniform growth characteristics.

On the other hand, as the ferroelectric film 43, SBT [SrBi ₂ Ta ₂ O ₉ ], SBTN [SrBi ₂ (Ta _1-x , Nb _x ) ₂ O ₉ ], BTO (Bi ₄ Ti ₃ O ₁₂ ), BLT [Bi _1-x , La _x ) Ti ₃ O ₁₂ ] or PZT [(Pb, Zr) TiO ₃ ] or a combination thereof, and the ferroelectric film 43 is spin coated or LSMCD (Liquid). It is formed to a thickness of 50 ~ 3000 ~ by using a Source Mixed Chemical Deposition) method.

In addition, the upper electrode 45 may be formed by depositing one selected from chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and plasma enhanced layer deposition (PEALD). It is deposited by using one of platinum (Pt), iridium (Ir), ruthenium (Ru), tungsten (W), iridium oxide film, ruthenium oxide film, tungsten nitride film or titanium nitride film or a composite structure thereof. .

In the above-described embodiment, the lower electrode of the stacked structure is taken as an example, but it is also applicable to the case where the lower electrode is a single metal layer. At this time, the metal film is selected from Pt, Ru, Ir, W or WN as in the embodiment.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention described above, the hard mask protects the surface of the lower electrode during the chemical mechanical polishing or etch back process of the isolation insulating layer so that the surface of the lower electrode is very uniform, thereby preventing uneven growth of the subsequent ferroelectric film, thereby obtaining uniform capacitor performance. It can be effective.

1A to 1C are cross-sectional views illustrating a method of manufacturing a ferroelectric memory device according to the prior art;

2A to 2F are cross-sectional views illustrating a method of manufacturing a ferroelectric memory device according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

31: semiconductor substrate 32: device isolation film

33: word line 34: first interlayer insulating film

35: bit line contact 36: bit line

37: second interlayer insulating film 38: storage node contact

39a: lower electrode 40: hard mask

42: isolation insulating film 43; Ferroelectric film

44: upper electrode

Claims (6)

Forming an interlayer insulating film on the semiconductor substrate; Forming a laminated film stacked on the interlayer insulating film in the order of a lower electrode and a hard mask; Forming a separation insulating film on the entire surface including the laminated film; Planarizing the isolation insulating film until the surface of the hard mask is exposed; Removing the hard mask through wet etching; Forming a ferroelectric film on the entire surface including the lower electrode exposed after removing the hard mask; And Forming an upper electrode on the ferroelectric film A method of manufacturing a ferroelectric memory device, characterized in that it comprises a. The method of claim 1, Forming the laminated film of the lower electrode and the hard mask, Sequentially forming a lower electrode conductive film and a hard mask on the interlayer insulating film; Forming a photoresist pattern defining a lower electrode on the hard mask; Etching the hard mask using the photoresist pattern as an etching barrier; Removing the photoresist pattern; Etching the lower electrode conductive layer using the etched hard mask as an etching barrier; A method of manufacturing a ferroelectric memory device, characterized in that it comprises a. The method according to claim 1 or 2, And said hard mask is formed of a titanium nitride film. The method of claim 3, And the titanium nitride film has a thickness of 50 kV to 1000 kV. The method of claim 1, Removing the hard mask through wet etching, And a wet etching solution for etching the separation insulating layer while etching the hard mask. The method of claim 5, The wet etching solution is a method of manufacturing a ferroelectric memory device, characterized in that using the SC-1 chemical mixture of NH ₄ OH / H ₂ O ₂ / H ₂ O.