KR100968428B1 - Fabricating method for protecting loss of area of ferroelectric capacitor - Google Patents

Abstract

In the present invention, when forming a stacked capacitor, the etching process for forming the capacitor is performed by dividing the etching process horizontally and vertically, thereby suppressing the occurrence of rounding occurring at the corners of the rectangular capacitors, thereby preventing the reduction of the effective area of the capacitors. Invention. To this end, the present invention comprises the steps of forming a conductive film for the lower electrode of the capacitor on a substrate having a predetermined substructure including a storage node contact plug; Patterning the conductive film for the lower electrode, and performing patterning by dividing into two steps of a first direction and a second direction; And forming a ferroelectric film and an upper electrode on the patterned lower electrode.

Stacked Capacitors, Ferroelectric, Rounding, Effective Area

Description

TECHNICAL FIELD OF THE INVENTION Capacitor Manufacturing Method Preventing the Reduced Area of Ferroelectric Capacitors {FABRICATING METHOD FOR PROTECTING LOSS OF AREA OF FERROELECTRIC CAPACITOR}             

1A is a cross-sectional view showing a cross section in which a lower electrode of a capacitor is first patterned according to the prior art;

FIG. 1B is a cross-sectional view showing a cross section when a capacitor is formed by sequentially stacking a lower electrode, a dielectric, and an upper electrode of a capacitor and patterning the same according to the prior art; FIG.

2a to 2b is a SEM photograph showing the rounding occurs in the corner portion when forming a ferroelectric capacitor according to the prior art,

3 is a cross-sectional view illustrating a hard mask and a photosensitive film formed on the lower electrode in order to pattern the lower electrode of the capacitor according to an embodiment of the present invention;

4A is a plan view showing a state in which the lower electrode is first patterned in the horizontal direction according to one embodiment of the present invention;

FIG. 4B is a sectional view showing a section along the line AA ′ shown in FIG. 4A;

4C is a cross-sectional view illustrating a cross section taken along the line BB ′ shown in FIG. 4A;

5A is a plan view showing how a photosensitive film pattern is formed to pattern a lower electrode in a vertical direction;

5B is a plan view illustrating a state after an etching process using the photosensitive film pattern of FIG. 5A is performed;

6 is a cross-sectional view showing a state in which the lower electrode is completed according to an embodiment of the present invention;

Figure 7 is a cross-sectional view showing a state completed until the dielectric, the upper electrode and the metallization process according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

21: lower film 22: first interlayer insulating film

23: storage node contact plug 24: barrier metal

25: lower electrode 26: hard mask

27a, 27b: Photosensitive film 28: Second interlayer insulating film

29 ferroelectric 30 upper electrode

31: third interlayer insulating film 32: diffusion barrier film

33: metal wiring

The present invention relates to a method for manufacturing a capacitor of a ferroelectric memory device, and in particular, by performing an etching process for forming a capacitor divided into a horizontal direction and a vertical direction, thereby preventing rounding occurring at the corners of the rectangular capacitor to prevent an effective area reduction. Invention.

In general, by using a ferroelectric layer as a dielectric of a capacitor in a semiconductor memory device, development of a device capable of using a large-capacity memory to overcome the limitation of refresh required in a DRAM (Dynamic Random Access Memory) device Has been going on.

A ferroelectric memory device (hereinafter referred to as 'FeRAM') using the ferroelectric film is a kind of nonvolatile memory device, which not only stores the stored information even when the power is cut off. In addition, the operation speed is comparable to DRAM, and is becoming a popular next-generation memory device.

A nonvolatile memory device using a ferroelectric film inputs a signal by adjusting the direction of polarization in the direction of an applied electric field and stores the digital signals '1' and '0' by the direction of residual polarization remaining when the electric field is removed. Hysteresis characteristics are used.

Dielectrics of such FeRAM devices include (Bi, La) ₄ Ti ₃ O ₁₂ (hereinafter BLT), SrBi ₂ Ta ₂ O ₉ (hereinafter SBT), and Pb (Zr, Ti) O having a perovskite structure. Ferroelectric films such as ₃ (hereinafter PZT) and Sr _x Bi _y (Ta _i Nb _j ) ₂ O ₉ (hereinafter referred to as SBTN) are mainly used.The ferroelectric film has a constant dielectric constant of several hundred to thousands at room temperature and has two stable residual polarizations (Remnant). It has a polarization (Pr) state and has been thinned to realize application to nonvolatile memory devices.

A method of forming a stack type capacitor according to the prior art using such a ferroelectric as a dielectric of a capacitor is shown in FIGS. 1A to 1B.

First, FIG. 1A illustrates a method of stacking a lower electrode 15 first and then stacking a dielectric and an upper electrode thereon. In FIG. 1A, the dielectric and the upper electrode are not shown. Only the patterned bottom electrode is shown.

In addition, FIG. 1B is a diagram in which a stacked capacitor is formed by sequentially stacking a lower electrode dielectric and an upper electrode and then etching the same at a time. First, a method of forming a capacitor shown in FIG. 1A will be described.

Referring to the foregoing, first, an interlayer insulating film 12 is formed on a semiconductor substrate 11 on which predetermined substructures (eg, word lines and bit lines) are formed, and then the interlayer insulating film 12 is selectively etched. As a result, a contact hole for exposing the semiconductor substrate 11 is formed.

Subsequently, a conductive film (for example, polysilicon) is coated on the interlayer insulating layer 12 including the contact hole, and then subjected to an etch Beck process or chemical mechanical polishing (CMP). The contact plug 13 is formed.                         

Subsequently, a barrier metal 14 is formed on the entire structure to prevent oxidation of the storage node contact plug 13 and to prevent mutual diffusion between upper and lower layers, and a lower portion of the barrier metal 14 is disposed on the lower portion of the barrier metal 14. An electrode conductive film 15 is formed.

Next, the lower electrode conductive layer 15 and the barrier metal 14 are etched using an appropriate mask to isolate the lower electrode. In this case, an etching process for isolating the lower electrode is performed at once using one mask.

When the lower electrode is patterned in a plan view, each patterned lower electrode should have a rectangular shape, but rounding occurs at the corners of the rectangular shape, so that the overall shape of the capacitor has an elliptical shape, which is the effective area of the capacitor. This results in a decrease of which will be described later with reference to FIGS. 2A to 2B.

After the lower electrode is patterned in this manner, although not shown in FIG. 1A, the ferroelectric film and the upper electrode are sequentially stacked on the lower electrode to complete capacitor formation.

In addition to the method illustrated in FIG. 1A, after stacking the lower electrode, the dielectric, and the upper electrode in order, there is a method of forming the stacked capacitor by etching them at once and this will be described with reference to FIG. 1B.

First, as shown in FIG. 1B, the process of forming the storage node contact plug 13 is the same as the manufacturing method of FIG. 1A, and thus description thereof will be omitted.

Next, the barrier metal 14, the lower electrode 15, the ferroelectric layer 16, and the upper electrode 17 are sequentially stacked on the interlayer insulating layer 12 including the storage node contact plug 13.

Subsequently, the barrier metal 14, the lower electrode 15, the ferroelectric layer 16, and the upper electrode 17 are etched at once using one mask to complete capacitor formation.

As described above, when the capacitor is formed in plan view, it should have a rectangular shape, but due to the same reasons as described above, rounding occurs at the corners of the rectangular shape, thereby reducing the effective area of the capacitor.

2A to 2B are SEM photographs showing rounding at corners when ferroelectric capacitors are formed according to the method shown in FIG. 1B. FIG. 2A to FIG. An enlarged view of the capacitor is shown.

In the method of forming a capacitor according to the prior art, since such rounding forms an elliptical capacitor rather than a rectangular shape, there is a disadvantage in that the effective area of the capacitor is reduced.

Also, after the lower electrode is patterned according to the manufacturing method shown in FIG. 1A, the shape of the lower electrode also has a similar elliptical shape as in the SEM photographs shown in FIGS.

The reduction of the effective area of the capacitor means a reduction in the polarization value of the capacitor, and this problem becomes more serious as the area of the memory cell is reduced for higher integration of the memory device.

The present invention has been made to solve the problems of the prior art, by performing the etching process for forming the capacitor divided into the horizontal direction and the vertical direction, respectively, to suppress the occurrence of rounding to reduce the capacitor effective area of the ferroelectric capacitor It is an object to provide a manufacturing method.

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According to an aspect of the present invention, a barrier metal, a lower electrode conductive film, a hard mask, and a patterned first photoresist film are sequentially formed on a substrate on which a predetermined substructure including a storage node contact plug is completed; Patterning the conductive film for the lower electrode in a first direction by using the first photosensitive film and the hard mask; Forming a second photosensitive film for patterning the conductive film for the lower electrode in a second direction; Patterning the conductive film for the lower electrode in a second direction by using the second photosensitive film and the hard mask; And sequentially forming a ferroelectric film and an upper electrode on the patterned lower electrode.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

As a method of forming a stacked capacitor, first, there may be a manufacturing method of forming a dielectric and an upper electrode after patterning a lower electrode first, and, secondly, after forming a lower electrode, a dielectric, and an upper electrode sequentially There may be a method of manufacturing a capacitor by etching the lower electrode, the dielectric and the upper electrode at once.

3 to 7 illustrate a manufacturing method of forming a dielectric and an upper electrode after first patterning a lower electrode of a capacitor. Referring to this, a ferroelectric capacitor is manufactured according to an embodiment of the present invention. Explain how.

First, FIG. 3 is a cross-sectional view illustrating a hard mask and a photosensitive film formed on the lower electrode in order to pattern the lower electrode. Referring to Figure 3, the process up to forming the storage node contact plug 23 is the same as in the prior art.

That is, after the first interlayer insulating film 22 is formed on the semiconductor substrate 21 on which a predetermined substructure (eg, word line, bit line, source / drain region, etc.) is formed, the first interlayer insulating film 22 is formed. ) Is selectively etched to form a contact hole through which the semiconductor substrate 21 is exposed.

Subsequently, a conductive film (polysilicon) is applied on the first interlayer insulating film 22 including the contact hole and the inside of the contact hole is filled with a conductive film, followed by an etch-beck process or chemical mechanical polishing. The contact plug 23 is completed.                     

Subsequently, a barrier metal 24 is formed on the first interlayer dielectric layer 22 including the storage node contact plug. The barrier metal prevents the storage node contact plug 23 from being oxidized in a subsequent high temperature process, and also prevents the interdiffusion of materials forming a layer formed on the upper and lower portions of the barrier metal.

As such a barrier metal, TiN, TiAlN, TiSiN, RuTiN, or the like can be used, or a laminate thereof can be used, and the thickness of the barrier metal is 100 to 3000 kPa.

Subsequently, the barrier metal 24 and the lower electrode 25 are stacked to form. The lower electrode may be formed by laminating one or several kinds of metal electrodes. For example, iridium (Ir), A lower electrode having a structure in which an iridium oxide film (IrO ₂ ) and platinum (Pt) are stacked may be used.

Next, a hard mask 26 and a photoresist pattern 27a are formed on the lower electrode 25. The hard mask furnace 26 can use TiN, TiAlN, TiSiN, RuTiN, etc., or can laminate these, The thickness of a hard mask shall be 100-3000 GPa.

Here, the photoresist pattern 27a and the hard mask 26 are for etching and patterning the lower electrode 25. In the exemplary embodiment of the present invention, the etching process for patterning the lower electrode is performed in two steps. The difference is that.

That is, in the prior art, the lower electrode is patterned using one mask. However, in the exemplary embodiment of the present invention, after the lower electrode is first patterned in the horizontal direction (or vertical direction), the new photoresist pattern is used in the vertical direction. The lower electrode is patterned in the horizontal direction.

In addition, in an embodiment of the present invention, the lower electrode patterning process is divided into two stages of the horizontal patterning process and the vertical patterning process perpendicular to the horizontal direction (90 °), but the orthogonal (90 °) It is not limited only to a direction, The internal angle which both directions make may change between 10-90 degrees.

This will depend on the planar shape of the capacitor. In recent years, instead of the conventional rectangular capacitor shape for the high integration of the device, research on the rhombus shape or the polygon type capacitor is being conducted. The present invention applying the multi-step etching process may be applied to the production of capacitors of this type.

As shown in FIG. 4A, the lower electrode 25 is first etched in the horizontal direction using the photoresist pattern 27a and the hard mask 26, and then the photoresist pattern 27a is removed.

FIG. 4A is a plan view showing the patterning of the lower electrode in the horizontal direction. The barrier metal 24 is exposed because the hard mask 26 remains and the lower electrode 25 is etched away. Part is shown.

First, the hard mask is selectively removed using the photosensitive film 27a. Subsequently, the lower electrode is patterned by performing an etching process until a portion of the barrier metal is exposed using the remaining hard mask.

In the first etching process (patterning in the horizontal direction) for the lower electrode patterning, the process conditions are adjusted to leave a predetermined thickness or more without removing all of the hard mask and barrier metal. This is to reuse the remaining barrier metal and hard mask in the subsequent second etching process (patterning in the vertical direction). Here, the width at which the lower electrode is removed to expose the barrier metal is about 100 to 20,000 kPa.

FIG. 4B is a cross-sectional view illustrating a cross section taken along the AA ′ line of FIG. 4A, and it can be seen that a hard mask 26 remains on the lower electrode 25, and FIG. 4C is BB ′ of FIG. 4A. As shown in FIG. 4C, the hard mask and the lower electrode are etched and removed, and only the first barrier metal 24 remains.

After the lower electrode is first patterned in the horizontal direction as described above, a new photoresist pattern 27b is formed to pattern the lower electrode in the vertical direction.

FIG. 5A is a plan view showing the formation of a new photoresist pattern 27b for patterning the lower electrode in a vertical direction, in which the first barrier metal 24 and the hard mask 26 are shown in FIG. It is a figure which shows the state in which the new photosensitive film pattern 27b was formed. Referring to FIG. 5A, the new photoresist pattern 27b exposes a predetermined region 26 of the hard mask and a predetermined region 24 of the barrier metal.

When the etching process of patterning the lower electrode in the vertical direction using the new photoresist pattern 27b is performed, a predetermined region of the exposed hard mask, a lower electrode formed under the predetermined region of the exposed hard mask, and exposed A certain region of the barrier metal is etched and removed. After the etching process is performed, the photoresist pattern is removed.                     

A portion of the exposed barrier metal 24 shown in FIG. 5A is etched twice through a horizontal etching process and a vertical etching process, and even the barrier metal is completely removed to expose the first interlayer dielectric layer 22. It can be seen with reference to Figure 5b.

In addition, the predetermined region 26 of the exposed hard mask shown in FIG. 5A is removed through the vertical etching process to remove the exposed hard mask and the lower electrode under the exposed hard mask to expose the barrier metal 24. It can be seen with reference to Figure 5b.

In addition, since the lower portion of the new photoresist pattern 27b is not etched in the vertical etching process, it can be seen that the hard mask and the barrier metal remain as they are.

After the lower electrode is patterned in two horizontal and vertical steps as described above, the remaining barrier metal and the hard mask are removed by wet etching to obtain the patterned lower electrode 25 as shown in FIG. 6. have.

In the present invention, since the etching process for the lower electrode patterning is divided into two stages in the horizontal direction and the vertical direction, it is possible to obtain a capacitor having a completely rectangular shape when viewed in plan, and thus, in the rounding as in the prior art. Since it is possible to prevent the reduction in area due to the high integration is an advantage.

Also, as shown in Fig. 6, since the capacitors formed in each cell can have a uniform shape, the uniformity of the device can be improved.

After patterning the lower electrode 25 as shown in FIG. 7, the ferroelectric layer 29, the upper electrode 30, and the like are sequentially formed on the lower electrode to complete the capacitor.

The process after the lower electrode patterning is a conventional capacitor manufacturing process and will be described in detail with reference to FIG. 7 as follows. First, after the lower electrode patterning, the second interlayer insulating film 28 is formed on the first interlayer insulating film 22 including the lower electrode, and subjected to an etch back process or chemical mechanical polishing to expose the surface of the lower electrode.

Next, after forming the ferroelectric film 29 on the second interlayer insulating film 28 and the lower electrode 25, the upper electrode 30 is formed on the ferroelectric film. Subsequently, a third interlayer insulating film 31 is formed on the ferroelectric film 29 including the upper electrode 30 to planarize the surface.

Next, a portion of the third interlayer insulating layer 31 is etched to form a contact hole for metal wiring exposing a portion of the upper electrode 30.

Subsequently, after the diffusion barrier 32 is formed on the entire surface including the above-described metal wiring contact hole, the diffusion barrier 32 remains only in the contact hole through etch back or chemical mechanical polishing.

The diffusion barrier 32 is for preventing the deterioration of the capacitor dielectric film made of ferroelectric in the manufacturing process of the semiconductor memory device, interlayer dielectric (Interlayer Dielectric) forming process, InterMetal Dielectric (IMD) forming process, protective film ( Passivation) Hydrogen or water generated in the forming process or the like is prevented from deteriorating the characteristics of the ferroelectric film.

Subsequently, after forming aluminum (Al) for metal wiring on the diffusion barrier film 32, aluminum is patterned to complete the metal wiring 33.                     

The technical idea of the present invention as described above may be applied to a method of manufacturing a capacitor by etching the lower electrode, the dielectric and the upper electrode at a time after stacking the lower electrode, the dielectric, and the upper electrode.

That is, when the process of etching the lower electrode, the dielectric, and the upper electrode at a time is performed by dividing the horizontal electrode and the vertical electrode at the same time, a rounded rectangular capacitor can be obtained.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, it will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

When the ferroelectric capacitor manufacturing method according to the present invention is applied, it is possible to prevent the reduction of the effective area of the capacitor to prevent the reduction of the polarization value, and the uniformity of the capacitor is improved. In addition, due to the increase in the effective area of the capacitor, it is possible to achieve high integration of the device.

Claims (9)

delete delete delete In the method of manufacturing a ferroelectric capacitor of a semiconductor device, Sequentially stacking a barrier metal, a conductive film for a lower electrode, a hard mask, and a patterned first photoresist film on a substrate on which a predetermined substructure including a storage node contact plug is completed; Patterning the conductive film for the lower electrode in a first direction by using the first photosensitive film and the hard mask; Forming a second photosensitive film for patterning the conductive film for the lower electrode in a second direction; Patterning the conductive film for the lower electrode in a second direction by using the second photosensitive film and the hard mask; And Sequentially forming a ferroelectric film and an upper electrode on the patterned lower electrode Ferroelectric capacitor manufacturing method comprising a. The method of claim 4, wherein An internal angle formed by the first direction and the second direction is 0 to 90 °, characterized in that the ferroelectric capacitor manufacturing method. The method of claim 4, wherein The patterning of the lower electrode conductive film in a first direction may include: Patterning the hard mask in a first direction by using the first photoresist film; And After removing the first photoresist layer, patterning the conductive layer for the lower electrode in a first direction so that a predetermined portion of the barrier metal is exposed using the patterned hard mask Ferroelectric capacitor manufacturing method characterized in that it further comprises. The method of claim 6, The patterning of the conductive film for the lower electrode in the second direction using the second photosensitive film and the hard mask may include: Removing the hard mask and the exposed barrier metal exposed by using the second photoresist film, and then removing the second photoresist film; And Wet etching the remaining hard mask and barrier metal Ferroelectric capacitor manufacturing method characterized in that it further comprises. The method of claim 4, wherein The barrier metal is any one of TiN, TiAlN, TiSiN, RuTiN or a method of manufacturing a ferroelectric capacitor, characterized in that used by laminating them. The method of claim 4, wherein The ferroelectric film is a ferroelectric capacitor manufacturing method, characterized in that any one of the BLT film, PZT film, SBT film, SBTN film.

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