KR20020094712A - Method and Apparatus for Driving Plasma Display Panel - Google Patents

Abstract

PURPOSE: A method and a device for driving a plasma display panel(PDP) are provided which can reduce a consumption power of a data drive IC(Integrated Circuit). CONSTITUTION: According to the device for driving a plasma display panel(PDP)(70), data(RGB) is inputted to a frame memory(61), and the first and the second reverse gamma compensation part(62,71) perform a reverse gamma compensation. An error spreading part(63) spreads an error component to surrounding cells. A sub field mapping part(67) maps data rearranged per bit to a sub field. An overcurrent generation pattern detection part(64) is connected between the error spreading part and the sub field mapping part. The device also comprises a sub field limit signal generation part(65) and a control part(66). And a data driving part(68) drives an address electrode line(X) of the PDP, and a waveform generation part(72) generates a driving waveform. And an unused sub field detection part(69) detects an unused sub field.

Description

Method and apparatus for driving plasma display panel {Method and Apparatus for Driving Plasma Display Panel}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving apparatus for a plasma display panel, and more particularly, to a method and apparatus for driving a plasma display panel to reduce power consumption of a data drive integrated circuit (IC).

Plasma Display Panel (hereinafter referred to as "PDP") displays an image including text or graphics by emitting phosphors by 147 nm ultraviolet rays generated during discharge of He + Xe or Ne + Xe inert mixed gas. . Such a PDP is not only thin and easy to enlarge, but also greatly improved in quality due to recent technology development. In particular, the three-electrode AC surface discharge type PDP has advantages of low voltage driving and long life because wall charges are accumulated on the surface during discharge and protect the electrodes from sputtering caused by the discharge.

Referring to FIG. 1, a discharge cell of a three-electrode AC surface discharge type PDP is formed on a scan / sustain electrode 12Y and a common sustain electrode 12Z formed on an upper substrate 11, and a lower substrate 16. An address electrode 17X is provided.

Each of the scan / sustain electrode 12Y and the common sustain electrode 12Z is formed of a transparent electrode, for example, Indium-Tin-Oxide (ITO).

Each of the scan / sustain electrode 12Y and the common sustain electrode 12Z is provided with a metal bus electrode 13 for reducing resistance.

An upper dielectric layer 14 and a passivation layer 15 are stacked on the upper substrate 11 on which the scan / sustain electrode 12Y and the common sustain electrode 12Z are formed. In the upper dielectric layer 14, wall charges generated during plasma discharge are accumulated. The passivation layer 15 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As the protective film 15, magnesium oxide (MgO) is usually used.

The lower dielectric layer 18 and the partition wall 19 are formed on the lower substrate 16 on which the address electrode 17X is formed, and the phosphor layer 20 is coated on the surfaces of the lower dielectric layer 18 and the partition wall 19.

The address electrode 17X is formed in the direction crossing the scan / sustain electrode 12Y and the common sustain electrode 13Z. The partition wall 19 is formed in parallel with the address electrode 17X to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor layer 20 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue.

An inert mixed gas such as He + Xe or Ne + Xe for discharging is injected into the discharge space of the discharge cells provided between the upper and lower substrates 11 and 16 and the partition wall 19.

The PDP is driven by dividing one frame into several subfields having different number of emission times in order to realize gray level of an image. Each subfield is further divided into a reset period for uniformly generating discharge, an address period for selecting a discharge cell, and a sustain period for implementing gray levels according to the number of discharges. For example, when the image is to be displayed with 256 gray levels, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields. In addition, each of the eight subfields is divided into an address period and a sustain period. Here, the reset period and the address period of each subfield are the same for each subfield, while the sustain period is 2 ⁿ (n = 0,1,2,3,4,5,6,7) in each subfield. Is increased. As described above, since the sustain period is changed in each subfield, gray levels of an image can be realized.

An integrated circuit (hereinafter, referred to as IC) for driving the electrodes 12Y, 12Z, and 17X of the PDP has a high voltage applied to the electrodes 12Y, 12Z, and 17X to cause a discharge. There is a disadvantage that the power consumption is large and expensive because it must be supplied. For example, each of the data drive ICs for driving the address electrodes 17X drives dozens of address electrode lines X and supplies data voltages of tens to hundreds of volts to each address electrode line X, thereby reducing power consumption. Big. The data drive IC 21 is mounted on the film 22 as shown in FIG. 2 so that the input terminal and the output terminal are bonded to the system board 23 and the PDP 20, that is, a chip on film (hereinafter referred to as "COF"). It is installed in the form of.

For the low cost of the data drive IC 21, it is necessary to drive the low voltage, increase the output port of the IC, and reduce the size (or die size) of the IC. In the case of the PDP whose resolution is VGA, the number of address electrode lines X on the PDP 20 is 640 x 3 (RGB), which is a total of 1920.

In this VGA resolution PDP, assuming that there are 96 output pins of each of the data drive ICs 21, 20 data drive ICs 21 are required. When four 96-pin data drive ICs 21 are mounted on one film 22, one COF has 384 output ports. Therefore, five data driving COFs are required for the above-described VGA resolution PDP. Do.

If the output pins of each of the data drive ICs 21 are increased to 192, the number of data drive ICs 21 required for the PDP of VGA resolution is reduced to ten. In this case, if five data drive ICs 21 can be mounted on the film 22, the COF required for the PDP of VGA resolution is reduced to two. Therefore, as the number of COFs decreases, the cost Cost of the PDP and the data drive IC 21 can be lowered.

In order to drive the low voltage of the data drive IC 21 and increase the number of output pins, the power consumption of the data drive IC 21 should be considered. The 96- / 64-pin data drive ICs 21 allow for 2.5W / 2.1W power consumption, respectively. In order to reduce the power consumption of the data driver IC 21, low voltage driving and low current must be realized, but it is difficult to reduce the power consumption of the data drive IC 21 due to the overcurrent flowing in the PDP. For example, when low voltage driving of 40V is possible, when 2A of current is consumed in a 40 ″ PDP, the power consumption of the PDP is VI, which is 80W. Assuming that the number of data drive ICs required for this PDP is 20, the power consumption of each of the data driver ICs 21 is 4 W, which exceeds the allowable power consumption of 2.5 W of the 96-pin data drive IC.

In addition, the power consumption of the data drive IC is proportional to the number of on / off switching of a large number of switch elements configured in the data drive IC and the length of the address electrode line X to which the data drive IC should be driven. For example, if a 40 ″ PDP is driven in a single scan without splitting the screen, the address electrode line X is driven in comparison to a dual scan that splits the screen up and down. Since the length of the circuit is twice, the power consumption of the data drive IC is increased. Similarly, when the number of on / off switching is large, for example, even when the number of subfields is large, the power consumption of the data drive IC 21 is inevitably increased.

Accordingly, an object of the present invention is to provide a method and apparatus for driving a PDP to reduce power consumption of a data drive IC.

1 is a perspective view showing a discharge cell structure of a conventional three-electrode AC surface discharge type plasma display panel.

FIG. 2 is a partially cut perspective view illustrating a chip on film bonded to the plasma display panel shown in FIG. 1.

3 is a flowchart illustrating a method of driving a plasma display panel according to an embodiment of the present invention in stages.

4 is a plan view illustrating a data pattern in which overcurrent occurs most frequently.

5 is an equivalent circuit diagram of a unit driver of a data drive IC and a plasma display panel.

6 is a block diagram illustrating a driving device of a plasma display panel according to an exemplary embodiment of the present invention.

FIG. 7 is a block diagram illustrating in detail the overcurrent generation pattern detector illustrated in FIG. 6.

FIG. 8 is a diagram illustrating an XOR operation and count for two vertically adjacent bit data in an n−1 th horizontal line and an n th horizontal line; FIG.

9 illustrates an XOR operation and count for two horizontally adjacent bit data.

<Description of Symbols for Main Parts of Drawings>

11: upper substrate 12Y: scan / sustain electrode

12Z: common sustain electrode 13: metal bus electrode

14 upper dielectric layer 15 protective film

16: lower substrate 17X: address electrode

18 lower dielectric layer 19 partition wall

20: fluorescent layer 61: frame memory

62,71: reverse gamma correction unit 63: error diffusion unit

64: overcurrent generation pattern detector 65: subfield limit signal generator

66: control unit 67: subfield mapping unit

68: data driver 69: unused subfield detector

70: PDP 72: waveform generator

73: line memory 74: XOR calculator

75,78: Counter 76: 1 Bit Delay

79: adder

In order to achieve the above objects, a method of driving a PDP according to the present invention includes detecting a data pattern with a high current consumption in an input image, and controlling the number of subfields in a data pattern with a high current consumption. do.

The controlling of the number of subfields may include reducing the number of subfields in a data pattern in which current is consumed.

The subfields removed from the data patterns in which the current consumption is high are characterized in that the luminance relative ratio is set small.

The driving apparatus of the PDP according to the present invention includes detection means for detecting a data pattern with high current consumption in the input image, and subfield control means for controlling the number of subfields in the data pattern with high current consumption.

The detecting means includes a 1 bit delay unit for delaying an input image of a horizontal line in units of 1 bit, a first calculating unit for performing an exclusive OR operation on bit data delayed 1 bit and undelayed bit data of the input image, and a first calculating unit. A first counter connected to count different logic value occurrences of two adjacent cells in a horizontal line to generate a first counting signal, a one-line delayer for delaying an input image by one horizontal line, and a one-line delayer A second arithmetic unit performing an exclusive OR operation on bit data corresponding to two vertically adjacent cells in the n-th horizontal line from the n-th horizontal line and the n-th horizontal line from the input line; A second counter connected to the operation unit and counting different logic value occurrences of two vertically adjacent cells to generate a second count signal; An adder for adding a signal, a control unit for comparing the added count value with a predetermined threshold value and determining the input image as a data pattern with high current consumption when the added count value is greater than or equal to the threshold value; The apparatus may further include a subfield mapping unit for reducing the number of subfields with respect to a data pattern that consumes large amounts of.

Other objects and features of the present invention in addition to the above object will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 3 to 9.

Referring to FIG. 3, in the driving method of the PDP according to the present invention, when data is input, the data is inverted in the horizontal direction (H) and the vertical direction (V), that is, the number of toggles is counted. (Steps S1 to S3) and the count value in the horizontal direction H and the count value in the vertical direction V are added. (Step S4) The added count value is compared with a predetermined threshold value, and the comparison result is determined. Accordingly, it is determined whether the number of subfields is adjusted (step S5).

Steps S1 to S5 are processes for determining a pattern in which a large current is consumed in the PDP. Among the data patterns displayed on the panel, the most current-consuming pattern is a pattern in which cells turned on and cells turned off between adjacent cells in a horizontal direction H and a vertical direction V as shown in FIG. 4. In detail, the unit driver of the data drive IC for driving one address electrode line X is a push-pull between the data D1 and D2 and the base voltage source (GND or low potential common voltage), respectively. It consists of two switch elements T1, T2 or T3, T4 connected in the form. If the cells turned on and off in the horizontal direction H or vertical direction V are repeated, the equivalent circuit at this time may appear as shown in FIG. When data D1 is supplied to one of the cells to be turned on and data D2 is not supplied to the cells to be turned off adjacent thereto, the data D1 of the cells to be turned on is the first switch element T1 and the cell Cp of the PDP. Is supplied to the cell Cp of the PDP along the current path through the circuit. Further, this data D1 leaks to the adjacent unit driver along the current path via the fourth switch element T4 and the ground voltage source GND. Therefore, when the cells turned on and the cells turned off in the horizontal direction H and the vertical direction V alternately, the leakage current increases in the data driver IC, so that the power consumption of the data drive IC increases.

In step S5, if the count value is determined to be a data pattern that consumes more current than the threshold value, the number of subfields included in one frame is reduced. (Step S6) When the number of subfields is reduced, the subfields are removed. Since the number of switching in the data drive IC is reduced, the switching loss of the data drive IC is reduced by that much. The subfield to be removed is preferably selected as a subfield of low luminance relative ratio. If the number of subfields is reduced, the range of expression of the gradation level to be expressed may be reduced, but when the subfields of low luminance relative ratio which are hardly detected by the user due to the viewer's visual perception are removed, This is because the decrease is small.

If it is determined in step S5 that the count value is smaller than the threshold value and the current consumption is determined to be a relatively small data pattern, the number of preset subfields is maintained (step S7).

6 shows an apparatus for driving a PDP according to an embodiment of the present invention.

Referring to FIG. 6, a frame memory 61 into which data RGB is input, first and second inverse gamma correction units 62 and 71 for performing inverse gamma correction, and error components are diffused into neighboring cells. An error diffusion section 63 for interfacing the data rearranged bit by bit to a subfield, and an error diffusion section 62 and a subfield mapping section 67 Generates an overcurrent generation pattern detector 64, a subfield limit signal generator 65 and a controller 66, a data driver 68 for driving the address electrode line X of the PDP 70, and a driving waveform. The waveform generator 72 is provided, and an unused subfield detector 69 for detecting an unused subfield is provided.

The frame memory 61 stores one frame of data RGB and supplies the stored data to the first and second inverse gamma correction units 62 and 71.

The first and second inverse gamma correction units 62 and 71 perform inverse gamma correction on the data supplied from the frame memory 61.

The error diffusion unit 63 serves to finely adjust the luminance value by diffusing the error component of the cell to the surrounding cells.

The overcurrent generation pattern detection unit 64 is connected between the error diffusion unit 63 and the subfield limit signal generation unit 65 to detect a data pattern in which an overcurrent can be generated. The detailed description of the overcurrent generation pattern detection unit 64 will be described later with reference to FIGS. 7 to 9.

The subfield limit signal generator 65 is connected between the overcurrent generation pattern detector 64 and the controller 66 to generate a control signal for reducing the number of subfields in response to a data pattern in which an overcurrent may be generated. .

The control unit 66 is connected between the subfield limit signal generation unit 65 and the subfield mapping unit 67 to control the subfield mapping unit 67 according to the control signal from the subfield limit signal generation unit 65. This reduces the subfields in the data pattern where overcurrent can occur.

In the subfield mapping unit 67, an error diffusion unit 63 is connected to an input terminal, and a control unit 66 is connected to a control terminal. The subfield mapping unit 67 maps the data supplied from the error diffusion unit 63 to a subfield allocated bit by bit according to the gradation level, and the subfield of the data pattern in which overcurrent is generated by the control of the control unit 66. Will reduce the number of. Here, in the data pattern in which the overcurrent is generated, subfields having a low luminance relative ratio are removed.

The data driver 68 includes a plurality of data drive ICs connected to the address electrode lines X of the PDP 70 so that bit-by-bit data supplied from the subfield mapping unit 67 may be addressed. Will be supplied to Since the number of subfields is reduced by the subfield mapping unit 67 in the data pattern in which the overcurrent is generated, the number of times of switching of the data driver 68 and the amount of current consumed are larger than the number of subfields is maintained in this data pattern. Becomes smaller.

The unused subfield detection unit 69 is connected between the subfield mapping unit 67 and the waveform generation unit 72 to generate a signal indicating a subfield removed from the data pattern in which an overcurrent is generated.

The waveform generator 72 is connected to the scan / sustain electrode line Y and the common sustain electrode line Z of the PDP 70 to generate the reset, scan voltage and sustain voltage required for the scan / sustain electrode line Y. In addition, a sustain voltage required for the common / sustain electrode line Z is generated.

Referring to FIG. 7, the overcurrent generation pattern detection unit 64 includes a line memory 73 for storing data for one horizontal line, a one bit delayer 76 for delaying one bit, and an input line 80. ) And an exclusive OR operation unit 74 (hereinafter referred to as an 'XOR operation unit') connected to the line memory 73, a first counter 75 connected between the XOR operation unit 74 and the output line 81, and An XOR gate 77 connected to the adder 79, the input line 80 and the 1-bit delay 76, and a second counter 78 connected between the XOR gate 77 and the adder 79 Equipped.

The line memory 73 stores the data from the input line 80 by one line, and supplies the stored data to the XOR calculator 74. Therefore, the line memory 73 delays data in units of one horizontal line.

The XOR operation unit 74 bit-by-bit for the n-th horizontal line data supplied from the line memory 73 (where n is a positive integer of 2 or more) and the n-th horizontal line data supplied from the input line 80. XOR operation will be performed. The XOR operation unit 74 generates a high logic '1' when the data of two vertically adjacent cells are different in the n-1th horizontal line and the nth horizontal line as shown in FIG. 8, and the data of the two vertically adjacent cells are the same. Produces a low logic '0'.

The first counter 75 counts the number of high logic '1's output from the XOR operator 74.

The one bit delay unit 76 stores the data from the input line 80 by one bit, and supplies the stored one bit to the XOR gate 77. This one bit delay 76 may be implemented as a flip-flop.

The XOR gate 77 performs an XOR operation on the n−1 (where n is a positive integer greater than or equal to 2) bits supplied from the 1-bit delay unit 76 and the nth bit supplied from the input line 80. Done. As shown in FIG. 9, the XOR gate 77 generates high logic '1' if the logic values of the n-th bit and the n-th bit that are horizontally adjacent are different, and if the data of two horizontally adjacent cells is the same, the low logic ' Occurs 0 '.

The second counter 78 counts the high logic '1' output from the XOR gate 77.

The adder 79 adds the count values of the first and second counters 75 and 78 to the control unit 81.

The controller 81 compares the preset threshold value with the count value added by the adder 79, and if the count value is greater than or equal to the threshold value, the controller 81 determines that the data is a data pattern in which excessive current may occur in the vertical direction and the horizontal direction. This reduces the number of subfields for that data pattern.

As described above, the method and apparatus for driving a PDP according to the present invention determine the degree of alternating the on data and the off data in the horizontal direction and the vertical direction so that a large amount of current may be consumed in the data drive IC. Reduce the number. As a result, the method and apparatus for driving a PDP according to the present invention can reduce the power consumption of the data drive IC by reducing the number of switching and leakage current in the data pattern in which overcurrent can occur.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (8)

Detecting a data pattern with a high current consumption in the input image; And controlling the number of subfields in the data pattern with high current consumption. The method of claim 1, The controlling of the number of subfields may include reducing the number of subfields in the data pattern with high current consumption. The method of claim 2, And the subfields removed from the data pattern with high current consumption have a small luminance relative ratio. The method of claim 1, The detecting of the data pattern may include performing an exclusive OR operation on bit data corresponding to two adjacent cells in a horizontal line; Generating a first coefficient signal by counting different occurrences of logic values of two adjacent cells in the horizontal line generated as a result of the exclusive OR operation; performing an exclusive OR operation on bit data corresponding to two vertically adjacent cells in the n-th horizontal line and the n-th horizontal line; Generating a second coefficient signal by counting the number of different logic value occurrences of the two vertically adjacent cells generated as a result of the exclusive OR operation; Adding the first and second count signals; Comparing the added count value with a predetermined threshold value; And determining the input image as a data pattern with a high consumption of current when the added count value is greater than or equal to the threshold value. Detecting means for detecting a data pattern with high current consumption in the input image; And subfield control means for controlling the number of subfields in the data pattern with high current consumption. The method of claim 5, And the subfield control means reduces the number of subfields in the data pattern with high current consumption. The method of claim 6, And the subfield control means removes the subfield in which the luminance relative ratio is set small in the data pattern with high current consumption. The method of claim 5, The detecting means includes a 1 bit delay unit for delaying the input image of the horizontal line by 1 bit unit; A first operator for performing an exclusive OR operation on the one bit delayed bit data and the undelayed bit data of the input image; A first counter connected to the first calculator and counting different occurrences of logic values of two adjacent cells in the horizontal line to generate a first counting signal; A one line delay unit for delaying the input image by one horizontal line unit; An exclusive-OR operation on bit data corresponding to two vertically adjacent cells in the n-th horizontal line delayed by the one-line delay unit and n-th horizontal line from the input line and the n-th horizontal line from the input line 2 arithmetic unit, A second counter connected to the second calculator and counting different occurrences of logic values of two vertically adjacent cells to generate a second count signal; An adder for adding the first and second count signals; A controller for comparing the added count value with a predetermined threshold value and determining the input image as a data pattern with high consumption of current when the added count value is greater than or equal to the threshold value; And a subfield mapping unit for reducing the number of subfields for the data pattern with high current consumption under the control of the controller.