KR20040017557A - Apparatus and method for driving plasma display panel - Google Patents

Abstract

PURPOSE: An apparatus and a method for driving a plasma display panel are provided to reduce the power consumption of a data drive IC by reducing the switching number and the leakage current in a data pattern. CONSTITUTION: A data pattern having the large amount of consumed current is detected from an inputted picture. Data pulses are applied to adjacent cells during an address period, respectively. The detection process for detecting the data pattern includes a process for performing an exclusive logical OR operation for bit data corresponding to two adjacent cells on a horizontal line, a process for generating the first coefficient signal, a process for performing the exclusive logical OR operation for bit data corresponding to two adjacent cells on a vertical line, a process for generating the second coefficient signal, a process for adding the first and the second coefficient signals to each other, a process for comparing the added result to a predetermined threshold value, and a process for determining the inputted picture as the data pattern.

Description

Apparatus And Method For Driving Plasma Display Panel

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a method and apparatus for driving a plasma display panel to reduce power consumption when data pulses are applied.

Recently, a plasma display panel (hereinafter referred to as "PDP"), which is easy to manufacture a large panel, has attracted attention as a flat panel display device. As a PDP, a three-electrode AC surface discharge type PDP having three electrodes and driven by an alternating voltage is typical.

Referring to FIG. 1, a discharge cell of a three-electrode AC surface discharge type PDP includes a scan electrode 12Y and a sustain electrode 12Z formed on the upper substrate 10, and an address electrode formed on the lower substrate 18. 20X). The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 having the scan electrode 12Y and the sustain electrode 12Z side by side. Wall charges generated during plasma discharge are accumulated in the upper dielectric layer 14. The protective layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge, and increases emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used. The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode 20X is formed, and the phosphor 26 is coated on the surfaces of the lower dielectric layer 22 and the partition wall 24. The address electrode 20X is formed in the direction crossing the scan electrode 12Y and the sustain electrode 12Z. The partition wall 24 is formed in parallel with the address electrode 20X to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. Inert gas for gas discharge is injected into the discharge space provided between the upper and lower plates and the partition wall.

These discharge cells are arranged in a matrix form as shown in FIG. In FIG. 2, the discharge cells 1 are provided at the intersections of the scan electrode lines Y1 to Ym, the sustain electrode lines Z1 to Zm, and the address electrode lines X1 to Xn. The scan electrode lines Y1 to Ym are sequentially driven, and the sustain electrode lines Z1 to Zm are commonly driven. The address electrode lines X1 to Xn are driven by being divided into odd-numbered lines and even-numbered lines.

The three-electrode AC surface discharge type PDP is driven by being divided into a plurality of subfields, and gray scale display is performed by emitting light a number of times proportional to the weight of video data in each subfield period. For example, when an image is displayed in 256 gray scales using 8-bit video data, one frame display period (for example, 1/60 second = about 16.7 msec) in each discharge cell 1 is shown in FIG. As shown, the data is divided into eight subfields SF1 to SF8. Each subfield SF1 to SF8 is further divided into a reset period, an address period, and a sustain period, and 1: 2: 4: 8:... The weight is given at the ratio of 128. Here, the reset period is a period for initializing the discharge cells, the address period is a period for causing selective address discharge according to the logic value of the video data, and the sustain period is for discharge to be maintained in the discharge cells in which the address discharge has occurred. It is a period. The reset period and the address period are equally allocated to each subfield period.

4 is a plan view illustrating a data pattern in which overcurrent occurs most frequently, and FIG. 5 is a waveform diagram illustrating a method of driving a PDP according to the pattern shown in FIG. 4, and FIG. 6 is an equivalent of a unit driver of a data driver IC and a PDP. It is a circuit diagram.

Referring to FIGS. 4 to 6, first, the most current-consuming pattern among the data patterns displayed on the panel is a cell turned on and a cell turned off between adjacent cells in a horizontal direction (H) and a vertical direction (V) as shown in FIG. 4. This is an alternating pattern. The data driving waveforms for the alternating patterns are alternately applied to two adjacent cells as shown in FIG. 5. At this time, the data pulse DP applied to two adjacent cells has a falling section and a rising section. These sections may occur due to the characteristics of the data driver IC, and each data pulse DP is switched by a latch enable (LE) signal. In detail, the unit driver of the data drive IC for driving one address electrode line X is a push-pull between the data D1 and D2 and the base voltage source (GND or low potential common voltage), respectively. It consists of two switch elements T1, T2 or T3, T4 connected in the form. When the cells turned on and off in the horizontal direction H or vertical direction V are repeated, the equivalent circuit at this time may appear as shown in FIG. 6. When data D1 is supplied to one of the cells to be turned on and data D2 is not supplied to the cells to be turned off adjacent thereto, the data D1 of the cells to be turned on is the first switch element T1 and the cell Cp of the PDP. Is supplied to the cell Cp of the PDP along the current path through the circuit. Further, this data D1 leaks to the adjacent unit driver along the current path via the fourth switch element T4 and the ground voltage source GND. Therefore, when the cells turned on and the cells turned off in the horizontal direction H and the vertical direction V alternately, the leakage current increases in the data driver IC, so that the power consumption of the data drive IC increases.

Accordingly, it is an object of the present invention to provide a method and apparatus for driving a PDP that reduces power consumption of a data driver IC.

1 is a perspective view showing a discharge cell structure of a conventional three-electrode AC surface discharge type plasma display panel.

FIG. 2 is an overall electrode layout of the plasma display panel including the discharge cells shown in FIG. 1.

3 is a frame configuration diagram for describing a conventional subfield driving method.

4 is a plan view illustrating a data pattern in which overcurrent occurs most frequently.

FIG. 5 is a waveform diagram illustrating a method of driving a PDP according to the pattern shown in FIG. 4.

6 is an equivalent circuit diagram of an address driver and a panel.

7 is a waveform diagram illustrating a method of driving a PDP according to an embodiment of the present invention.

8 is a diagram illustrating a driving device of a PDP according to an embodiment of the present invention.

9 is a diagram illustrating in detail an overcurrent generation pattern detector illustrated in FIG. 8.

FIG. 10 is a diagram illustrating an XOR operation and a count of two vertically adjacent bit data in an n−1 th horizontal line and an n th horizontal line.

11 is a diagram illustrating an XOR operation and a count on two horizontally adjacent bit data.

12 is a graph showing the effect on the power consumption when applying the driving device of the PDP according to the present invention.

<Description of Symbols for Main Parts of Drawings>

81: frame memory 82: inverse gamma correction unit

83: gain adjusting unit 84: error diffusion unit

85: subfield mapping unit 86: data alignment unit

87: address driver 88: scan driver

89: sustain drive unit 90: PDP

91: waveform generation unit 92: overcurrent generation pattern detection unit

93: timing controller 103: line memory

104: XOR calculator 105, 108: counter

106: Bit Delay 107: XOR Gate

109: adder 112: overcurrent pattern determination unit

In order to achieve the above object, a method of driving a plasma display panel of the present invention includes detecting a data pattern with a high current consumption in an input image, and a cell adjacent to a data pulse in an address period in the data pattern with a high current consumption. And controlling to be applied independently.

The detecting of the data pattern may include performing an exclusive OR operation on bit data corresponding to two adjacent cells in a horizontal line, and two adjacent cells in the horizontal line generated as a result of the exclusive OR operation. Generating a first counting signal by counting the number of different logic value occurrences of the signal, and bit data corresponding to two vertically adjacent cells in the n-th horizontal line and the n-th horizontal line And an exclusive OR operation on the plurality of data fields, generating a second coefficient signal by counting different occurrences of logic values of two vertically adjacent cells generated as a result of the exclusive OR operation, and generating the second coefficient signal. Adding two counting signals, comparing the added count value with a predetermined threshold value, and wherein the added count value is the threshold value; And determining the input image as a data pattern that consumes the current when the value is greater than or equal to the value.

The controlling of the data pulse to be applied to adjacent cells independently may include inputting information determined as a data pattern with a high consumption of current, and allowing the input determination information to be input to the adjacent cells. Generating a control signal for independently applying a data pulse to each address electrode of the apparatus.

The control signal of the present invention is characterized in that the signal to the data pulse applied to the current address electrode is turned off.

The driving apparatus of the plasma display panel according to the present invention includes an overcurrent generation pattern detector for detecting a data pattern with a high current consumption in an input image, and a timing for controlling application of a data pulse to an address driver in the data pattern with a high current consumption. It is characterized by including a controller.

The overcurrent generation pattern detector according to the present invention includes a 1-bit delay unit for delaying an input image of a horizontal line by 1 bit unit, and an exclusive OR operation for the 1-bit delayed bit data and the undelayed bit data of the input image. A first counter connected to the first calculator and a first counter connected to the first calculator to generate a first count signal by counting different occurrences of logic values of two adjacent cells in the horizontal line, and delaying the input image by one horizontal line And a bit line corresponding to two vertically adjacent cells in the n-th horizontal line and n-th horizontal line from the input line, which are delayed by the 1-line delay unit. A second operation unit for performing an exclusive logical sum operation on the second operation unit, and different logical value generations of two vertically adjacent cells connected to the second operation unit. A second counter that counts the number of times and generates a second count signal, an adder that adds the first and second count signals, and compares the added count value with a predetermined threshold value and adds the count value And an overcurrent pattern determiner configured to determine the input image as a data pattern that consumes a large amount of current and supply information to the timing controller.

Other objects and features of the present invention in addition to the above object will be apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 7 to 12.

FIG. 7 is a waveform diagram illustrating a method of driving a PDP according to an exemplary embodiment of the present invention. In particular, FIG.

Referring to FIG. 7, a data pulse DP is supplied to an address electrode line X included in two cells adjacent to an address period of a driving waveform of the present invention, and a scan pulse SP is supplied to a scan electrode line Y. Is supplied. The data pulse DP is a main data pulse MDP synchronized with the scan pulse SP, and a main data pulse between the main data pulse MDP and the main data pulse MDP applied to the next address electrode line X. It is composed of an auxiliary data pulse (ADP) having a falling ramp slope in association with (MDP). The main data pulse MDP is supplied simultaneously with the application of the latch enable (LE) signal, and the auxiliary data pulse ADP is supplied simultaneously with the application of the blank signal. At this time, the latch enable (LE) signal serves to output data latched in the data driver IC, and the blank signal serves to output all output signals from the data driver IC as a low signal.

When the driving thereof is described in detail, when the main data pulse MDP in one cell is applied and the scan pulse SP and the address discharge are completed, the auxiliary data pulse ADP is applied by the blank signal. Thereafter, the data pulse DP is supplied to the next address electrode line X by the latch enable signal LE. In addition, the scan pulse SP applied to be synchronized with the main data pulse MDP is sequentially applied in synchronization with the rising edge of the clock signal CLK from a timing controller (not shown). The waveform width can be adjusted. The scan pulse SP stops applying to the scan electrode line Y in synchronization with the rising edge of the strobe signal STB from the timing controller and maintains the scan reference potential.

As a result, the rising intervals of the auxiliary data pulse ADP of one cell and the main data pulse MDP of another cell do not overlap in two adjacent cells. That is, the first data pulse DP1 supplied to one on-cell and the second data pulse DP2 supplied to the next on-cell of the cell adjacent thereto are independently driven to alternate between the cells Cp of the PDP. The leakage current caused by the data pattern is reduced. As a result, the power consumption of the data drive IC can be reduced.

8 shows an apparatus for driving a PDP according to an embodiment of the present invention.

Referring to FIG. 8, a frame memory 81 into which data RGB is input, first and second inverse gamma correction units 82A and 82B for performing inverse gamma correction, and inverse gamma corrected video data may be used. A gain adjusting unit 83 for amplifying by an effective gain, an error diffusion unit 84 for diffusing an error component into neighboring cells, and a subfield mapping unit 85 for mapping the rearranged data bit by bit to a subfield And a data alignment unit 86 for converting the video data input from the subfield mapping unit 85 and the address electrode line X of the PDP 90 in accordance with the resolution format of the PDP 90. An address driver 87 for driving, a waveform generator 91 for generating driving waveforms, a scan driver 88 for driving scan electrode lines Y and sustain electrode lines Z of the PDP 90, and Sustain driver 89 and timing controller 93 for controlling each driver 87, 88, 89. ), And an overcurrent generation pattern detection unit 92 connected between the frame memory 81 and the timing controller 93.

The frame memory 81 stores one frame of data RGB and supplies the stored data to the first and second inverse gamma correction units 82A and 82B.

The first and second inverse gamma correction units 82A and 82B perform inverse gamma correction on the data supplied from the frame memory 81.

The gain adjusting unit 83 amplifies the video data corrected by the first inverse gamma correction unit 82A by the effective gain. The error diffusion unit 84 serves to finely adjust the luminance value by diffusing the error component of the cell to the surrounding cells.

The subfield mapping unit 85 reassigns the video data corrected by the error diffusion unit 84 for each subfield. The data alignment unit 86 converts the video data input from the subfield mapping unit 85 in accordance with the resolution format of the PDP 90 and supplies it to the address driver 87.

The overcurrent generation pattern detector 92 is connected between the frame memory 81 and the timing controller 93 to detect a data pattern in which an overcurrent can be generated, and supplies detection information to the timing controller 93. A detailed description of the overcurrent generation pattern detection unit 92 will be described later with reference to FIGS. 9 to 11.

The waveform generator 91 is connected to the scan electrode line Y and the sustain electrode line Z of the PDP 90 to generate the reset, scan voltage, and sustain voltage required for the scan electrode line Y. The sustain voltage required for the line Z is generated.

Referring to FIG. 9, the overcurrent generation pattern detector 92 includes a line memory 103 for storing data for one horizontal line, a one bit delayer 106 for delaying one bit, and an input line 110. ) And an exclusive OR operation unit 104 (hereinafter referred to as an "XOR operation unit") connected to the line memory 103, a first counter 105 connected between the XOR operation unit 104 and the output line 111, and An XOR gate 107 connected to the adder 109, the input line 110 and the 1-bit delay 106, and a second counter 108 connected between the XOR gate 107 and the adder 109; And an overcurrent pattern determination unit 112 connected to the adder 109 for supplying control information to the timing controller 93.

The line memory 103 stores the data from the input line 110 by one line, and supplies the stored data to the XOR operator 104. Therefore, the line memory 103 delays the data in units of one horizontal line.

The XOR operator 104 performs bit-by-bit on the n-th horizontal line data supplied from the line memory 103 (where n is a positive integer of 2 or more) and the n-th horizontal line data supplied from the input line 11. XOR operation will be performed. The XOR operator 104 generates a high logic '1' when the data of two vertically adjacent cells are different in the n-1th horizontal line and the nth horizontal line as shown in FIG. 10, and the data of the two vertically adjacent cells are the same. Produces a low logic '0'.

The first counter 105 counts the number of high logic '1's output from the XOR operator 104.

The one bit delay unit 106 stores the data from the input line 11 by one bit and supplies the stored one bit to the XOR gate 107. This one bit delay 106 may be implemented as a flip-flop.

The XOR gate 107 performs an XOR operation on the n-th bit supplied from the 1-bit delay 106 (where n is a positive integer of 2 or more) and the n-th bit supplied from the input line 11. Done. The XOR gate 107 generates a high logic '1' if the logic values of the n-th bit and the n-th bit that are horizontally adjacent as shown in FIG. 11 are different, and if the data of two horizontally adjacent cells is the same, the low logic ' Occurs 0 '.

The second counter 108 counts the high logic '1' output from the XOR gate 107.

The adder 109 adds count values of the first and second counters 105 and 108 to supply the overcurrent pattern determination unit 112.

The overcurrent pattern determination unit 112 compares a preset threshold value with a count value added by the adder 109 and if the count value is greater than or equal to the threshold value, the data pattern in which the overcurrent may occur in the vertical direction and the horizontal direction. In response to the determination, the control signal of the address driver 87 is output to the timing controller 93.

When the overcurrent generated data pattern is detected when the PDP is driven using the driving device as described above, the address driver is controlled as shown in FIG. 7, and otherwise, the address driver is controlled to output the data pulse as in the prior art. By doing so, power consumption can be reduced. As shown in FIG. 12, the power consumption is reduced in the super pixel and sub pixel areas in which the overcurrent pattern is generated.

As described above, the method and apparatus for driving a plasma display panel according to the present invention determine an alternating degree of on data and off data in a horizontal direction and a vertical direction to address an data pattern in which a large current may be consumed in a data drive IC. In this period, data pulses are independently applied. As a result, the method and apparatus for driving a PDP according to the present invention can reduce the power consumption of the data drive IC by reducing the number of switching and leakage current in the data pattern in which overcurrent can occur.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (6)

Detecting a data pattern with a high current consumption in the input image; And controlling data pulses to be applied independently to adjacent cells in an address period in a data pattern in which the current consumption is high. The method of claim 1, The detecting of the data pattern may include performing an exclusive OR operation on bit data corresponding to two adjacent cells in a horizontal line; Generating a first coefficient signal by counting different occurrences of logic values of two adjacent cells in the horizontal line generated as a result of the exclusive OR operation; performing an exclusive OR operation on bit data corresponding to two vertically adjacent cells in the n-th horizontal line and the n-th horizontal line; Generating a second coefficient signal by counting the number of different logic value occurrences of the two vertically adjacent cells generated as a result of the exclusive OR operation; Adding the first and second count signals; Comparing the added count value with a predetermined threshold value; And determining the input image as a data pattern with a high consumption of current when the added count value is greater than or equal to the threshold value. The method of claim 1, The step of controlling the data pulse to be applied independently to the adjacent cells, Inputting information determined as a data pattern in which the current consumption is high; And generating a control signal by causing the input determination information to independently apply a data pulse to each address electrode of the adjacent cell. The method of claim 3, wherein And the control signal is a signal for turning off a data pulse applied to a current address electrode. An overcurrent generation pattern detector for detecting a data pattern with a high current consumption in the input image; And a timing controller for controlling the application of data pulses to the address driver in the data pattern with high current consumption. The method of claim 5, wherein The overcurrent generation pattern detection unit includes a 1-bit delay unit for delaying the input image of the horizontal line by 1 bit unit; A first operator for performing an exclusive OR operation on the one bit delayed bit data and the undelayed bit data of the input image; A first counter connected to the first calculator and counting different occurrences of logic values of two adjacent cells in the horizontal line to generate a first counting signal; A one line delay unit for delaying the input image by one horizontal line unit; An exclusive-OR operation on bit data corresponding to two vertically adjacent cells in the n-th horizontal line delayed by the one-line delay unit and n-th horizontal line from the input line and the n-th horizontal line from the input line 2 arithmetic unit, A second counter connected to the second calculator and counting different occurrences of logic values of two vertically adjacent cells to generate a second count signal; An adder for adding the first and second count signals; Compare the added count value with a predetermined threshold value, and if the added count value is greater than or equal to the threshold value, determine the overcurrent pattern for supplying information to the timing controller by judging the input image as a data pattern with high current consumption. And a driving unit for the plasma display panel.