KR20020086870A - Solution processed devices - Google Patents

Abstract

Depositing a first material from a solution using a first solvent to form a first layer of the transistor, and then depositing the first material on the first material while still allowing the first material to be soluble in the first solvent, Forming a second layer of the transistor by depositing a second material from a solution in a second solvent in which the first material is substantially insoluble.

Description

[0001] SOLUTION PROCESSED DEVICES [0002]

In recent years, semiconducting conjugated polymer thin film transistors (TFTs) have been used in the field of inexpensive logic circuits (Cedrari et al., Published in APL 73, 108 (1998)) integrated on plastic substrates, high resolution active- (Published in Science 280, 1741 (1998) and Eidobarapur et al., Appl. Phys. Lett. 73, 142 (1998)), I was attracted to them. In the test, device configurations with polymer semiconductor and inorganic metal electrodes and gate dielectric layers have been demonstrated to be high performance TFTs. Charge carrier mobilities of up to 0.1 cm ² / Vs and ON-OFF current ratios of 10 ⁶ -10 ⁸ were achieved, because the performance of amorphous silicon TFTs (H. Schillinghaus et al., Advances in Solid State Physics 39, 101 Announcement).

Thin device-quality films of conjugated polymer semiconductors can be formed by coating a polymer solution of an organic solvent on a substrate. Thus, this technique is ideally suited for solution processing over a range of inexpensive and wide areas that are compatible with flexible plastic substrates. In order to make full use of the advantages of processing in terms of potential cost and ease, it is desirable that all components of the device including semiconductor layers, dielectric layers, conductive electrodes and interconnects be deposited by solution.

In order to manufacture all-polymer TFT devices and circuits, the following main problems must be solved:

Completeness of the multilayer structure: During solution deposition of subsequent semiconductor, insulating and / or conductive layers, the underlying layers must not be dissolved or swelled by the solvent used for the deposition of subsequent layers. This expansion occurs when the solvent is mixed in the underlying layer, which generally degrades the properties of the layer.

High resolution patterning for the electrodes: The conductive layers need to be patterned to form well defined interconnects and TFT channels with a channel length of L ≤ 10 mu m.

To fabricate the TFT circuits, vertical interconnect regions (via holes) need to be formed to electrically connect the electrodes of the different layers of the device.

In WO 99/10939 A2, a method of manufacturing all polymer TFTs is disclosed, which method relies on the conversion of the solution-treated layers of the device into an insoluble form before depositing subsequent layers of the device. This overcomes the problems of dissolution and expansion of the underlying layers. However, this limits the selectivity of semiconductor materials that can be used to be low, and in some respects to an undesirable class of precursor polymers. In addition, cross-linking of the gate insulating layer of the dielectric makes it difficult to manufacture via holes through the dielectric layers, and therefore techniques such as metal punching have to be used (WO 99/10939 Al).

The present invention relates to solution processing devices and methods of forming such devices.

The invention will be described by way of example with reference to the accompanying drawings.

Figure 1 shows different device configurations of solution-processed all-polymer TFTs.

2 shows transfer characteristics of the polymer TFTs according to FIG. 1C with a F8T2 active layer, a PVP gate insulating layer, and a PEDOT / PSS gate electrode.

3 shows transfer characteristics of the polymer TFTs according to FIG. 1C with a F8T2 active layer, a PVP gate insulating layer and a PEDOT / PSS gate electrode deposited with the sample held at room temperature (a) and at about 50 DEG C (b) .

Figure 4 shows the output (a) and transfer characteristics (b) of a F8T2 full-polymer TFT comprising an F8 diffusion barrier layer and a PVP surface strained layer as in Figure 1 (a).

Figure 5 shows the transfer characteristics of F8T2 full-polymer TFTs as in Figure 1 (a) with TFB (a) and polystyrene (b) diffusion barrier and PVP surface strained layers.

Figure 6 shows an optical micrograph of a full-polymer TFT according to Figure 1 (a) with F8T2 active layer and source-drain electrodes printed directly on a bare glass substrate.

Figure 7 illustrates the formation of TFTs with small overlap lengths that pass through the patterning of the substrate surface to a small channel length and hydrophobic and hydrophilic regions.

8 is an optical micrograph of a transistor channel region with L = 20 μm (a) and L = 5 μm (b) after IJP deposition of PEDOT / PSS source / drain electrodes in the vicinity of a hydrophilic polyimide bank Respectively.

Figure 9 shows an optical microscope photograph taken during the deposition of ink droplets in the vicinity of the polyimide bank.

Figures 10 and 11 show the output and transfer characteristics of transistors formed as in Figure 7 (c) with channel lengths L = 20 [mu] m and L = 7 [mu] m, respectively.

Figure 12 shows a schematic diagram (a), a Dektak profile and photomicrographs (b) of the process of forming via holes by continuous deposition of methanol droplets on a PVP gate dielectric layer with a thickness of 1.3 탆, (C) the diameter of the droplet and the dependency of the inner diameter and the outer diameter of the via hole with respect to the thicknesses of the PVP layer.

13 shows the current-voltage characteristics through the via hole having the PEDOT electrode and the upper electrode of the base portion.

14 illustrates different processes for forming via holes.

Figure 15 is a schematic diagram of the logic inverters (depletion-load (a), enhancement-load (b) and resistance-load (c) (d). < / RTI >

Fig. 16 shows the characteristics of the improved-load inverter circuits as in Fig. 1 (a) formed with printed full-polymer TFTs having two registers with different W / L size ratios.

17 shows an alternative base-gate device configuration.

Figure 18 shows a simplified diagram of an active matrix pixel, wherein the display or memory component is controlled by voltage (a) or current (b).

Figure 19 shows a possible configuration of pixels of the active matrix.

Figure 20 shows the polarized optical absorption of an aligned F8T2 TFT.

Figure 21 shows an overlap region between the polymer TFTs having patterned active layer islands formed by printing (a) semiconductor and dielectric layers and (b) the conductor interconnects separated by a printed insulating island. do.

Figure 22 shows the metrics of transistor devices connected by a network of IJP interconnects to form user defined electronic circuits.

According to aspects of the present invention, device (s) and method (s) presented in the dependent claims of the appended claims are provided. Preferred features are described in the dependent claims.

According to a first aspect of the present invention there is provided a method of manufacturing a transistor, comprising: depositing a first material from a solution using a first solvent to form a first layer of a transistor; And depositing a second material from a solution in a second solvent in which the first material is substantially insoluble on the first material while still allowing the first material to be soluble in the first solvent, And forming a first layer and a second layer.

Advantageously, the method further comprises the step of removing the third material from the solution in the third solvent, wherein the second material is substantially not dissolved on the second material, while allowing the second material to still be soluble in the second solvent Lt; RTI ID = 0.0 > a < / RTI > third layer of the transistor.

Suitably, at least one layer of the transistor is formed by ink jet printing (IJP). This layer can be, for example, a layer providing an electrode of a transistor, such as a gate, source or drain electrode.

Preferably, the method further comprises: forming a functional layer of the transistor; forming an isolation layer on the functional layer; And forming a gate of the transistor on the insulating layer. The isolation layer may provide separate or identical layers of diffusion barriers and / or surface strained layers.

According to a second aspect of the present invention, there are provided methods of confining solution deposition of a material to defined areas on a substrate. The method includes patterning the surface of the lower substrate into regions having different surface free energies. The substrate has surface areas that are hydrophobic, and the remaining surface areas that are hydrophilic. Such solution deposition includes ink jet printing, and restriction of the ink to hydrophobic or hydrophilic surface areas.

Preferably, the pattern on the substrate comprises source and drain electrodes of a transistor having a small channel length, preferably L < 20 占 퐉, gate electrodes having a well defined overlap with the source and drain electrodes, .

According to a third aspect of the present invention, there is provided a method of forming via holes in interconnects in different layers and defining electrical connections between the electrodes. The method comprises dissolving or doping the layers by local deposition of solvents or dopant solutions, preferably by ink jet printing.

According to another aspect of the invention, there is provided an integrated circuit manufacturing method of transistor devices in which some of the transistor devices and / or other circuit elements are formed by inkjet printing.

According to another aspect of the present invention, a method of manufacturing an array of electronic devices having at least one exposed electrode is provided. The method includes interconnection of electronic devices by inkjet printing of a conductive material in such a way that an electronic circuit having a user-defined function is obtained.

Preferably, one of the first and second solvents is a polar solvent, and the other of the first and second solvents is a nonpolar solvent.

Preferably, one of the first or second materials is a semiconductor material, and the other of the first or second materials is a dielectric material.

Preferably, the second material is a dielectric material, one of the first and third materials is a semiconductor material, and the other of the first or third materials is a conductive material.

One of the first and second layers may be a non-polar polymer layer soluble in the non-polar solvent. The other of the first and second layers may be a polar polymer layer soluble in a polar solvent. The interaction parameter D for the nonpolar polymer and the polar solvent is suitably greater than 5, preferably greater than 10, and most preferably greater than 15. The interaction parameter (D) for the polar polymer and the nonpolar solvent is suitably greater than 5, preferably greater than 10, and most preferably greater than 15.

Suitably, one of the second and third solvents is a polar solvent, and the other of the second and third solvents is a non-polar solvent.

Suitably, the second solvent is a moderately polar solvent comprising a polar and a non-polar group, and one of the first and third solvents is a highly polar solvent containing only polar groups .

The second polymer layer may be a generally polar polymer layer that is soluble in a polar solvent. In this case, one of the first or third polymer layers is a normal non-polar polymer layer and the other one of the first or third polymer layers is a polar polymer layer. The interaction parameter (D) for the nonpolar polymer and the solvent of the polar polarity is greater than 5, preferably greater than 10, and most preferably greater than 15. The interaction parameter (D) for the polar polymer and the solvent of the polar polarity is greater than 5, preferably greater than 10, and most preferably greater than 15. Usually polar solvents can be, for example, alcohols or acetates.

The first layer is soluble in a non-polar solvent, and the second layer is soluble in a solvent of a normal polarity including hydrophilic and hydrophobic groups. The third layer is soluble in a polar solvent. Alternatively, the third layer may be soluble in a non-polar solvent.

The second layer may be an active layer of a transistor.

Suitably, one of the first and second layers is a source and / or drain electrode layer of the transistor, and the other of the first and second layers is a semiconductor layer of the transistor.

Suitably, one of the first and second layers is a semiconductor layer of a transistor, and the other of the first and second layers is an insulating layer of a transistor.

The semiconductor layer may be a conjugated polymer, preferably a conjugated block copolymer.

Wherein the semiconductor layer has a block copolymer having an electron affinity of at least 3.0 eV or 3.5 eV and wherein the block copolymer has a first block of conjugated monomers each connected by at least two covalent bonds and a second block of monomer units Block.

Wherein the semiconductor layer has a block copolymer having an ionization potential in the range of 5.5 eV to 4.9 eV, the block copolymer having a first block of conjugated monomers each connected by at least two covalent bonds and a second block of conjugated monomers Block.

Wherein the first block of the monomer units comprises one or more groups comprising a fluorine derivative, a phenylene derivative and an indenofluorene derivative, and the second group of monomer units comprises a thiophene derivative, Triarylamine derivatives, and benzothioadiazole derivatives.

The semiconductor polymer may be F8T2 or TFB.

Preferably, the semiconductor layer comprises a liquid crystal conjugated polymer. The method includes heating the liquid crystal polymer to its liquid crystal state. The method preferably comprises the step of uniaxially aligning the liquid crystal polymer. The step of aligning the liquid crystal polymer comprises depositing the liquid crystal polymer on a layer having an ordered molecular structure. The step of aligning the molecular structure of the layer is performed by mechanically rubbing the layer. The method preferably comprises aligning the molecular structure of the layer by optically treating the layer.

The semiconductor layer suitably has a bandgap of 2.3 eV or more, preferably 2.5 eV or more and is optically transparent. The semiconductor layer suitably has an ionization potential of 4.9 eV or 5.1 eV or higher. The semiconductor layer suitably has an electron affinity of 3.0 eV or more, or 3.5 eV or more.

Wherein one of the first and second layers is an insulator layer of the transistor and the other of the first and second layers is a gate electrode layer of the transistor.

One of the first and third layers being an insulator layer of the transistor and the second layer of the transistor being another of the first and third layers is an isolated layer of a transistor. This isolation layer may be a diffusion barrier layer. The diffusion barrier layer may comprise a non-polar polymer. The diffusion barrier layer may comprise a polyfluorine derivative. The polyfluorine derivative may be F8, F8T2 or TFB. The isolation layer may be a surface strained layer, preferably as described above.

The method includes modifying the surface of the first layer prior to depositing the second layer. The surface deformation of the first layer is intended to provide a contact angle of less than 100 ^o , 80 ^o or 60 ^o to deposit the second layer on the first layer.

The step of modifying the surface of the first layer suitably comprises the step of treating the surface of the first layer.

Modifying the surface of the first layer suitably includes depositing a surface modification material on the surface of the first layer. This surface modification material can be deposited from a solution in a suitably polar solvent.

Suitably, the first layer is deposited on a surface, and the method comprises heating the substrate prior to depositing the second or third layer.

At least one of the first, second and third layers is formed by inkjet printing.

Suitably, at least one of the source, drain or gate electrode of the transistor is formed by inkjet printing.

Suitably, the transistor has a source, drain or gate electrode formed of a conductive polymer. Suitably, the electrode is formed of an optically transparent conductive polymer. Suitably, the conductive polymer comprises a polymeric counterion dopant.

Suitably, the material of one of the first and second layers is PEDOT / PSS.

Suitably, the transistor has an insulator layer formed of a non-conjugated or partially conjugated polymer. Suitably, the insulating polymer comprises hydrophilic and hydrophobic groups and is usually soluble in a polar solvent.

Suitably, the material of one of said first and second layers is PVP.

According to another aspect of the present invention, there is provided a light emitting device comprising: a first active layer soluble in a first solvent; And a second active layer adjacent to the first active layer, wherein the second active layer is soluble in a second solvent in which the first material is substantially insoluble.

The transistor preferably includes a third active layer which is adjacent to the second active layer and is soluble in a third solvent in which the second material is substantially insoluble. Preferably, one of said first and second layers comprises a polar polymer soluble in a polar solvent, and the other of said first and second layers is a non-polar polymer soluble in a non-polar solvent. Suitably, one of said second and third layers comprises a polar polymer soluble in a polar solvent, and the other of said second and third layers is a non-polar polymer soluble in a non-polar solvent. Suitably, one of the solvents is an alcohol.

Suitably, one of the first and second layers is a source and / or drain electrode layer of the transistor, and the other of the first and second layers is a semiconductor layer of the transistor.

Suitably, one of the first and second layers is a semiconductor layer of a transistor, and the other of the first and second layers is an insulator layer of a transistor.

Suitably, the material forming the semiconductor layer is a polyfluorene derivative.

Suitably, the semiconductor layer has a bandgap of at least 2.3 eV, preferably at least 2.5 eV, and is optically transparent. The semiconductor layer suitably has an ionization potential of 4.9 eV or more, preferably 5.1 eV or more.

Wherein the semiconductor layer comprises a block copolymer having an electron affinity of at least 3.0 eV or 3.5 eV, the block copolymer having a first block of conjugated monopolymer units each connected by at least two covalent bonds, And a second block of units.

Wherein the semiconductor layer comprises a block copolymer having an ionization potential in the range of 5.5 eV to 4.9 eV, the block copolymer having a first block of conjugated monopolymer units each connected by at least two covalent bonds, And a second block of units.

Wherein the first block of the monomer units comprises one or more groups comprising a fluorine derivative, a phenylene derivative and an indenofluorene derivative, and the second group of monomer units comprises a thiophene derivative, a triarylamine derivative, And one or more groups comprising benzothiadiazoles derivatives.

The polyfluorene derivative is suitably F8T2 or TFB.

The semiconductor layer preferably has an ionization potential exceeding 4.9 eV or 5.1 eV.

Preferably, one of the first and second layers is an insulating layer of a transistor, and the other of the first and second layers is a gate electrode layer of the transistor.

One of the first and third layers is an insulating layer of a transistor, the other of the first and third layers is a gate electrode layer of the transistor, and the second layer is an insulating layer of the transistor. The isolation layer may be a surface modification layer.

The isolation layer is preferably a diffusion barrier layer. The diffusion barrier layer may comprise a polyfluorene derivative. The polyfluorene derivative may be F8T2 or TFB.

The first or second layer may be formed by ink-jet printing. The third layer may be formed by inkjet printing.

Wherein one of the first, second and third layers is a source layer of a transistor, the other of the first, second and third layers is a drain layer of the transistor, and the first, The other of the three layers is preferably a gate layer of the transistor.

The material of one of the first and second layers may be PEDOT / PSS.

The material of one of the first and second layers may be PVP.

The transistor may be optically transparent.

The transistor may be a thin film transistor.

According to another aspect of the present invention, there is provided a logic circuit, a display portion, or a memory device including the proposed transistor.

According to another aspect of the present invention there is provided a logic circuit, display portion or memory device comprising an active matrix array of a plurality of said presented transistors.

According to another aspect of the present invention, there is provided a display portion comprising a plurality of display elements, wherein at least one of the display elements is switched by an optically transparent thin film transistor.

Preferably, the transistor is located on the backside of the display member.

The display portion may include an optically active region that can be switched by the transistor, the transistor being electrically connected to the optically active region by means of a conductive object located in a via hole formed through at least one layer of the transistor Region. &Lt; / RTI &gt;

The preferred formation process described herein allows the formation of a solution-treated thin film transistor of fully organic, wherein no layer is converted or cross-linked to an insoluble form. Each layer of such a device can remain in a form that can be dissolved in the solvent from the deposition. This enables a simple method of forming via holes that pass through the dielectric insulating layers based on local deposition of the solvent, which is described in detail below. Such a device may include, for example, one or more of the following components.

- patterned conductive source-drain, gate electrodes and interconnects.

A semiconductor layer having a charge carrier mobility of greater than 0.01 cm 2 / Vs and a fast on-off current switching speed in excess of 10 ⁴ .

- thin gate insulating layer

A diffusion barrier layer that protects said semiconductor layer and said insulating layer from unintentional doping by impurities and ion diffusion.

- a surface strained layer that enables high resolution patterning of the gate electrode by printing techniques.

- via holes for interconnections through the dielectric layers.

However, the method described herein is not limited to the formation of devices having all the features described above.

The formation of the first exemplary device will now be described with reference to FIG. The device of Figure 1 is a thin film field effect transistor (TFT) configured to have an upper-gate structure.

An aqueous solution containing conductive polymer polyethylenedioxythiophene / polystyrolsulfonate (PEDOT (0.5% by weight) / PSS (0.8% by weight)) was applied on top of the cleaned 7059 glass substrate 1 By inkjet printing, the source-drain electrodes 2, 3 and interconnect lines and contact pads (not shown) between the electrodes are deposited. Other solvents such as methanol, ethanol, isopropanol or acetone may be added to affect the surface tension, viscosity and wetting properties of the ink. PEDOT / PSS is available from Bayer under the name "Baytron". The IJP printer is of a piezoelectric type. It is equipped with a precise two-dimensional analysis stage and a microscope stage that enables the alignment of patterns that are printed sequentially on each one. The IJP head is driven by a voltage pulse. Suitable driving conditions for injecting droplets of 0.4 ng of typical solid contents per droplet can be achieved with a pulse height of 20 V, a rise time of 10 s, and a fall time of 10 s. After drying the top of the glass substrate, they produce a PEDOT point having a typical diameter of 50 mu m with a typical thickness of 500 ANGSTROM.

The IJP of the source-drain electrodes is performed in air. Thereafter, the samples are transferred to an inert atmosphere glove box system. The substrates are then spun-dried in an organic solvent such as mixed xylenes in the case of polyfluorene polymers to be used for the deposition of the active semiconductor layer. They are then heat treated at 200 ° C for 20 minutes in an inert nitrogen atmosphere to remove residual solvents and other volatile species in the PEDOT / PSS electrodes. The active semiconductor polymer 4 is then deposited by spin-coating into a thick film of 200-1000 ANGSTROM. Such as polyfluorene co-polymers such as poly-9,9'-dioctylfluorene-co-dithiophene (F8T2), and regioregular poly-3-hexylthiophene Polymers have been used. F8T2 is a preferred choice because it exhibits good stability in air during the deposition of the gate electrode. A 5-10 mg / ml solution of F8T2 (obtained from Romil) in anhydrous, mixed xylenes is spin-coated at 1500-2000 rpm. For P3HT, 1% solution per weight is used in the mixed xylene. Lower PEDOT electrodes are insoluble in polar solvents such as xylene. The films are then spun-dried in a solvent such as isopropanol or methanol, which can then be used for deposition of the gate insulator layer 5.

A subsequent heat treatment step may then be performed to improve the charge transfer properties of the semiconductor polymer. In polymers exhibiting a liquid crystalline state at a high temperature thermal treatment at this temperature, the direction of the polymer chains as a result of the liquid crystal transition is parallel to each other. In the case of F8T2, heat treatment is performed for 5-20 min. 275-285 ℃ under an inert N ₂ atmosphere. The samples are then quickly cooled to room temperature to fix the orientation of the chains and make amorphous glass. If samples are provided on a flat glass substrate without an alignment layer, the polymer employs a multidomain configuration, wherein liquid crystal domains with random orientation are located within the TFT channel. Transistor devices in which F8T2 is provided in a glassy state by rapid cooling from a liquid crystal state showing mobility of about 5-10 &lt; ^-3 &gt; / cm &lt; 2 &gt; / Vs are larger in magnitude than mobility measured in devices having the spun F8T2 films. In addition, the deposited devices exhibit a high turn-on voltage Vo. This is because the density of the localized electron trap state of the vitreous state is lower compared to the deposited state, which is partially determined.

If the polymer is provided in a monodomain state with a uniaxial of polymer chains parallel to the transistor channel, the mobility by factors of typically 3-5 can be further improved. This is accomplished by coding the glass layer with a suitable alignment layer such as a mechanically polished polyimide layer (9 in Figure 1 (b)). In the single domain state, the polymer chains are aligned so as to be uniaxially parallel to the polishing direction of the lower polyimide layer. This further improves the charge carrier mobility of the devices, where the TFT channels are parallel to the alignment direction of the chains. Such a process is described in more detail in co-pending UK Patent Application No. 9914489.1.

After the semiconductor layer is deposited, the gate insulating layer 5 is deposited by spin-coating a solution of polyhydroxystyrene (also referred to as polyvinylphenol (PVP)) from a polar solvent, The polymer is insoluble. The choice of a preferred solvent is an alcohol such as methanol, 2-propanol or butanol, where nonpolar polymers such as F8T2, which have particularly low solubility, do not swell. The thickness of the gate insulating layer is between 300 nm (solution concentration is 30 mg / ml) and 1.3 탆 (solution concentration is 100 mg / ml). The use of poly-methyl-methacrylate (PVA) for poly-vinylalcohol (PVA) or propyleneglycol methyl ether acetate for butyl acetate or water, methacrylate: PMMA) may also be used as well as other insulating polymers and solvents that meet the solubility requirements.

Then, a gate electrode 6 is deposited on the gate insulating layer. The gate electrode layer may be deposited directly on the gate insulating layer (see FIG. 1 (c)) or may be deposited on one or more intermediate layers (FIG. 1 (a) and (b)) may be present.

To form the simple device of Figure 1 (c), the PEDOT / PSS gate 6 may be directly printed on top of the PVP insulating layer 5. The substrate is again transferred to the IJP station in the air where the PEDOT / PSS gate electrode pattern is printed in aqueous solution. The lower PVP gate insulating layer has low solubility in water, whereby the integrity of the gate electrode is preserved during printing of the PEDOT / PSS gate electrode. Although PVP contains high density polar hydroxyl groups, its solubility in water is low due to its backbone similar to nonpolar polystyrene. Similarly, PMMA is insoluble in water. 2 shows transfer characteristics of an IJP TFT having a F8T2 semiconductor layer, a PVP gate insulating layer, and IJP PEDOT / PSS source-drain and gate electrodes. The device characteristics are measured in a nitrogen atmosphere. Continuous measurements show rise (upward triangle) and fall (downward triangle) of the gate voltage, respectively. Properties belonging to the devices were obtained by the newly prepared group (a) of PEDOT / PSS (bithronite) and the group (b) that passed one year. The transistor operation can be clearly shown. However, these devices exhibit anomalous normally-on operation at a positive threshold voltage (Vo)> 10 V, while reference devices formed by depositing gold source-drain and gate electrodes are normally-off, (Vo < 0). &Lt; / RTI &gt; In devices formed from the &quot; old &quot; group of PEDOTs (Fig. 2 (b)), high hysteresis effects are observed due to the high concentration of mobile ionic impurities (see below). If the deep-depleted (Vg = + 40V) from the curved (sweep) is started, the transistor is V ^f _o It is turned on at + 20V (upper triangle). However, in a reverse scan (downward triangle) the transistor is turned off only at V ^f _o &gt; + 35V.

The normal-on operation and the hysteresis effects may be caused by diffusion of ion species of one of the layers of the device. The value of the oddly large positive of Vo implies that the ions are negative. It can be expected that positive species will compensate for a portion of the transfer charge of the accumulation layer and move Vo to a more negative value. To identify the source of these ionic species, other layers and PEDOT source / drain electrodes were formed as described above, while the upper-gate IJP PEDOT electrode was replaced with a deposited gold electrode to form devices. In such a structure it has been found that the devices are normally off and exhibit a stable threshold voltage. This means that the doping and hysteresis effects of the full-polymer device are related to solution deposition of the conductive polymer top gate electrode and migration of the PEDOT solution from the film to the underlying layers of the device, possible diffusion of ionic impurities.

It has been found that the value of the threshold voltage can be controlled and the amount of hysteresis can be reduced by depositing the gate electrode on the heated substrate. This reduces the drying time of water droplets on the substrate. 3 (b) shows the transfer characteristics of the TFT device, in which the substrate was heated to a temperature of 50 [deg.] C during the deposition of the gate electrode. It can be seen that the hysteresis effect is much smaller than at room temperature (Fig. 3B) and that Vo has a relatively small positive value of 6V. By controlling the deposition temperature, the threshold voltage can be adjusted to the range of Vo = 1-20V.

The device having the gate electrodes deposited directly on the PVP layer as shown in Fig. 1 (c) is a depletion type device. Its normal-on operation is useful for depletion type logic circuits such as a simple depletion-load logic inverter (Figure 14 (a)).

During the deposition of the gate, the doping of the semiconductor can be prevented by the bonding of the diffusion barrier layer to form an improved type of normal-off TFTs. In the device of Figures 1 (a) and (b), a thin layer 7 of nonpolar polymer is deposited over the PVP gate dielectric layer prior to deposition of the conductor polymer gate electrode. This layer will act as a diffusion barrier to block the diffusion of ion species through the PVP insulator of weak polarity. The PVP contains a series of high-density poles that tend to improve the conductivity and diffusion of ions through the membrane. Poly (9,9'-dioctyl-fluorene-N- (4-butylphenyl) diphenylamine) (TFB) or F8T2 &Lt; / RTI &gt; were used. Thin films of these polymers of about 50-100 nm can be deposited on the surface of the PVP gate insulating layer from a solution of a nonpolar organic solvent such as xylene where the PVP is insoluble.

Direct printing of PEDOT / PSS from a polar aqueous solution on top of a non-polar diffusion barrier layer or on top of a weakly polar polymer such as PMMA has been found to be problematic due to poor wettability and wide contact angles. To treat this, a surface modifying layer 8 is deposited on top of the nonpolar polymer. The layer provides a hydrophilic surface rather than a hydrophobic surface, wherein the PEDOT / PSS can be formed more easily. This enables high resolution printing of the gate electrode pattern. To form the surface strained layer, a thin layer of PVP can be deposited from an isopropanol solution, wherein the bottom diffusion barrier layer is insoluble. The thickness of the PVP layer is preferably 50 nm or less. High resolution printing of PEDOT / PSS on the surface of PVP is possible. Alternative surface modified layers may be used. These include thin layers of surfactants or polymers such as soaps including hydrophilic and hydrophobic functional groups. These molecules tend to separate into hydrophobic and hydrophilic groups that are attracted to the lower nonpolar polymer and the interface with the free surface, respectively. Another possibility is to briefly expose the surface of the nonpolar diffusion barrier to a weak O ₂ plasma which makes the surface hydrophilic. A suitable plasma treatment that does not reduce the TFT device performance is to expose to 13.5 Mhz O2 plasma at a power of 50 W for 12 seconds.

If the gate electrode is printed from a less polar solvent than water containing alcohol (isopropanol, methanol, etc.), a surface modification layer at the top of the non-polar diffusion barrier may be required.

The integrity of the layer sequence depends on the alternating deposition of polymeric materials extracted from polar and non-polar solvents. The first layer in the solvent used to deposit the second layer is less than 0.1w%, preferably less than 0.01w%, per unit volume.

Criteria for solvent compatibility can be quantified using the Hildebrand solubility parameter for the quantification of polarity (DW van Krevelen, Properties of polyners, Elsevier, Amsterdam (1990)). The solubility of each polymer (solvent) can be described by the parameters δ _d , δ _p , δ _h , which indicate interactions, polarity, and hydrogen bond interactions between molecules of a polymer (solvent) in liquid state. If the molecular structure is known by adding a donor of a polymer of another functional group, then values for the three parameters can be calculated. Most of these polymers are common polymers. Often, δ _p and δ _d are combined to become δ _v ² = δ _d ² + δ _p ² .

The mixed free energy is given by ΔG _m = ΔH _m -T ΔS _m where the mixing entropy is ΔSm> 0 and the mixing enthalpy is ΔH _m = V * φ _p * φ _s * ((δ _v ^p -δ _v ^s ) a ^{_{2 + (δ h p -δ h}} s) 2). Polymer (P) from this I is more soluble than the solvent (S), that is, the less ΔH _{m ^{D = ((δ v p -δ}} v s) 2 + (δ h p -δ h s) 1/2 ). As a rough guideline, if the interaction parameter (D) is less than approximately 5, the polymer may be soluble in the solvent. If D is 5-10, swelling is often observed. When D is larger than 10, the polymer generally does not dissolve in the solvent, and there is no swelling.

In order to obtain the adiabatic interface in the dissolvable TFT device, the D value for each polymer layer and the solvent of the next layer should be approximately 10. This is particularly important for the solvent of the semiconductor polymer layer and the keat dielectric. For F8T2 and isopropanol (butyl acetate), the D value is approximately 16 (12).

In some device configurations, the overall multilayer structure may include polymers that include a polar material group that is well soluble in a polar solvent such as water, or polymers that are soluble in a non-polar solvent such as xylene, It can be a stacked form. In this case, the interaction parameter D is larger due to the difference in δ ₉ between the polymer layer and the next solvent. A high polarity electrode of PEDOT / PSS, a nonpolar semiconductor layer such as F8T2, a high polarity dielectric layer such as polyvinyl alcohol deposited from a storage material, a nonpolar diffusion barrier layer of TFB serving as a buffer layer enabling a series of stacking, / PSS gate electrode is an example.

However, it is often convenient to separate the non-polar semiconductor layer and the polarity gate electrode layer by a single dielectric layer. This layer sequence is possible by having a polymer substance with a slight polarity deposited from a solvent having a slight polarity between the high polarity or nonpolar polymer. Polymers that undergo some polarity are polymers that contain polar and nonpolar groups and are not well soluble in polar solvents. With respect to the solubility parameter, the solubility parameter 隆_H of a slightly polar solvent can be defined as having a significant difference from the base polymer. In this case, even if the polar solubility parameter? _P (? _V ) of the solvent is similar to the base polymer layer, the bulge (large D) can be prevented. The polymer layer having a slight polarity may contain a specific functional group such as a hydroxyl group, and the hydroxyl group functions to dissolve the polymer well in a solvent containing a functional group that attracts the functional group of the polymer. Such attraction may be a hydrogen bonding interaction. Due to the functionality of the polymer, the polymer is well soluble in a material having an appropriate polarity and is not well soluble in a polar solvent. An example of a polymer with suitable polarity is a PVP gate dielectric layer (Figure 1) that lie between the nonpolar semiconductor layer and the PEDOT / PSS gate electrode layer. Examples of the solvent having the appropriate polarity are _{IPA (δ h; F8T2: δ} h ≒ 0) a.

Figure 4 shows the output (a) and transfer (b) properties of all F8T2 IJT TFT polymer layers with a PVP gate insulating layer, an F8 barrier layer, and a PVP surface modification layer as disclosed in Figure 1. [ The device has a pure-to-ideal-normal-off transistor behavior at V ₀ &lt; RTI ID = 0.0 &gt; The threshold voltage shift between the top (top triangle) and bottom (bottom triangle) voltage is ≤1v. The nature of the device is very similar to standard devices fabricated in an inert-atmosphere combination using Au drain and gate electrodes. The field effect fluidity is 0.005-0.01 cm ² / Vs, and the on / off current ratio measured between V _g = 0 and -60 V is 10 ⁴ -10 ⁵ .

The device is fabricated using a wide range of non-polar diffusion barrier layers such as F8, TFB (Fig. 5 (a) shows transfer properties), PS (Fig. 5 (b) shows transfer properties). In each case, pure normally-off behavior and hysteresis effects and threshold voltage shifts can be observed, and this phenomenon is quantitatively equivalent to a reference device with an Au drain electrode. This supports the interpretation that inserting a non-polar polymer under the gate electrode prevents the diffusion of ionic impurities during and during the melt-deposition of the gate insulating layer. It is known that this regenerates the TFT threshold voltage and results in excellent operational stability. A normally-off device having a diffusion barrier is preferred to a normally-off device having a diffusion barrier rather than the depletion device described above, because it has a better long-term threshold voltage stability and a longer lifetime due to the diffusion of ion diffusion being prevented . Composite polymer or oligomer is melt processable materials may be used as a semiconductor layer, in which case the polymer or oligomer material has a suitable field effect mobility in excess of 10 ^-3 cm / Vs, and preferably 10 ^-2 cm / Vs . Suitable materials are described in HE Katz, J. Mater in Chem. 7,369 (1997) or in Advanced Materials 12, 227 (2000) by Z. Bao.

One of the important requirements for processing printing TFTs to have excellent stability and a low on-off current ratio is the excellent stability of the semiconductor material for accidental doping due to atmospheric oxygen and water in the processing and printing processes. Printing TFTs have been fabricated using regloregular P3HT semiconductor polymers deposited as F8T2 (see above) or a mixed xylene solution as the active semiconductor layer. In the case of P3HT TFTs provided in a test device under inert atmospheric pressure, the field effect fluidity in the range of 0.05-0,1 cm ² / Vs is slightly higher than that of F8T2. However, regloregular P3HT is unstable to doping with oxygen and / or water, thereby increasing the film conductivity during the fritting step performed at air and low on-off current ratios. This is related to the low ionization potential in the range of I _P ? 4.9 eV of P3HT. P3HT having a high on-off current ratio of greater than 10 ⁶ was tested, but a reduction doping step such as exposing to hydrazine vapor after deposition was required (H. Sirringhaus et al., Advances in Solid State Physics 39, 101 ). However, in the case of the aforementioned IJP TFTs, such a post-treatment reduction step can not be performed because the PEDOT electrode is doped off and the conductivity is significantly reduced. Therefore, in order to obtain a high current conversion ratio, it is important that the polymer semiconductor is used with excellent stability against accidental doping with oxygen or water.

A group of materials with good peripheral stability and high flowability is an AB hard bar block copolymer comprising a series of ordered A and B blocks. Suitable A blocks are structurally well defined, ladder-type polymers with a large band gap, a single polymer with an ionization potential greater than 5.5 eV, and excellent peripheral stability. Suitable A blocks include fluorine derivatives (US 5,777,070), indifluorine derivatives (S. Setayesh, Macromolecules 33, 2016 (2000)), phenyl or ladder type phenyl derivatives (J, Grimme et al., Adv. , 292 (1995)). Suitable B blocks include hole transport moieties with small band spacings, including heteroatoms such as sulfur or nitrogen, and have an ionization potential of less than 5.5 eV as a single polymer. The role of the B block is to lower the ionization potential of the block copolymer. The ionization potential of the block copolymer is preferably a 4.9eV≤I _p ≤5.5eV. An example of such a copolymer is F8T2 (ionization potential 5.5 eV) or TFB (US 5,777,070).

Another suitable hole transporting polymer is a single polymer of a polycyanophene derivative with an ionization potential greater than 5 eV, such as polythiophene with alkoxy or fluorine and side chains (RD McCullough, Advanced Materials 10, 93 (1998) ).

Instead of the hole-transporting semiconductor polymer, a fusible electron-transporting material may be used. They require an electron affinity greater than 3 eV to prevent atmospheric impurities such as oxygen acting as a carrier trap from remaining. Electron transport small molecule semiconductors (disclosed in H.E. Katz et al., Nature 404, 478 (2000)) or polymeric fluorinated derivatives having electron-donating fluorinated side chains can be included. It is also possible to use a structurally well defined AB type block copolymer, a ladder type A block with an ionization energy greater than 5.5 eV, and a B block for electron transport which increases the electron affinity of the copolymer by more than 3 eV, preferably greater than 3.5 eV Do. Examples of A blocks include, but are not limited to, fluorine derivatives (US 5,777,070), idenofluorene derivatives (S. Setayesh, published in Macromolecules 33, 2016 (2000)), phenylenes or ladder phenylalanine derivatives (J. Frimme et al. Mat., 7,292 (1995)). The B block for electron transport is a benzocyclohexane derivative (US 5,777,00), a phenyl derivative, a naphthalene tetracarboxylic dimide derivative (HE Katz et al., Published in Nature 404, 478 (2000)) or a fluorinated cefoxin derivative have.

For fast operation of the logic circuit, the channel length (L) of the transistor and the overlap (d) between source / drain and gate should be as small as possible. The critical dimension is L. This is because the operating speed of the transistor circuit is roughly proportional to L &lt; ^{-2 &} gt ;. This is important for semiconductor layers having relatively low fluidity.

This high resolution pattern can not be achieved with current inkjet printing technology, and even with the latest IJP technology (Fig. 6), the feature size is limited to 10-20 占 퐉. If fast operation of the features and high-density packing are required, techniques should be adopted to enable finer feature resolution. The techniques described below use ink surface interactions to define inkjet droplets on the substrate surface. Making the channel length smaller can be accomplished by the above techniques rather than the prior art.

The above described technique can deposit the deposition material on the substrate with high resolution. First, the surface of the substrate is processed so that some selected surfaces are relatively repulsive with relatively attractive forces on the material to be deposited. For example, some surfaces are hydrophobic and some others are hydrophilic. By performing the preliminary pattern processing step with high resolution and / or accurate registration, subsequent deposition can be accurately performed.

Fig. 7 shows an embodiment of the preliminary pattern processing. Fig. 7 shows the formation of the device of Fig. 1 (c) with a particularly fine channel length L. Fig. 1 (c), the same reference numerals are used. Figure 7 (b) shows printing and ink restraints on pretreated substrates.

Prior to deposition of the source-drain electrodes 2 and 3, a thin polyimide layer 10 is formed on the glass sheet 1. The polyimide layer 10 is finely patterned to be removed at a position where the source-drain electrode is formed. The removal step can be performed by photolithography capable of high resolution and / or accurate registration. In one example of such a process, the polyimide may be covered with a layer of photoresist 11. The photoresist is patterned photolithographically so that it can be removed where the polyimide is removed. Next, the polyimide is removed by a process in which the photoresist is resistant. The polyimide is selected because it has hydrophobicity as opposed to being relatively hydrophilic. Next, a PEDOT material forming the source-drain electrode is deposited over the hydrophilic substrate region 12 by ink-jet printing. When the ink droplet spreading on the glass substrate region touches the boundary of the hydrophobic polyimide region 12, the ink repels and does not flow into the hydrophobic surface region. With this limiting effect, the ink is deposited only on the hydrophilic surface, and a high resolution pattern with small spacing and a transistor channel length of less than 10 mu m can be formed (Fig. 7 (b)).

FIG. 7 (a) shows an embodiment of a process in which the polyimide is removed or the relative surface effect is increased after removal of the polyimide. The polyimide layer 10 and the photoresist 11 are exposed to an oxygen plasma. The oxygen plasma etches the thin (500 Å) of the polyimide layer faster than the thick (1.5 袖 m) photoresist layer. The exposed glass surface 12 in the source-drain electrode region is exposed to an oxygen plasma prior to removal of the photoresist to become hydrophilic. It should be noted that, during removal of the polyimide, the surface of the polyimide is protected by the photoresist and remains hydrophobic.

If necessary, the surface of the polyimide may be further rendered hydrophobic by further exposing it to CF ₄ plasma. The CF ₄ plasma only fluorinates the polyimide surface and does not interact with the hydrophilic glass substrate. This additional plasma treatment may be performed after fluorination of only the side surface of the polyimide pattern 10 or after removing the photoresist by removing the photoresist before removing the photoresist.

The contact angle of water PEDOT / PSS in oxygen plasma treated 7059 glass is θ _glass ≒ 20 °, in contrast to the contact angle θ _PI ≒ 70-80 ° at the polyimide surface. The contact angle of PEDOT / PSS in water in the fluorinated polyimide is 120 °.

When the PEDOT / PSS layer is deposited as a pre-patterned polyimide layer from the aqueous solution as described above, the PEDOT / PSS ink has a source-drain (not shown), even though the channel length L is only a few microns Electrode region.

In order to facilitate the definition of ink droplets, the kinetic energy of the ink droplets is kept as small as possible. The larger the size of the droplet, the greater the likelihood that the spreading droplet will ignore the hydrophilic confinement structure or spill into a neighboring hydrophilic region.

The deposition of the ink droplet 13 is preferably performed on the substrate 12 at a distance d between the center of the ink droplet and the polyimide boundary. On the other hand, d needs to be small enough so that the spreading ink touches the boundary, allowing the PEDOT film to extend across the polyimide boundary. On the other hand, it is necessary that d is sufficiently large so that the rapidly spreading ink does not spill into the hydrophobic region. This increases the risk that the PEDOT deposition on top of the polyimide 10 will limit the TFT length and can form a short circuit between the source and drain electrodes. In order for the PEDOT droplets containing 0.4 ng of solid component to be deposited as oxygen plasma treated 7059 glass with a horizontal distance between adjacent droplets of 12.5 占 퐉, d? 30-40 占 퐉 was found to be suitable. The optimum d value depends not only on the deposition pitch, which is the horizontal distance between successively deposited droplets, on the period of deposition of the droplets and on the drying time of the solution, but also on the wettability of the surface.

The hydrophobic confinement layer, which defines the channel length of the transistor, may provide a second function. In a subsequent deposition step of depositing a semiconductor polymer into the channel of the transistor, this can be used as an alignment tool. The polyimide layer 10 may be mechanically polished or photo aligned and used as an alignment layer 9 (Fig. 1 (b)) to provide a single-domain alignment of the liquid crystal semiconductor polymer 4.

Similarly, the gate electrode 6 may be defined by the patterned layer 14 formed on the top of the gate insulating layer 5. The gate leading layer (5) has a surface region that attracts or repels against the solution in which the gate electrode is deposited. The patterned layer 6 may be aligned along the source-drain pattern to minimize the overlap region between the source / drain and the gate electrode (Fig. 7 (c)).

Materials other than polyimide can be used as the pre-patterned layer. Other sophisticated preliminary pattern processing techniques other than photolithography may be used.

Figure 8 illustrates the ability to define a liquid " ink " that is relatively hydrophobic and has a hydrophilic layer structure deposited by inkjet printing. 8 shows the optical microstructure of a substrate comprising a thin polyimide strip 10 treated to be relatively hydrophobic as described above and a wide glass substrate area 12 treated to be relatively hydrophilic as described above . The PEDOT material used as the source-drain electrode is deposited by inkjet printing a series of droplets that flow in lines 2, 3 adjacent to the strip 10. Although the ink jetted material exhibits a low contrast, it can be seen that the deposited material at the end surfaces 2, 3 of the deposited material is limited to the strip 10 to reach the strip thickness (L = 5 占 퐉) have.

9 is a view showing an inkjet deposition process in the vicinity of the polyimide strip 10. The image was taken with a stroboscopic camera mounted below a transparent substrate. The ends of the polyimide pattern 10 appear as white lines. The ink droplet 21 is ejected from the nozzle of the ink head 20 and the droplet center thereof is landed at a distance d from the polyimide strip 10. This image can be used to finely and locally align the inkjet deposition along the strip pattern 10 and to automate the local alignment process using pattern recognition (see below).

Figs. 10 and 11 show the output and transfer characteristics of a transistor formed by the method of Fig. 7 (c) and each having a channel length L of 20 mu m and 7 mu m defined by the above-described differential wetting process. In each case, the channel width is 3 mm. 10 (a) shows the output characteristics of a 20 탆 device. 10 (b) shows the output characteristics of a 7 [micro] m device. 10 (c) shows the transfer characteristics of a 20 [micro] m device.

11B shows the transfer characteristics of a 7 [mu] m device. The 7 μm device exhibits characteristic short channel operation with reduced current at small source-drain voltages and limited output conductance under saturated conditions. The mobility and on-off current ratio of the short channel is similar to that of the long channel device discussed above. That is, μ = 0.005 - 0.01 cm ² / Vs and I _ON / I _OFF = 10 ⁴ - 10 ⁵ .

Ink limitations are the result of differences in the moist nature of hydrophobic and hydrophilic surfaces and do not require the presence of a topographic profile. In the above embodiment, the polyimide film can be made very thin (500 Å). This is much smaller than the size of the droplet of ink in the liquid state (several micrometers). Thus, other methods for forming a substrate pre-pattern, such as a patterned self-assembled monolayer (SAM), for example a fluorine or an alkoxy group such as hydrophobic alkyl or trifluoropropyl-trimethoxysilane, A method of functionalizing the surface of a glass substrate with a SAM containing a group can be used. SAMs are prepared by appropriate methods such as UV light exposure through a shadow mask (as disclosed by H. Sugimura et al. In Langmuir 2000, 885 (2000)) or micro-contact printing (Brittain et al. In Physics World May 1998, p. Can be patterned.

Since pre-patterning is performed prior to deposition of a layer of TFT, the pre-patterning of the substrate is easily compatible with the process flow described above. Thus, a wide range of patterning and printing methods can be used to generate a high-resolution pre-pattern without the risk of degrading the polymer layer.

Similar methods can be applied to pre-pattern the surface of the gate insulating layer or the surface strained layer prior to the deposition of the gate electrode so as to achieve small overlapping performance. As shown in Fig. 7C, the gate electrode 6 may be defined by the patterned layer 4. One example of such pre-patterning is micro-contact printing or UV photopatterning of a magnetically bonded monolayer (SAM) containing a methoxysilane group such as chlorosilane or octadecyltrichlorosilane. These molecules form a stable monolayer on the surface of SiO ₂ or a glass substrate on which the molecules are chemically bonded to the hydroxy group on the polar surface to render the surface hydrophobic. The inventors have discovered that it is possible to form a similar monolayer on the surface of a gate dielectric polymer such as PVP or PMMA. This is believed to be due to the binding of molecules to the hydroxy group on the PVP surface. Surface free energy patterns consisting of source-drain electrodes surrounded by SAM-coated wastewater areas and fine wastewater lines with well-defined small overlapping areas can be easily defined by soft lithographic stamping. To align the stamp pattern with the underlying source-drain electrode, stamping can be performed under an optical microscope or mask alignment device. When induction is made, the water-based polymer ink is confined to fine hydrophilic lines defined by the magnetically bonded monolayer. In this way, a line width smaller than the typical line width on the gate dielectric layer where no pattern is formed can be obtained. As a result, the source-drain to gate overlap capacitance decreases.

With the aid of the pre-patterned substrate, it is possible to assemble a high speed logic circuit based on the assembly process through the TFT and via hole described herein.

One of the important requirements for the assembly of transistor circuits on large areas is the alignment and alignment of the deposition on the pattern on the substrate. It is particularly difficult to obtain adequate matching on a flexible substrate that exhibits distortion over a large area. If the substrate is twisted between subsequent patterning steps, the next mask level in the lithographic printing process will no longer overlap with the underlying pattern. Since the position of the ink jet head can be locally adjusted to the pattern on the substrate, the high resolution ink jet printing process developed here is suitable for achieving accurate registration over a large area on a plastic substrate (FIG. 9). This local alignment process may be automated using a pattern recognition technique using images such as the case of FIG. 9 combined with a feedback mechanism to calibrate the position of the ink jet head.

In order to form a multi-transistor integrated circuit using a device of the type described above, it is desirable that the via holes are directly interconnected through the thickness of the device. Whereby this circuit can be formed particularly small. One way to make such interconnection is to use a via hole formed of a solvent. This will be described in detail below. This method has an advantage that none of the solution treatment layers of the above-described TFTs is converted into a non-melting form. Whereby the via hole is opened by local deposition of the solvent.

To make a via hole (Fig. 12A) formed by a solvent, an appropriate amount of solvent 29 is locally deposited on top of the layer where the via hole should be formed. The solvent is selected so as to melt the lower layer in which the via hole is formed. The solvent seeps into the layer by gradual dissolution until the via hole is formed. The dissolved material is deposited on the side wall W of the via hole. The type of solvent and its deposition method are selectable according to the respective application. However, the following four cases are preferable.

1. Solvent and process conditions must be met so that the solvent can be easily removed so that it does not evaporate or otherwise cause undue or inaccurate dissolution of the device without interfering with subsequent processes.

2. The solvent should be deposited by an optional process such as IJP, whereby a precisely controlled amount of solvent can be accurately applied to the desired point on the substrate.

3. The diameter of the via hole is affected by the surface tension of the droplet and the ability of the substrate to wet the substrate.

4. Solvent does not dissolve the underlying layer where electrical connection is to be made.

Figure 12a shows the deposition of a methanol droplet 29 (containing 20 ng per droplet) on a generic type of parting transistor device illustrated in Figure 1c. The partial device of FIG. 12A includes a PVP insulating layer 28 of 1.3 μm thickness, a F8T2 semiconductor layer 27, a PEDOT electrode layer 26, and a glass substrate 25. In this example, it is preferable to form the via hole through the insulating PVP layer. Methanol is easily selected as a solvent because of its ability to dissolve PVP. The reason for this is that it can easily evaporate so as not to interfere with subsequent processes and has satisfactory wet properties of PVP. In this example, in order to form a via hole, the IJP printing head moves to a point on the substrate where a via hole is to be formed. The required number of methanol droplets drops from the IJP until the via hole is formed. The interval between successive dropping drops is chosen to match the rate at which methanol dissolves the layer of the device. It is preferred that each droplet is completely or nearly completely evaporated before the next droplet is deposited. It should be noted that when the via hole reaches the bottom non-polar semiconductor layer, the etching process is stopped so that the bottom layer is not removed. Other solvents such as isopropanol, ethanol, butanol or acetone may also be used. In order to increase the throughput, it is preferable to form a via hole by vapor deposition of a single droplet of solvent. For a 300 nm thick film, a droplet with a volume of 30 pl and a diameter of 50 탆, the solubility of the layer in the solvent should be higher than 1-2 wt% per volume. If it is necessary to form a via hole with a single droplet, a higher boiling point is required. For PVP, 1,2-dimethyl-2-imidazolidinone (DMI) having a boiling point of 225 &lt; 0 &gt; C can be used.

12B shows that several drops of methanol are sequentially dropped on the points where the via holes are formed. The right panel shows a photomicrograph of the device after dropping 1, 3, and 10 drops. The left panel shows the Dektak surface profile measurement of the same device across the via hole when the via hole is formed. (The points of the via holes are indicated by the position " V " in each panel.) When a plurality of droplets are sequentially deposited at the same point, a hole is formed in the PVP film. The depth of the hole increases as the droplet continues to fall, and after approximately 6 drops, the surface of the underlying F8T2 layer is exposed. The dissolved PVP material is deposited in the side wall W of the via hole. The diameter of the via hole is approximately 50 μm, which is limited by the size of the droplet. This size is suitable for many applications such as logic circuits, large display devices, and the like.

The diameter of the via hole is determined by the size of the inkjet solvent droplet. The depth of the hole was observed to be proportional to the diameter of the droplet (see FIG. 12C). The outer diameter of the sidewalls is determined by the size and spread of the first droplet, which is independent of the thickness of the polymer layer to be dissolved. As the thickness of the polymer increases, the inner diameter of the sidewall decreases. In fields where smaller holes are required, such as high resolution display devices, smaller droplet sizes may be used and the substrate surface may be pre-patterned by any suitable method to define droplets on the surface as described above. Other solvents may also be used.

By the measurement of the surface profile, the material can be dissolved by the formation of the via hole to be displaced to the edge of the via hole, and the state is maintained after the solvent is spouted (as shown by W in Fig. 12B). It should be noted that the displaced material is of a smoother shape than that illustrated in FIG. 12B. The scale of the x and y axes of the surface profile graph of Figure 12b is different (x is μm, y is Å).

It is believed that the mechanism for via hole formation, i.e., the movement of material to the sidewalls, is similar to that of the well-known coffee-stain effect. This effect occurs when the contact line of the droplet that is drying contains solute. Adhesion may also occur due to, for example, surface roughness or chemical heterogeneity. It should be noted that the deposition of a good solvent always generates surface roughness during dissolution. When the solvent evaporates, capillary flow occurs to replace the solvent that evaporates near the contact line. Since the surface to bulk ratio near the contact line is large, more solvent evaporates near the contact line. The capillary flow rate is large compared to the conventional diffusion rate. Thus, the solute is delivered to the edge of the droplet, solute deposition occurs only near the rim, and does not occur at the center of the droplet being dried (RD Deegan et al., Nature 389, 827 (1997)). Diffusion of the solute tends to encourage homogeneous redeposition of the polymer over the entire area when the solvent is dried, rather than forming sidewalls. Capillary flow velocity v (r) is proportional to (where, r:: distance from the center, the radius R of the drops) is (Rr), ^-λ _{(where, λ = (π-2θ c} ) / (2π-2θ c)) Is predicted by theory. Therefore, v increases as λ increases. That is, the contact angle? _C decreases. Thus, the smaller the contact angle is, the faster the deposition at the edge occurs.

Therefore, in the case of forming a via hole, it is necessary to (a) fix the contact line of the initial droplet, (b) sufficiently reduce the contact angle of the droplet on the dissolved polymer, and (c) It is important that evaporation is fast enough. For IPA on PVP, the contact angle is about 12 [deg.] And droplets are dried within less than one second.

The smaller the contact angle, the faster the capillary flow rate in the droplet. In other words, the formation of the side wall becomes more certain. However, on the other hand, the smaller the contact angle is, the larger the diameter of the droplet becomes. Therefore, the optimum contact angle is an angle at which a via hole with a small diameter having a well-defined sidewall can be obtained. In order to obtain a larger contact angle in a good solvent, the surface of the substrate may be treated with, for example, a magnetically bonded monolayer having a high permeation preventing property of the solvent. The magnetically bonded monolayer may be patterned to provide hydrophobic and hydrophilic surface areas to confine the deposition of the solvent to a small area.

The depth and etch rate of the via holes can be controlled by a combination of the number of drops of the solvent, the deposition frequency, and the evaporation rate of the solvent compared with the substrate dissolution rate. The environment in which the deposition takes place and the temperature of the substrate may affect the rate of evaporation. A layer of a material that is not soluble in the solvent or dissolves very slowly may be used to limit the depth of dissolution.

Since the layer of the TFT is constituted by alternately arranging the polar layer and the non-polar layer, the solvent and solvent combination can be selected so that the etching is stopped at a well defined depth.

A conductor layer may be deposited thereon so as to extend into the via hole and be electrically connected to the material at the bottom of the via hole so as to be contactable via the via hole. 13A shows a device of the type shown in FIG. 12A, but includes a gold electrode 25 formed after forming a via hole as described above.

13 shows the curve 30 of the current-voltage characteristics measured between the bottom PEDOT electrode 25 and the conductor electrode 29 deposited on top of the PVP gate insulating layer 28. FIG. The diameter of the via hole was 50 탆. For comparison, curve 31 shows the reference sample. In this curve, no via hole is located in the overlapping region between the upper and lower electrodes. The characteristic clearly shows that the current through the via hole is several times the leakage current through the gate insulating device without via holes. The current through the measured via holes is limited by the conductivity of the PEDOT electrode, as can be seen by performing a conductivity measurement of the individual PEDOT electrodes. Since this is not limited by the resistance of the via-hole, only the lower limit of the via-hole resistance R _V can be obtained from these measurements: R _V <500 kΩ.

The via hole forming method described above with reference to FIG. 12 can be applied directly to a small model device having no diffusion barrier (as shown in FIG. 1C) and to a device in which a diffusion barrier is deposited after the via hole is formed. 14A shows a device in which a via hole is formed, and then a gate electrode is deposited without a diffusion barrier layer interposed therebetween. 14B shows a device in which the diffusion barrier polymer 7 is formed before the gate electrode 6 is deposited after the formation of the via hole. In this case, the diffusion barrier layer needs to exhibit good charge transport characteristics in order to minimize the via hole resistance R _V. A suitable diffusion barrier is a thin TFB layer as shown in Figure 5A.

When a low contact resistance is required, the semiconductor layer can also be removed at the via hole position. This is preferably done after the diffusion barrier is formed. The diffusion barrier 7 and the semiconductor polymer 4 can be locally dissolved by IJP deposition of a good solvent-xylene in this example. By mixing a good solvent for both the semiconductor material and the insulating material, both of these layers can be dissolved simultaneously. A device in which the gate electrode is subsequently deposited is shown in Fig. 14C.

The mixture of solvents may also be used to reduce the diameter of the via holes by increasing the contact angle of the solvent mixture on the layer to be dissolved. Another method of depositing a conductive material to form a via hole interconnect thereon is to locally deposit a material that can locally transform the substrate of the underlying layer to become a conductor. For example, there is local IJP deposition of a solution containing mobile impurities that can diffuse into one or more layers. This is illustrated in Figure 14d. Region 32 refers to a material that has been treated with impurities to become a conductor. The impurity is a small conjugated molecule such as triarylamine such as N, N'-diphenyl-N, N'-bis (3-methylphenyl) - (1,1'-biphenyl) -4,4'- diamine . Impurities are preferably delivered as in the case of solvents.

The via hole formation method through the PVP dielectric layer can be used to connect the gate electrode of the TFT to the source or drain electrode in a lower layer required, for example, in a logic inverter device as shown in Fig. Similar via hole connections are required in most logic transistor circuits. Figure 16 graphically illustrates the characteristics of an enhanced-load inverter device formed with two normally off transistor devices as in Figure 15b. Two inverters with different ratio of channel width to channel length ratio (W / L) are shown (graph 35 ratio 3: 1, graph 36 ratio 5: 1). It can be seen that when the input voltage changes from logic low to logic high, it changes from a logic high (-20V) to a logic low (? 0V). The gain of the inverter, in other words the maximum slope of the characteristic, is greater than one. This is a necessary condition to allow assembly of more complex circuits, such as ring oscillators.

The via holes as described above can also be used to provide an electrical connection between interconnect lines in different layers. For complex electronic circuits, multilevel interconnect structures are required. This is formed by depositing a different dielectric layer 70 (71) with a series of interconnects 72 deposited from a compatible solvent (Fig. 15d). Then, the via hole 73 is formed in the above-described manner. The interconnect line provides an automatic etch stop function.

An example of a suitable dielectric material is a polar polymer 70, such as PVP, and a non-polar dielectric polymer 71, such as polystyrene. They can be alternately deposited from polar and nonpolar solvents. As long as the lower dielectric layer provides an etch stop layer, via holes can be formed by local deposition of a good solvent of each dielectric layer.

It should be noted that in selecting the material and deposition process of the device of the type described above, a great advantage can be obtained when each layer is deposited from a solvent that does not substantially dissolve the layer immediately below it. In this way, the layer can be continuously formed by the treatment of the solution. One way to simplify the selection of such materials and process steps is to deposit two or more layers alternately from polar and nonpolar solvents, as exemplified as the continuous layer described above. Thus, it is possible to easily form a multi-layer device including a conductor, a semiconductor, and an insulator layer which can be melted. This avoids the problem of dissolution and expansion of the underlying layer.

The structures, materials, and processes of the devices described above are merely examples for illustrating the present invention, and thus various modifications are possible.

A device configuration different from the top-gate configuration shown in FIG. 1 can be used. Another configuration is the more standard bottom-gate configuration shown in FIG. If necessary, a diffusion barrier 7 and a surface strained layer 8 may also be included. In Fig. 17, similar parts are denoted by reference numerals used in Fig. Other device configurations with different layer orders can also be used. A device other than the transistor may be formed in an analog manner.

PEDO / PSS can be replaced with any conductive polymer that can be attached from solution. Examples of such include polyaniline or polypyrrole. However, some of the interesting features of PEDO / PSS include (a) inherently poorly dispersed polymeric dopant (PSS), (b) good thermal stability and stability in air, And (c) an operating capability of about 5.1 eV that is well suited to the ionization potential of a common hole-transferring semiconductor polymer that allows efficient hole charge carrier injection.

Efficient charge carrier injection is particularly important for short channel transistor devices with a channel length L less than 10 [mu] m. The source-drain contact resistance effect in such a device can limit the TFT current for a small source-drain voltage (see Fig. 10B). It has been found that, for devices with significant channel lengths, implantation from PEDOT source / drain electrodes is more efficient than implantation from inorganic gold electrodes. This indicates that the inorganic electrode material is preferably a polymer source-drain electrode having an ionization potential well suited to the ionization potential of the semiconductor.

The conductivity of PEDOT / PSS deposited from aqueous solution (Baytron P) is on the order of 0.1 to 1 S / cm. Higher conductivities with an upper limit of 100 S / cm can be achieved with a formulation containing a mixed solvent (Bayer CCP 105T containing isopropanol and N-methyl-2-pyrrolidone (NMP) &Lt; / RTI &gt; In the latter case care must be taken that the solvent combination of the siblings may be compatible with the solubility requirements of the layer arrangement. In applications where higher conductivity is required, another conductive polymer, or a solution-treating inorganic conductor, such as a gelatin suspension in which the metallic inorganic particles remain in a liquid state, may be used.

The processes and devices described herein are not limited to devices fabricated from solution-treated polymers. A portion of the conductive electrodes and / or interconnection of the TFT in a circuit or display device (see below) may be formed, for example, by depositing a glue suspension on a pre-patterned substrate, And may be formed of a conductor. For devices in which all layers are not adhered from solution, one or more of the PEDOT / PSS portions of the device may be replaced with a poorly conductive material, such as a vacuum deposition conductor.

The semiconductor layer may also be replaced by another solution-processing semiconductor material. Small conjugated molecules with solubilized side chains (Journal of the American Chemistry Society 120, 664 (1998), J. G. J. G. Laquindanum et al., Semiconductor organic-inorganic hybrid materials self-bonded from solution [Science 286, 946 (1999), author: egg. C. R. Kagan et al.) Or solution-bound inorganic semiconductors such as CdSe nanoparticles (Science 286, 746 (1999); B. A. Ridley et al.] May also be included.

The electrodes can be patterned with other techniques than ink jet printing. Suitable techniques include, but are not limited to, soft lithographic printing [Physics Letter 75, 1010 (1999), a. J. A. Rogers et al .; Physics World, May 1998, p. 31, author: S. S. Brittain et al.], Or screen printing [Chemical Material 9, 12999 (1997), Author: Rat. Z. Bao et al.], Or photolithographic patterning (see WO 99/10939) or plating, or simple immersion coating of patterned substrates with hydrophobic and hydrophilic surface areas, and the like. Ink jet printing is particularly suitable for patterning large areas, particularly rigid plastic substrates, while maintaining good printing consistency.

Such a device may be mounted on a flexible plastic substrate such as polyethersulfone or other substrate material such as Perspex (trade name) instead of a glass plate. Such a material is preferably in the form of a plate, preferably a polymer material, and may also be transparent and / or flexible.

While it is preferred that all layers and components of the device and circuit be adhered and patterned by solution processing and printing techniques, one or more components such as a semiconductor layer may be attached by a vacuum deposition technique and / . &Lt; / RTI &gt;

Devices such as TFTs fabricated as described above may be components of more complex circuits or devices in which one or more of these devices are integrated with each other and / or with other devices. Examples of such application devices include logic circuits and active matrix circuits for displays or memory devices, or user-defined gate array circuits.

The basic component of the logic circuit is the inverter shown in Fig. When all the transistors on the substrate are of the depletion type or the accumulation type, there are three possible configurations. The depletion-load inverter (see FIG. 15A) is suitable for normally-on devices (see FIGS. 1C and 3) and the improved load configuration (see FIG. 15B) 1a, 1b, and 4). Both of these structures require a via hole between the gate electrode of the load transistor and each of the power source and the drain electrode of the load transistor. Another configuration is a resistive load inverter (see Fig. 15C). The latter device can be fabricated by printing a thin and wide PEDOT line with a suitable length and conductivity as a load resistor. For example, by decreasing the conductivity of PSSPEDOT by increasing the ratio of PSS to PEDOT, the length of the resistor line can be minimized. PEDOT / (PEDOT + PSS) Conductivity of Baytron P PEDOT / PSS with a weight ratio of 0.4 was measured at a level of 0.2 S / cm for conventional deposited films. The conductivity was increased to 2 S / cm by annealing to 280 ° C for 20 minutes under N ₂ atmosphere. By diluting the solution with PSS, the conductivity could be reduced to that level of scale. When the weight ratio of PEDOT / (PEDOT + PSS) was 0.04, the conductivity after annealing at 280 ° C was measured to be 10 ^-3 S / cm. A line of PEDOT having a width of 60 mu m and a length of 500 mu m was ink-jet printed to produce a resistor having a resistance value of 50 M OMEGA.

Other inkjet printing components that have already been developed, such as transistors, via hole interconnects, resistors, capacitors, and multilayer interconnect schemes, are used to fabricate integrated electronic circuits by a combination of direct printing and solution processing Can be integrated. Inkjet printing can be used for all processing steps where side patterning is required. The simple inverter circuit already described is a building block for more complex logic circuits.

A solution-processing TFT as described above may be applied to a liquid crystal display (LCD) or an electrophoretic display (Nature 394, 253 (1998), author: Non- An active matrix display, such as an active matrix display, such as a light emitting diode display such as the one shown in Fig. 18 (B Comiskey et al.) And a suitable circuit is shown in Fig. 18b (Science 280, 1741 (1998) Such as H. Sirrinhaus et al., Or may be used as an active matrix addressing element of a memory device, such as a random access memory (RAM). 18A and 18B, the transistors T1 and T2 may be formed with the transistors as described above. Reference numeral 40 denotes a display or memory element having current and voltage supply pads.

An example of a possible device configuration for controlling the voltage on the electrodes of an LCD or electrophoretic display is shown in Fig. 19, wherein the same elements as in Fig. 1 are designated by the same reference numerals. 19, the gate insulating layer may comprise a multi-layer structure including a diffusion blocking wall and / or a surface strained layer as in FIG. 1A. In FIG.

18, the power source and gate electrodes 2 and 3 of the TFT are connected to the data lines 44 and addressing lines (not shown) of the active matrix, which may be made of other conductive materials to obtain appropriate conductivity over a longer length 43. The drain electrode 3 of the TFT may be the pixel electrode 41. [ The pixel electrode may be formed of another conductive material as in Fig. In a device that depends on application of an electric field rather than charge carrier injection, the electrode 41 may not be in direct contact with the display device 40 such as liquid crystal or electrophoretic ink. In such a configuration, the total pixel area occupied by the TFT and the interconnect line must be kept small so that an appropriate aperture ratio can be obtained and the signals on the data line 43 and addressing line 44, The potential crosstalk between the elements 40 can be reduced.

The configuration of Fig. 19B is more complicated. However, the entire pixel or most of it in the pixel region may be used for TFT and interconnect lines, and the display element is shielded from the signal on the data line 43 and addressing line 44 by the pixel electrode 41. In order to manufacture such a structure, a via hole filled with an additional dielectric layer 42 and a conductive material 45 is required in order to connect the pixel electrode 41 to the TFT drain electrode 3. The via hole can be manufactured by the procedure as described above.

In such a configuration, the opening ratio may be minimized or almost 100%. This configuration can also be used for display application devices with a backlight, such as a full-reach LCD display, because all of the polymer TFTs, as made here, have high transparency in the visible spectrum. Figure 20 shows the optical absorption spectra measured on F8T2 polymer TFTs where the polymer chains are shortened by attaching the liquid crystal semiconductor polymer onto a friction polyimide alignment layer that also serves as a pre-patterned layer for high resolution printing. It can be seen that the device is very transparent in most visible spectral regions due to the relatively high band gap of F8T2. If a semiconductor layer having a larger bandgap such as F8 or TFB or another polyfluorene derivative (see U.S. Patent No. 5,777,070) is used, even better transparency can be achieved. The alignment of the polymer chains is such that the optical anisotropy which allows the light polarized parallel to the alignment direction (shown by the symbol "∥") to be absorbed more strongly than the light polarized perpendicular to the alignment direction (shown by the "⊥" . Optical anisotropy may be used in an LCD display to further increase the optical transparency of the TFT by orienting the alignment of the polymer chains perpendicular to the polarization prism between the glass back surface and the backlight. When the thickness of the F8T2 layer is 500 angstroms or less under light-polarized state, the transistor device appears almost colorless in visible light. All other layers of the TFT including PEDOT have low optical absorption in the visible spectrum region.

Another advantage of the semiconductor device with low optical absorptivity is that the photosensitive characteristic of the TFT is reduced to visible light. In the case of an amorphous silicon TFT, a black matrix should be used to prevent a large off-current under light illumination. In the case of a polymer TFT semiconductor having a wide bandgap, it is not necessary to protect the TFT from ambient light and the backlight of the display.

19B is also suitable for the driving transistor Tl of the LED display (see Fig. 18B), because the source and drain electrodes having a large channel width W using the entire region below the pixel electrode 41 So that the drive current of the TFT can be increased.

Alternatively, the bottom gate TFT configuration of Figure 17 may be used in all of the above applications (see Figure 19c).

One of the important technical considerations in the production of the active matrix circuit is the contact between the PEDOT / PSS TFT and the pixel electrodes 2, 3, 6 and the metal interconnect lines 43, 44, 41. Due to the strongly acidic nature, PEDOT / PSS can not be compatible with many conventional inorganic metals such as aluminum. Aluminum is easily oxidized when in contact with PEDOT / PSS. One possible solution is to fabricate interconnect lines and pixel electrodes 43, 44 and 41 with indium tin oxide (ITO) or tantalum, tungsten, and other materials that are more refractory in this environment , Or use an appropriate barrier wall layer.

In the case of application to a display, it is also preferable to manufacture a TFT having a short channel length by printing on the pre-patterned substrate indicated by reference numeral 10 in Fig. 19 as described above.

If the pixel element to be controlled is a memory element, such as a capacitor or a diode, as well as a display element, for example a dynamic random access memory, a similar device configuration for an active matrix transistor switch may be used.

In addition to the conductive electrodes, some other layers of the TFT may also be patterned by direct printing techniques such as screen printing or IJP. 21A (the same elements as those in FIG. 1 are denoted by the same reference numerals in FIG. 21A) shows a device in which the active layer island of the semiconductor layer 4 and the gate insulating layer 5 are directly printed. In this case, a via hole is not required, but a connection portion can be formed by direct printing of the appropriate gate electrode pattern 6. When the addressing or interconnecting lines 43, 44 overlap, the thick island dielectric polymer 46 can be printed to provide electrical insulation.

Many of the devices formed as described above can be formed on one substrate and interconnected by a conductive layer. Devices can be formed on one level or on more than one level, some devices can be formed on top of other levels. The use of interconnection strips and via holes as described above results in a particularly compact circuit structure.

Techniques developed in the present invention for the fabrication of inkjet printing transistors, via holes, and interconnect lines can be used to fabricate integrated electronic circuits by inkjet printing. A prefabricated substrate containing heat of hydrophilic and hydrophobic surface regions can be used to define the channel length of the transistor and / or the width of the interconnect line. The substrate may also comprise a row of highly conductive metal interconnect lines. The combined use of ink jet printing and adherence of the continuous layer from the solution allows the heat of the transistor device to be partitioned into the custom channel width at the customized location. An integrated circuit is then fabricated by forming an electrical connection between a pair of transistors and a suitable interconnect using ink-jet printing of the via hole and the conductive line.

It is also possible that the prefabricated substrate already comprises one or more components of the transistor device. The substrate may comprise, for example, a row of completed inorganic transistor devices each having at least one exposed electrode. In this case, inkjet fabrication of the integrated circuit includes forming electrical connections between a pair of transistors and one or more levels of interconnect schemes using inkjet printing via holes, interconnect lines, and blocking pads (see FIG. 15D) .

The electronic circuitry includes, in addition to the transistor device, other active and passive circuit elements such as a display or memory element or a capacitive or resistive element.

Can be formed using a technique as described above to form a unit having a plurality of transistors and then to a specific subsequent use through solution based processing. As an example, a substrate having a plurality of transistors 50 of the type shown in FIG. 1A, 1B, or 1C, for example, in the form of a gate array may be formed on a plastic plate (see FIG. 22). Other devices such as diodes or capacitors may also be formed on the plastic plate. The plate is then coated with a suitable solvent (e.g., methanol) to form a via hole 52 and an ink containing a printing head for a suitable material (e.g., PEDOT) to form a conductive track 53 and fill the via hole. Jet printer. The ink jet printer is knowledgeable about the location and configuration of the transistors on the plate and is operable under the control of a suitably programmed computer. Then, by the combination of the via hole forming step and the interconnection step, the ink jet printer forms a circuit that performs predetermined electronic or logic functions by interconnecting the transistors in a predetermined manner. Thus, this technique allows logic specific circuits to be formed on a substrate even with small, inexpensive devices.

Applications of such circuitry include printing of active electronic tickets, baggage, and identification tags. The ticket or tag printing device is equipped with a plurality of non-configured units each containing a substrate supporting a plurality of transistors. The ticket printing device includes a computer capable of controlling the ink jet printer as described above and displaying the valid function of the ticket. When printing of a ticket is required, the printing device forms a substrate for a suitable electronic circuit by printing a via hole and / or a conductive material, whereby a transistor on the substrate is appropriately formed. Subsequently, the substrate may be covered with an adhesive plastic sheet, for example, and the electrical connection terminals 54 and 55 are left exposed. The ticket is then distributed. When the ticket is to be validated, an input value is applied to one or more input terminals and the output value at one or more output terminals is monitored to validate the function. The ticket is preferably printed on a flexible plastic substrate for convenient use.

User-defined circuits other than price attachments and tag attachments can also be manufactured in a similar manner. Circuit validation and reading may also be accomplished by remote meter reading using, for example, radio frequency radiation (Physics World, March 1999, p. 31).

The ability of the end user to define the circuit by merely ink jet printing the appropriate connections on a standard array provides significantly increased flexibility over the factory design circuitry.

The present invention is not limited to the above embodiments. Features of the present invention include all new and advanced features of the concepts described herein and all the new and advanced combinations of features described herein.

Applicant has noted that the present invention includes any feature or combination of features disclosed herein either implicitly or explicitly, or generally, without limiting the scope of any of the limitations set forth hereinabove do. In view of the above description, it is apparent to those skilled in the art that various modifications can be made within the scope of the present invention.

Claims (106)

Depositing a first material from a solution using a first solvent to form a first layer of the transistor; And Depositing a second material from a solution in a second solvent in which the first material is substantially insoluble on the first material while still allowing the first material to be soluble in the first solvent, &Lt; / RTI &gt; wherein the step of forming a transistor comprises forming a gate electrode. The method according to claim 1, Depositing a third material from a solution in a third solvent in which the second material is substantially insoluble on the second material while allowing the second material to remain soluble in the second solvent, RTI ID = 0.0 &gt; 1, &lt; / RTI &gt; 3. The method of claim 1 or 2, wherein one of the first and second solvents is a polar solvent and the other of the first and second solvents is a non-polar solvent. 4. The method of claim 1, wherein one of the first or second materials is a semiconductor material, and the other of the first or second materials is a dielectric material. 3. The method of claim 2, wherein the second material is a dielectric material, wherein one of the first and third materials is a semiconductor material, and the other of the first or third materials is a conductive material. 6. The method of any one of claims 1 to 5, wherein one of the first and second layers is a nonpolar polymer layer soluble in a nonpolar solvent, and the other of the first and second layers is a polar polymer layer soluble in a polar solvent &Lt; / RTI &gt; 7. The method of claim 6, wherein the interaction parameter (D) for the non-polar polymer and the polar polymer is 5 or greater. 7. The method of claim 6, wherein the interaction parameter (D) for the non-polar polymer and the polar polymer is greater than or equal to 10. 7. The method of claim 6, wherein the interaction parameter (D) for the non-polar polymer and the polar polymer is 15 or greater. 7. The method of claim 6, wherein the interaction parameter (D) for the polar polymer and the non-polar polymer is 5 or greater. 7. The method of claim 6, wherein the interaction parameter (D) for the polar polymer and the non-polar polymer is greater than or equal to 10. 7. The method of claim 6, wherein the interaction parameter (D) for the polar polymer and the non-polar polymer is 15 or greater. The method of claim 3, wherein one of the second and third solvents is a polar solvent and the other of the second and third solvents is a non-polar solvent. 3. The method of claim 2, wherein the second solvent is a solvent of a substantially polar nature including a polar and a non-polar group, wherein the first and third solvents are substantially polar solvents containing only polar groups. 15. The method of claim 14, wherein the second polymer layer is a generally polar polymer layer soluble in a solvent that is usually polar, wherein one of the first or third polymer layers is a non-polar polymer layer, Lt; RTI ID = 0.0 &gt; of a &lt; / RTI &gt; polar polymer layer. 15. The method of claim 14, wherein the interaction parameter (D) for the non-polar polymer and the generally polar solvent is 5 or greater. 15. The method of claim 14, wherein the interaction parameter (D) for the non-polar polymer and the generally polar solvent is greater than or equal to 10. 15. The method of claim 14, wherein the interaction parameter (D) for the non-polar polymer and the generally polar solvent is 15 or greater. 15. The method of claim 14 wherein the interaction parameter (D) for the polar polymer and the generally polar solvent is greater than or equal to 5. 15. The method of claim 14, wherein the interaction parameter (D) for the polar polymer and the generally polar solvent is greater than or equal to 10. 15. The method of claim 14, wherein the interaction parameter (D) for the polar polymer and the generally polar solvent is 15 or greater. 22. A process according to any one of claims 14 to 21, characterized in that the solvent, which is usually polar, is an alcohol. 22. A process according to any one of claims 14 to 21, characterized in that the solvent, which is usually polar, is acetate. 3. The method of claim 2, wherein the first layer is soluble in the non-polar solvent and the second layer is an isolating layer soluble in a solvent that is usually polar, including hydrophilic and hydrophobic groups. 25. The method of claim 24, wherein the third layer is soluble in the polar solvent. 25. The method of claim 24, wherein the third layer is soluble in the non-polar solvent. 27. The method according to any one of claims 24 to 26, wherein the second layer is an active layer of the transistor. 7. A method according to any one of the preceding claims, wherein one of said first and second layers is a source and / or drain electrode layer of a transistor, and the other of said first and second layers is a semiconductor layer of a transistor. 28. The method of any one of claims 1 to 27, wherein one of the first and second layers is a semiconductor layer of a transistor, and the other of the first and second layers is an insulating layer of a transistor. 30. The method of claim 28 or 29, wherein the semiconductor layer comprises a conjugated polymer. 30. The method of claim 28 or 29, wherein the semiconductor layer comprises a conjugated block copolymer. 31. The method of claim 28 or 29, wherein the semiconductor layer has a block copolymer having an electron affinity of at least 3.0 eV or 3.5 eV, wherein the block copolymer is a conjugated monomer having at least two covalent bonds A first block, and a second block of monomer units. 30. The method of claim 28 or 29, wherein the semiconductor layer has a block copolymer having an ionization potential in the range of 5.5 eV to 4.9 eV, the block copolymer having a conjugated monomer each of which is connected by at least two covalent bonds A first block, and a second block of monomer units. The method according to claim 15 or 33, wherein the first block of monomer units comprises one or more groups comprising a fluorine derivative, a phenylen derivative and an indenofluorene derivative, wherein the second group of monomer units Comprises one or more groups comprising a thiophene derivative, a triarylamine derivative and a benzothiadiazole derivative. 30. The method of claim 28 or 29, wherein the semiconductor polymer is F8T2 or TFB. 30. The method of claim 28 or 29, wherein the semiconductor layer comprises a liquid crystal conjugated polymer. 37. The method of claim 36, comprising heating the liquid crystal polymer to its liquid crystal state. 38. A method according to claim 36 or 37, comprising the step of uniaxially aligning said liquid crystal polymer. 39. The method of claim 38, wherein aligning the liquid crystal polymer comprises depositing the liquid crystal polymer on a layer having an ordered molecular structure. 40. The method of claim 39, wherein aligning the molecular structure of the layer is performed by mechanically rubbing the layer. 40. The method of claim 39, wherein aligning the molecular structure of the layer is performed by optically treating the layer. 28. The method of any of claims 28 to 24, wherein the semiconductor layer is optically transparent with a bandgap of at least 2.3 eV, preferably at least 2.5 eV. A method according to any one of claims 28 to 42, wherein the semiconductor layer has an ionization potential of 4.9 eV or greater. A method according to any one of claims 28 to 42, wherein the semiconductor layer has an ionization potential of at least 5.1 eV. The method according to any one of claims 28 to 42, wherein the semiconductor layer has an electron affinity of 3.0 eV or more. The method according to any one of claims 28 to 42, wherein the semiconductor layer has an electron affinity of 3.5 eV or more. 14. A device according to any one of claims 1 to 13, characterized in that one of the first and second layers is an insulating layer of the transistor, and the other of the first and second layers is a gate electrode layer of the transistor Way. 14. The semiconductor device according to any one of claims 2 to 13, wherein one of the first and third layers is an insulating layer of the transistor, the other one of the first and third layers is a gate electrode layer of the transistor, And the second layer is an isolated layer of the transistor. 49. The method of claim 48, wherein the isolation layer is a diffusion barrier layer. 50. The method of claim 49, wherein the diffusion barrier layer comprises a non-polar polymer. 50. The method of claim 49, wherein the diffusion barrier layer comprises a non-polar conjugated polymer. 50. The method of claim 49, wherein the diffusion barrier layer comprises a polyfluorine derivative. 53. The method of claim 52, wherein said polyfluorene derivative is F8, F8T2 or TFB. 54. The method according to any one of claims 48-53, wherein the isolation layer is a surface strained layer. 11. The method of any one of the preceding claims, comprising deforming the surface of the first layer prior to depositing the second layer. 56. The method of claim 55, wherein the surface deformation of the first layer is to provide a contact angle of less than or equal to 100 ^o for depositing the second material on the first layer. 56. The method of claim 55, wherein the surface deformation of the first layer is to provide a contact angle of less than or equal to 80 ^o for depositing the second material on the first layer. 56. The method of claim 55, wherein the surface deformation of the first layer is to provide a contact angle of less than or equal to 60 ^o for depositing the second material on the first layer. 62. The method according to any one of claims 55 to 58, wherein deforming the surface of the first layer comprises treating the surface of the first layer. 62. The method of any one of claims 55 to 58, wherein deforming the surface of the first layer comprises depositing a surface strain on the surface of the first layer. 61. The method of claim 60, wherein the surface strain material is deposited from a solution in a solvent that is usually polar. 7. A method according to any one of the preceding claims wherein the first layer is deposited on a substrate and the method comprises heating the substrate prior to depositing the second or third layer. 11. A method according to any one of the preceding claims, wherein at least one of said first, second and third layers is formed by ink jet printing. 64. The method of claim 63, wherein at least one of the source, drain, or gate electrode of the transistor is formed by the ink-jet printing. 11. A method according to any one of the preceding claims, wherein the transistor comprises a source, drain or gate electrode formed of a conductive polymer. 66. The method of claim 65, wherein the electrode is formed of an optically transparent conductive polymer. 66. The method of claim 65 or 66, wherein the conductive polymer comprises a polymeric counter ionic dopant. 11. A method according to any one of the preceding claims wherein the material of one of the first and second layers is PEDOT / PSS. 11. A method according to any one of the preceding claims, wherein the transistor comprises an insulating layer formed of a non-conjugated or partially conjugated polymer. 70. The method of claim 69, wherein the insulating polymer comprises hydrophilic and hydrophobic groups and is soluble in a solvent that is usually polar. 7. A method according to any one of the preceding claims, wherein the material of one of the first and second layers is PVP. A first active layer soluble in the first solvent; And And a second active layer adjacent to the first active layer, wherein the first active material is soluble in a second solvent that is substantially insoluble. 73. The transistor of claim 72, comprising a third active layer adjacent to the second active layer, wherein the second material is soluble in a substantially non-soluble third solvent. 73. The method of claim 72 or 73, wherein one of the first and second layers comprises a polar polymer soluble in a polar solvent and the other of the first and second layers is a nonpolar polymer soluble in a nonpolar solvent Lt; / RTI &gt; 74. The method of claim 74, depending on claim 73, wherein one of said second and third layers comprises a polar polymer soluble in a polar solvent and the other of said second and third layers is a nonpolar polymer soluble in a non- &Lt; / RTI &gt; 74. The transistor of claim 74, dependent on claim 73, wherein one of said solvents is an alcohol. 76. The device of any one of claims 72 to 76, wherein one of the first and second layers is a source and / or drain electrode layer of a transistor, and the other of the first and second layers is a semiconductor layer of a transistor Transistors. 76. The transistor according to any one of claims 72 to 76, wherein one of the first and second layers is a semiconductor layer of a transistor, and the other of the first and second layers is an insulator layer of a transistor. 78. The transistor according to claim 77 or 78, wherein the material forming the semiconductor layer is a polyfluorene derivative. 80. The transistor according to any one of claims 77 to 79, wherein the semiconductor layer has a bandgap of at least 2.3 eV, preferably at least 2.5 eV, and is optically transparent. 80. The transistor according to any one of claims 77 to 79, wherein the semiconductor layer has an ionization potential of 4.9 eV or more. 80. The transistor according to any one of claims 77 to 79, wherein the semiconductor layer has an ionization potential of at least 5.1 eV. 80. The device of any one of claims 77 to 79, wherein the semiconductor layer has a block copolymer having an electron affinity of at least 3.0 eV or 3.5 eV, wherein the block copolymer is linked by at least two covalent bonds, A first block of conjugated monomers, and a second block of monomer units. 80. The method of any one of claims 77-79, wherein the semiconductor layer has a block copolymer having an ionization potential in the range of 5.5 eV to 4.9 eV, the block copolymer being each linked by at least two covalent bonds A first block of conjugated monomers, and a second block of monomer units. 67. The method of claim 66 or 67, wherein the first block of monomer units comprises one or more groups comprising a fluorine derivative, a phenylene derivative, and an indenofluorine derivative, wherein the second group of monomer units Comprises one or more groups comprising a thiophene derivative, a triarylamine derivative and a benzothiadiazole derivative. 80. The transistor of claim 79, wherein the polyfluorine derivative is F8T2 or TFB. 87. The transistor according to any one of claims 77 to 86, wherein the semiconductor layer has an ionization potential of 4.9 eV or more. 87. The transistor according to any one of claims 77 to 86, wherein the semiconductor layer has an ionization potential of at least 5.1 eV. 76. The transistor of any one of claims 72 to 76, wherein one of the first and second layers is an insulating layer of the transistor, and the other of the first and second layers is a gate electrode layer of the transistor. . 76. The method of any one of claims 73 to 76, wherein one of the first and third layers is an insulating layer of the transistor, the other of the first and third layers is a gate electrode layer of the transistor, And the second layer is an isolation layer of the transistor. 91. The transistor of claim 90, wherein the isolation layer is a diffusion barrier layer. 92. The transistor of claim 91, wherein the diffusion barrier layer comprises a polyfluorene derivative. 92. The transistor of claim 92, wherein the polyfluorene derivative is F8T2 or TFB. 90. The transistor according to any one of claims 90 to 93, wherein the isolation layer is a surface strained layer. A transistor according to any one of claims 72 to 94, wherein the first or second layer is formed by inkjet printing. A transistor according to any one of claims 73 to 94, wherein said third layer is formed by said ink-jet printing. A method according to any one of claims 73 to 96, wherein one of the first, second and third layers is a source layer of the transistor, the other of the first, second and third layers is a drain layer of the transistor, And the other of the first, second and third layers is a gate layer of the transistor. 95. The transistor of claims 72-95, wherein the material of one of the first and second layers is PEDOT / PSS. 96. The transistor according to any one of claims 72 to 96, wherein the material of one of the first and second layers is PVP. 100. The transistor according to any one of claims 72 to 99, wherein the transistor is optically transparent. 100. The transistor according to any one of claims 72 to 100, wherein the transistor is a thin film transistor. 101. A logic circuit, display or memory device comprising the transistor claimed in any one of claims 72 to 101 above. 101. A logic circuit, display or memory device, comprising an active matrix array of a plurality of transistors claimed in any one of claims 72 to 101 above. 13. A display comprising a plurality of display elements, wherein at least one of the display elements is switched by an optically transparent thin film transistor. 105. The display of claim 104, wherein the transistor is located behind the display element. 108. The device of claim 105, wherein the display element comprises an optically active region switchable by the transistor, the transistor being electrically coupled to the optically active region by a conductive material located in a via hole formed through at least one layer of the transistor, To the display panel.