BRPI0016643B1 - METHOD FOR FORMING AN ELECTRONIC DEVICE ON A SUBSTRATE, AND LOGIC CIRCUIT, DISPLAY OR MEMORY DEVICE - Google Patents

Abstract

"method for forming on an substrate an electronic device, and logic circuit and display or memory device". a method for forming on an substrate an electronic device including an electrically conductive or semiconductor material in a plurality of regions, operating the device using current flow from a first region to a second region, the method comprising: forming a mixture by mixing the material with a liquid, forming on the substrate a confinement structure including a first zone in a first substrate area and a second zone in a second substrate area, the first zone having greater mixing repellency than the second zone, and a third zone in a third area of the substrate spaced from the second area by the first area, the first zone having greater mixing repellency than the third zone, and depositing the material on the substrate by applying the mixture on the substrate thereby the deposited material can be constrained by the relative repellency of the first zone to mutually spaced regions defining the first and second regions of the device and being electrically separated in their plane by the relative repellency of the first zone and being absent from the first substrate area so as to resist flow through the first zone of electric current between the mutually spaced regions of the device. deposited material.

Description

(54) Title: METHOD FOR FORMING AN ELECTRONIC DEVICE ON A SUBSTRATE AND LOGIC CIRCUIT, DISPLAY OR MEMORY DEVICE (73) Holder: SEIKO EPSON CORPORATION, Japanese Society. Address: 4-1, NISHIHINJUKU 2-CHOME, SHINJUKU-KU, TOKYO, JAPAN (JP); FLEXENABLE LIMITED. Address: 34 CAMBRIDGE SCIENCE PARK, MILTON ROAD, CAMBRIDGE, CAMBRIDGESHIRE CB4 0FX, UNITED KINGDOM (GB) (72) Inventor: HENNING SIRRINGHAUS; RICHARD HENRY FRIEND; TAKEO KAWASE

Validity Term: 10 (ten) years from 03/04/2018, observing the legal conditions

Issued on: 03/04/2018

Digitally signed by:

Júlio César Castelo Branco Reis Moreira

Patent Director

1/50 “METHOD FOR FORMING AN ELECTRONIC DEVICE ON A SUBSTRATE AND A LOGICAL CIRCUIT, DISPLAY OR MEMORY DEVICE”.

[001] The present invention relates to solution-processed devices and methods for forming such devices.

[002] Thin film transistors (TFTs) of semi-conductive conjugated polymer have recently become of interest for applications in logic circuits integrated in cheap plastic substrates (C. Drury et al., APL 73, 108 (1998)) and devices integrated optoelectronics and pixel transistor switches in high resolution active matrix display elements (H. Sirringhaus et al., Science 280, 1741 (1998), A. Dodabalapur et al. Appl. Phys. Lett. 73, 142 ( 1998)). In the test device configurations with a polymeric semiconductor and inorganic metal electrodes and dielectric gate layers, high performance TFTs have been demonstrated. Load-carrying mobilities of up to 0.1 cm2 / Vs and ON-OFF current ratios of 106 to 108 have been achieved, which are comparable to the performance of amorphous silicon TFTs (H. Sirringhaus et al., Advances in Solid State Physics 39 , 101 (1999)).

[003] Thin films of conjugated polymeric semiconductors can be formed by coating a solution of the polymer in an organic solvent on the substrate. The technology is therefore ideally suited for processing with a large, inexpensive area solution compatible with plastic and flexible substrates. In order to make full use of the potential cost and to make processing advantages easily available, it is desirable that all components of the devices, including semiconductor layers, dielectric layers as well as conductive electrodes and interconnections are deposited from the solution.

[004] For the manufacture of fully polymeric TFT devices and circuits, the following main problems must be overcome:

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- Structural integrity of the multiple layers: during a deposition of the solution of the subsequent semiconductor, insulating and / or conductive layers, the layers underneath must not be dissolved, or swelled by the solvent used for the deposition of the subsequent layers. Swelling occurs if the solvent is incorporated into the layer underneath, which usually results in a degradation of the properties of the layer.

- High resolution standardization of electrodes: The conductive layers need to be standardized to form well-defined interconnections and TFT channels with L <10 pm channel dimensions.

- For the manufacture of TFT circuits, vertical interconnection areas (via gaps) need to be formed to electrically connect the electrodes in different layers of the device.

[005] In WO 99/10939 A2, a method for making a

Fully polymeric TFT is demonstrated, which relies on converting the solution-processed layers of the device into an insoluble form before deposition of subsequent layers of the device. This overcomes the problems of dissolution and swelling of the layers underneath. However, this severely limits the choice of semiconductor materials, which can be used, to a small class and in some undesirable aspects of precursor polymers. Furthermore, a crosslinking of the insulating layer of the dielectric door makes it difficult to manufacture gaps through such dielectric layers, such that techniques, such as mechanical perforation, are used (WO 99/10939 A1).

[006] In accordance with an aspect of the present invention, a method is provided for forming on an substrate an electronic device, which includes an electrically conductive material, or semiconductor, in a plurality of regions, the operation of the device using current flow a first region to a second region, said method comprising: forming a mixture by mixing the material with a

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3/50 liquid; forming on said substrate a containment structure including a first zone in a first area of the substrate and a second zone in a second area of the substrate, the first zone having greater repellency for the mixture than the second zone, and a third zone in a third area of the substrate spaced from said second area by the first area, the first zone having greater repellency for the mixture than the third zone, and deposit the material on the substrate by applying the mixture on the substrate through which the deposited material can be confined by the relative repellency of said first zone to mutually spaced regions, defining said first and second regions of the device and being electrically separated in its plane through the relative repellency of the first zone and to be absent from the first substrate area in order to resist the flow through the first zone of the electric current between the mutually spaced regions of the mate deposited material.

[007] In accordance with another aspect of the present invention, a method is provided for forming on an substrate an electronic switching device, including an electrically conductive or semiconductor material in a plurality of regions, said method comprising: forming a mixture by mixing the material with a liquid; form a containment structure on the substrate including a first zone in a first area of the substrate and a second zone in a second area of the substrate, the first zone having greater repellency for mixing than the second zone, and a third zone in a third area of the substrate. substrate spaced from the first area by said second area, the third zone having greater repellency for mixing than the second zone; and depositing the material on the substrate by applying the mixture on the substrate; whereby the deposited material can be confined by the relative repellency of said first and third zones to said second zone.

[008] The width of said first area between the second and third

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4/50 areas is suitably less than 20 microns, and preferably less than 10 microns. The material formed in the said mutually spaced regions forms the source and drain electrodes of a transistor.

[009] The method, properly, comprises the step of depositing an additional material in the space between said regions that are mutually spaced. The additional material deposited in the space between said mutually spaced regions can form a channel of the transistor. The first material can be electrically conductive and said additional material can be semiconductor. The additional material can be a polymeric material. The additional material can be deposited from the solution, preferably a solution in a liquid that is not substantially repelled by the first zone.

[0010] The width of said second zone is suitably less than 20 microns. Said width of the second zone is suitably less than 10 microns. The material deposited in the second zone is suitable and electrically conductive. Such material adequately forms an interconnection. The material can form a transistor gate electrode. [0011] The width of the overlapping region between the transistor's door electrode and the source and drain electrodes, respectively, is preferably less than 20 microns.

[0012] The width of the overlapping region between the transistor's door electrode and the source and drain electrodes, respectively, is preferably less than 10 microns.

[0013] The substrate surface can be supplied by means of a self-assembled monolayer, and at least one of the first and second zones can be defined by standardization of the self-assembled monolayer.

[0014] The standardization step of the self-assembled monolayer can be performed by exposure to light through a shade mask.

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5/50 [0015] The standardization step of the self-assembled monolayer can be carried out by bringing the substrate into contact with a soft print. [0016] The first and second zones can be formed on the exposed surface of a layer deposited on a planar structural member.

[0017] The contact angle of the mixture in the first area is adequate and greater by 20 °, 40 °, or 80 °, than the contact angle of the mixture in the second area.

[0018] A method as disclosed is characterized by the fact that the substrate surface is provided by a self-assembled monolayer and at least one of said first and second zones is defined by the standardization of the self-assembled monolayer.

[0019] The said step of standardization of the self-assembled monolayer is adequately performed by exposure to light through a shade mask.

[0020] The standardization step of the self-assembled monolayer is carried out by bringing the substrate into contact with a soft print.

[0021] A method as disclosed is characterized by the fact that the substrate surface is provided by a non-polar material and at least one of the first and second zones is defined by the surface treatment of the non-polar polymer.

[0022] The non-polar material can be a polyimide.

[0023] The method may comprise the step of mechanically polishing, or otherwise superficially treating the polyimide in order to promote a molecular alignment of the polyimide.

[0024] The method can comprise the step of optically treating the polyimide to promote a molecular alignment of the polyimide.

[0025] Said surface treatment can be engraved by means of chemical attack. Said surface treatment can be plasma treatment.

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The plasma is preferably a carbon and / or oxygen tetrafluoride plasma.

[0026] The surface treatment may include exposure to ultraviolet light.

[0027] Preferably, the mentioned one of the zones is the second zone.

[0028] The first zone may induce, or even be able to induce, a molecular structure aligned with semiconductor or electrically conductive material.

[0029] The first zone is more preferably able to induce an alignment of polymeric chains in said electrically conductive or semiconductor polymer.

[0030] Said first zone is suitably capable of inducing the alignment of the chains of a polymeric material deposited on said first zone.

[0031] Said alignment is preferably in a direction that extends between the second and third zones.

[0032] Preferably, said chains are chains of said additional material.

[0033] Preferably, said electrically conductive or semiconductor polymer is deposited by droplet deposition.

[0034] Preferably, said electrically conductive or semiconductor polymer is deposited by inkjet printing.

[0035] Preferably, the width of at least one of the zones is less than the diameter of the droplet formed in said inkjet printing step.

[0036] Preferably, the boundary area between said first and second zones is optically distinct, and the method includes the step of optically detecting the boundary area between said first and second zones and locating the

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7/50 inkjet printing mechanism or apparatus relative to the substrate depending on that detection.

[0037] The first material can be a polymer, preferably a conjugated polymer. The first material can be an inorganic particulate material susceptible to suspension in said liquid.

[0038] In accordance with a further aspect of the present invention, a logic circuit, display or memory device provided by the method described above is provided.

[0039] According to another aspect of the present invention, a logic circuit, display or memory device is provided, which comprises an active matrix arrangement of a plurality of transistors formed by said method described above.

[0040] The present invention will now be described by way of example, with reference to the accompanying drawings, in which:

Figure 1 shows device configurations other than fully polymeric TFTs, processed by solution;

Figure 2 shows the transfer characteristics of polymeric TFTs according to Fig. 1c, with an active layer of F8T2, a PVP insulating layer and a PEDOT / PSS electrode;

Figure 3 shows the transfer characteristics of polymeric TFTs according to Fig. Lc, with an active layer of F8T2, a PVP insulating layer and a PEDOT / PSS electrode deposited with the sample kept at room temperature (at ) and at approximately 50 ° C (b);

Figure 4 shows the output (a) and transfer characteristics (b) of a fully polymeric F8T2 TFT, which contains an F8 diffusion barrier and a PVP surface modification layer like the one in Figure 1 (a);

Figure 5 shows the transfer characteristics of TFTs

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8/50 fully polymeric F8T2 as in Figure 1 (a), with a diffusion barrier of TFB (a) and polystyrene (b), and a PVP surface modification layer;

Figure 6 shows an optical micrograph of a fully pomeric TFT according to Figure 1 (a), with an active layer of F8T2 and source-drain electrodes printed directly on an uncovered glass substrate;

Figure 7 shows the fabrication of TFTs with small channel dimension and small overlap capacitance through the standardization of the substrate surface in hydrophobic and hydrophilic areas;

Figure 8 shows optical micrographs of the transistor channel region with L = 20 pm (a) and L = 5 pm (b), after a UP deposition of PEDOT / PSS source / drain electrodes in the vicinity of a barrier hydrophobic pobimide;

Figure 9 shows the optical micrographs taken during the deposition of ink droplets in the vicinity of a pobimide barrier;

Figures 10 and 11 show outputs and transfer characteristics of transistors formed as in Figure 7 (c) and having channel dimensions L = 20 pm and 7 pm, respectively;

Figure 12 shows a schematic diagram of (a) Dektak profileometry and optical micrographs (b) of the process of forming via gaps by the successive deposition of methanol droplets on a 1.3 pm thick PVP port dielectric layer and (c ) the dependence of the outer and inner diameter of the gap via the inkjet droplet diameter, as well as the thickness of the PVP layer;

Figure 13 shows current-voltage characteristics through a gap path with a bottom PEDOT electrode and a top electrode;

Figure 14 illustrates different processes for fabricating gaps;

Figure 15 shows gaps viapacations, such as inverters

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Logic 9/50 (depletion load (a), enhancement load (b) and resistance load (c)), and multi-level interconnection schemes (d);

Figure 16 shows the characteristics of the enhancement load inverter circuits as in Figure 1 (a), manufactured with fully pomeric TFTs printed with different ratios of the W / L dimensions of the two transistors;

Figure 17 shows an alternative door device configuration;

Figure 18 shows a schematic drawing of an active matrix pixel in which the display or memory element is controlled by a voltage or voltage (a) or a current (b);

Figure 19 shows possible pixel configurations of an active matrix;

Figure 20 shows a polarized optical absorption of a packed F8T2 TFT;

Figure 21 shows (a) such pomeric TFTs with a standardized active layer island manufactured by printing semiconductor and dielectric layers and (b) the region of overlap between the conductive interconnections separated by a printed insulation island; and

Figure 22 shows an array of transistor devices connected by a network of interconnections to UP for the manufacture of user-defined electronic circuits.

[0041] The preferred manufacturing methods described here allow the manufacture of a thin-film transistor (TFT) processed by solution, totally organic, in which none of the layers is converted or cross-linked to an insoluble form. Each layer of such a device can remain in a form that is soluble in the solvent from which it was deposited. As will be described in more detail below, this allows for a simple way to manufacture via gaps through dielectric insulating layers with

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10/50 base on focal solvent deposition.

[0042] Such a device may comprise, for example, one or more of the following components:

- source-drain and conductor electrodes and standardized interconnections.

- a semiconductor layer with a load-carrying mobility that exceeds 0.01 cm ² / Vs and a high LIGADESLIGA current switching ratio that exceeds 10 ⁴ .

- a thin door insulating layer.

- a diffusion barrier layer that protects the semiconductor layer and the insulating layer against unintentional doping by impurities and ionic diffusion.

- a surface modification layer that allows the high resolution standardization of the door electrode by printing techniques.

- via gaps for interconnections through said dielectric layers.

[0043] However, it will be assessed that the methods described here are not limited to the manufacture of devices having all the characteristics presented above.

[0044] The manufacture of a first illustrative device will now be described with reference to figure 1. The device of figure 1 is a thin film field effect (TFT) transistor configured to have a top gate structure.

[0045] On top of a clean 7059 glass substrate 1 source-drain electrodes 2, 3 and interconnecting lines between the electrodes and contact blocks (not shown) are deposited by inkjet printing a polymer solution conductor of polyethylene dioxythiophene / polystyrene sulfonate (PEDOT (0.5% by weight) / PSS (0.8% by weight)) in water. Other solvents, such as: methanol, ethanol, isopropanol, or acetone, can be

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11/50 added to affect the surface tension, viscosity and wetting properties of the paint. PEDOT / PSS is commercially obtained from Bayer (available as “Baytron P”). The IJP printer is a piezoelectric type. It is equipped with a precision two-dimensional translation stage and another microscope stage that facilitates the matching of the subsequently printed standards in relation to each other. The UP head is activated with a voltage pulse. Impulse conditions suitable for ejecting droplets with a typical content of 0.4 ng per droplet are obtained with a pulse height of 20V, a rise time of 10 ps and a drop time of 10 ps. After drying on the glass substrate they produce an o

PEDOT point with a typical diameter of 50 pm and a typical thickness of 500 A. [0046] IJP of source-drain electrodes is performed by air.

Subsequently, the samples are transferred to an inert atmosphere glove box system. The substrates are then dried by rotation in the organic solvent that will be used later for the deposition of the active semiconductor layer, such as mixed xylenes in the case of pobfluorene polymers. They are then annealed for 20 minutes at 200 ° C in an inert nitrogen atmosphere to remove residual solvent and other volatile species on the PEDOT / PSS electrodes. Then, a 200 to 1000 µm thick film of the active semipolymer conductor 4 is deposited by rotation coating. Various semi-polymeric conductors have been used such as regioregular poly-3-hexylthiaphen (P3HT) and pobfluorene copolymers such as pob-9,9'-dioctylfluorene-co-dithiophene (F8T2). The F8T2 is a preferred choice since it exhibits good air stability during deposition of the door electrode in the air. A solution of 5 to 10 mg / ml of F8T2 in mixed, anhydrous xylenes (purchased from Romil) is coated by rotation at 1500 to 2000 rpm. In the case of P3HT a solution of 1% by weight in mixed xylene was used. The PEDOT electrodes below are insoluble in an organic non-polar solvent such as xylene. The films are then dried

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12/50 per revolution in the solvent that will be used later for the deposition of the insulating layer port 5, such as isopropanol or methanol.

[0047] A subsequent annealing step can then be re-made to enhance the charge-carrying properties of the semiconductor polymer. For polymers that exhibit a liquid crystalline phase at elevated temperatures, annealing at a temperature above the liquid-crystalline transition results in the orientation of the pomeric chains parallel to each other. In the case of F8T2, annealing is carried out at 275 to 285 ° C for 5 to 20 minutes under an inert N2 atmosphere. The samples are then quickly cooled to room temperature until they freeze in the chain orientation and produce an amorphous glass. If the samples are prepared on flat glass substrates without an ablution layer, the polymer adopts a multiple domain configuration in which several liquid-crystalline domains with random orientation are located within the TFT channel. Transistor devices in which the F8T2 is prepared in a glassy state by cooling from a liquid-crystalline phase exhibits mobilities of the order of 5.10-3 cm2 / Vs, which are in more than an order of magnitude higher than those mobility measured on devices with F8T2 films also rotated. Equally deposited devices also exhibit higher V0 connection voltages. This is attributed to a lower density of electronic trap states located in the glass phase compared to the equally deposited phase, which is partially crystalline.

[0048] Additional mobility improvements in typically a factor of 3 to 5 can be obtained if the polymer is prepared in a monodomain state with the uniaxial alignment of the pomeric chains parallel to the transistor channel. This can be achieved by coating the glassy substrate with a suitable alignment layer, such as a mechanically rubbed polyimide layer (9 in figure 1 (b)). In the state of

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13/50 monodomain the polymeric chains are aligned uniaxially parallel to the friction direction of the polyimide layer underneath. This results in an additional enhancement of load-carrying mobility in devices where the TFT channel is parallel to the chain alignment direction. Such a process is described in more detail in our copending UK patent application number 9914489.1.

[0049] After deposition of the semiconductor layer, the insulating layer port 5 is deposited by spin coating of a polyhydroxystyrene solution (also called polyvinylphenol (PVP)) from a polar solvent in which the semiconductor polymer that is underneath do not be soluble. A preferred choice of solvents are alcohols such as methanol, 2-propanol or butanol, in which non-polar polymers such as F8T2 have exceptionally low solubility and do not swell. The thickness of the insulating door layer is between 300 nm (solution concentration 30 mg / ml) and 1.3 μιη (solution concentration 100 mg / ml). Other insulating polymers and solvents that satisfy solubility requirements such as polyvinyl alcohol (PVA) in water or polymethyl methacrylate (PMMA) in butyl acetate or propylene glycol methyl ether acetate can also be used.

[0050] The electrode port 6 is then deposited on the insulating layer port. The door electrode layer can be deposited directly on the insulating door layer (see figure 1 (c)), or it can be one or more intermediate layers (see figure 1 (a) and figure 1 (b)), for example, for surface modification, diffusion barrier or for process reasons such as solvent compatibility.

[0051] To form the simplest device in figure 1 (c) a PEDOT / PSS 6 door can be printed directly on top of the PVP insulating layer 5. The substrate is transferred to the UP station once again in the air where a PEDOT / PSS port electrode pattern is printed on

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14/50 from an aqueous solution. The PVP door insulating layer underneath has a low solubility in water such that the integrity of the door dielectric is preserved during the printing of the PEDOT / PSS door electrode. Although PVP contains a high density of polar hydroxyl groups, its solubility in water is low because of the main chain like that of extremely non-polar pobestyrene. Similarly, PMMA is insoluble in water. Figure 2 shows the transfer characteristics of a TFT to UP with a semiconductor layer of F8T2, an insulating layer of PVP port and source-drain electrodes and PEDOT / PSS to IJP port. The characteristics of the device are measured under a nitrogen atmosphere. Consecutive measurements are shown with increasing gate voltage (ascending triangles) and decreasing voltage (descending triangles), respectively. The features are part of devices manufactured from a freshly prepared batch (a) and a one year old batch (b) of PEDOT / PSS (Baytron P). The action of the transistor can be clearly observed, however, the devices exhibit an unusual low behavior with positive threshold voltages VO> 10V, whereas the reference devices manufactured with source-drain electrodes and evaporated gold gate were found to exhibit behavior normally off (VO <0). In devices formed from the “old” batch of PEDOT (figure 2 (b)) large hysteresis effects have been observed that are attributed to the high concentration of mobile ionic impurities (see below). If the movement is initiated in deep exhaustion (Vg = + 40V), the transistor bga at VfO ~ + 20V (upward triangles). However, in the reverse scan (descending triangles), the transistor dehubs only at VrO> + 35V.

[0052] The normally linked behavior and hysteresis effects are likely to be caused by the diffusion of ionic species in one of the layers of the device. The unusually large positive VO values suggest that the ion is negative. A positive species would be

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15/50 expected to compensate for some of the moving load in the accumulation layer and lead to a change in VO to more negative values. To identify the origin of these ionic species devices were manufactured in which the PEDOT electrode at the top port UP was replaced by an evaporated gold electrode while the other layers and the PEDOT source / drain electrodes were manufactured as described above. It was found that in this configuration the devices are normally turned off and exhibit stable threshold voltages. This implies that the doping and hysteresis effects in the fully polymeric device are related to the deposition of the conductive polymer top port electrode solution and the possible diffusion of ionic, mobile impurities from the PEDOT solution / film in the layers underneath the device.

[0053] It was found to be possible to control the threshold voltage value and reduce the amount of hysteresis by depositing the port electrode on a heated substrate. This reduces the drying time of the droplet on the substrate. Fig. 3 (b) shows the transfer characteristics of a TFT device to which the substrate was heated to a temperature of 50 ° C during the deposition of the port electrode. It can be seen that the hysteresis effect is much less than for door deposition at room temperature (Fig. 3b) and that VO has a relatively small positive value of 6V. By controlling the deposition temperature, the threshold voltage can be adjusted in a range of VO = 1 to 20V.

[0054] Devices with door electrodes deposited directly on the PVP layer as in figure 1 (c) are of the type of exhaustion. This normally connected behavior is useful for logic circuits of the exhaustion type such as the simple inverter load logic inverter (figure 1.4 (a)).

[0055] To make TFTs normally switched off, the semiconductor doping type during the deposition of the door can be enhanced

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16/50 prevented by the incorporation of a diffusion barrier layer. In the device of figures 1 (a) and (b) a thin layer 7 of a non-polar polymer is deposited on top of the PVP insulating layer prior to deposition of the conductive polymer electrode. This layer is believed to act as a diffusion barrier blocking the diffusion of ionic species through the moderately polar PVP isolator. PVP contains a high density of polar hydroxyl groups that tend to enhance ion conductivity and diffusivity across the film. Several non-polar polymers have been used such as poly-9,9'-dioctylfluorene (F8), polystyrene (PS), poly (9,9'-dioctyl-fluorene-co-N- (4-butylphenyl) diphenylamine) (TFB) or F8T2. Such thin films of these polymers of the order of 50 to 100 nm can be deposited on the surface of the PVP insulating layer from a solution in an organic non-polar solvent such as xylene, in which PVP is insoluble.

[0056] Direct printing of PEDOT / PSS from a polar solution in water on top of the non-polar diffusion barrier layer or on top of a moderately polar polymer such as PMMA has been found to be problematic because of poor wetting and angles large contact points. To address this, a surface modification layer 8 is deposited on top of the non-polar polymer. This layer provides a hydrophilic rather than hydrophobic surface on which PEDOT / PSS can be more easily formed. This allows for high-resolution printing facilities of the door electrode pattern. To form the surface modification layer, a thin layer of PVP can be deposited from the isopropanol solution, in which the diffusion barrier layer underneath is insoluble. The PVP layer thickness is preferably less than 50 nm. PEDOT / PSS high-resolution printing is possible on the PVP surface. Alternative surface modification layers can be used. These include thin layers of

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17/50 surfactants such as soap or polymers containing a hydrophobic or hydrophobic functional group. These molecules can tend to separate from phase with hydrophobic and hydrophilic groups being attracted against the interface with the non-polar polymer underneath and the free surface, respectively. Another possibility is the brief exposure of the surface of the non-polar diffusion barrier to a soft 02 plasma that takes over the hydrophilic surface. An appropriate plasma treatment that does not degrade the performance of the TFT device is exposure to a 13.5 MHz 02 plasma with a 50 W energy for 12 s.

[0057] A surface modification layer on top of the non-polar diffusion barrier may not be required if the port electrode is printed from a solvent that is less polar than water such as an alcohol-containing formulation (isopropanol, methanol , etc.).

[0058] The integrity of the layer sequence relies on alternating deposition of polymeric materials from polar and non-polar solvents. It is desirable that the solubility of a first layer in the solvent used for the deposition of a second layer is less than 0.1% by weight by volume, preferably less than 0.01% by weight by volume. [0059] The criterion for solvent compatibility can be quantified using Hildebrand's solubility parameters by which the degree of polarity can be quantified (D. W. van Krevelen, Properties of polymers, Elsevier, Amsterdam (1990)). The solubility behavior of each polymer (solvent) is described by three characteristic parameters ôd, δρ, ôh, which characterize the degree of dispersive interactions, polar interaction and hydrogen interactions between the polymer (solvent) molecules in the liquid state. The values for these parameters can be calculated if the molecular structure is known by adding the contributions of the different functional groups of the polymer. These are tabulated for the most common polymers. Often δρ and ôd are combined for δν2 = Ôd2 + δρ2.

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18/50 [0060] The free energy of the mixture is given by AGm = AHm - T. ASm, where ASm> 0 is the entropy of the mixture and AHm = V. <|) p. <|) S. ((ÔvP- ôvS) 2 + (ôhPôhS) 2). (V: volume; φρ and φβ: polymer volume fraction (P) / solvent (S) in said mixture). From this, it is expected that a polymer (P) will be the most soluble in a solvent (S) the smaller the AHm, that is, the D = ((5vP-ôvS) 2 + (5hP-ôhS) 2) l / 2 . As an approximate criterion, if the interaction parameter D is less than approximately 5 the polymer is soluble in the solvent. If D is between 5 and 10, swelling is often observed. If D is greater than 10, the polymer is substantially insoluble in the solvent, with no swelling occurring.

[0061] In order to obtain sufficiently abrupt interfaces in a solution-processed TFT device it is therefore desirable that the respective D values for each of the polymeric layers and the solvent of the next layer should be greater than approximately 10. This is particularly important for the polymeric semiconductor layer and the solvent of the port dielectric. In the case of F8T2 and isopropanol (butyl acetate) we estimate that D is approximately 16 (12).

[0062] For some device configurations the entire multilayer structure can be constructed by an alternating sequence of polymers that contain mainly polar groups and are soluble in a highly polar solvent such as water and polymers that contain only a few or do not no polar group and are soluble in a non-polar solvent, such as xylene. In this case the interaction parameter D is large because of the differences in δΡ for the polymeric layer and the solvent for the next layer. An example would be a transistor device comprising a highly polar PEDOT / PSS source-drain electrode, a non-polar semiconductor layer such as F8T2, a highly polar gate dielectric layer such as a polyvinyl alcohol deposited from aqueous solution, a barrier layer

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19/50 TFB non-polar diffusion which also acts as a buffer layer to facilitate the deposition of the layer sequence and a PEDOT / PSS port electrode.

[0063] However, it is often convenient to have a non-polar semiconductor layer and a polar gate electrode layer separated by a single dielectric layer. This layer sequence is also possible using a moderately polar polymeric layer deposited from a moderately polar solvent interspersed between the highly polar and the non-polar polymeric layer. A moderately polar polymer is a polymer that contains both polar and non-polar groups and is substantially insoluble in a highly polar solvent. Similarly, a moderately polar solvent contains both polar and non-polar groups, but does not substantially dissolve a non-polar polymer. In terms of the solubility parameters a moderately polar solvent can be defined as one where the solubility parameter ôh is enormously different from that of the polymer underneath. In this case, swelling can be avoided (large D) even if the polar solubility parameter δρ (δν) of the solvent may be similar to that of the polymeric layer underneath. The moderately polar polymer can contain a specific functional group such as a hydroxyl group that makes it soluble in a solvent containing a functional group that is attracted to the functional group of the polymer. This attraction may be a hydrogen bonding interaction. This polymer functionality can be used to enhance its solubility in a moderately polar solvent and decrease its solubility in a polar solvent. An example of a moderately polar polymer is a PVP gate dielectric layer sandwiched between a non-polar semiconductor layer and a PEDOT / PSS gate electrode layer (Fig. Lc). An example of a moderately polar solvent is an alkyl alcohol such as IPA (ôh = 8; F8T2: ôh ~ 0).

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20/50 [0064] Figure 4 shows the output (a) and transfer characteristics (b) of a fully polymeric IJP F8T2 TFT with a PVP insulating layer, an F8 diffusion barrier layer and a modification layer of the PVP surface, as shown in figure l (a) (L = 50 μιη). The device exhibits almost ideal transistor action normally off, clean with connection to V0 <0V. The threshold change voltage between increasing voltage movements (upward triangles) and decreasing voltage (downward triangles) is <1 V. The characteristics of the device are very similar to those of standard devices manufactured under inert atmosphere conditions with source-drain and gate electrodes of Au. The field-mobility effect is in the range of 0.005 to 0.01 cm2 / Vs and the ON-OFF current ratio measured between Vg = O and -60V is in the range of 104 to 106.

[0065] The devices were manufactured with a wide range of non-polar diffusion barrier layers, such as F8, TFB (figure 5 (a) shows transfer characteristics), PS (figure 5 (b) shows transfer characteristics ) and F8T2. In each case, normally clean off behavior and small hysteresis effects and threshold voltage changes were observed, which were of the same order of magnitude as those of the reference devices with gold source electrodes. This supported the interpretation that the insertion of a non-polar polymer under the door electrode blocks the diffusion of ionic impurities during and after the deposition of the solution of the door insulating layer. This has been found to result in reproducible TFT threshold voltages and good operating stability.

[0066] Normally disconnected devices containing a diffusion barrier are preferred compared to the depletion-type device described above, since the latter is expected to exhibit better long-term threshold voltage stability and better life time due to

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21/50 suppression of ionic diffusion.

[0067] For the semiconductor layer any conjugated polymeric or oligomeric material processable by solution that exhibits adequate field effect mobilities that exceed 10-3 cm2 / Vs, preferably that exceed 10-2 cm2 / Vs, can be used. Suitable materials are reviewed for example in Η. E. Katz, J. Mater. Chem. 7, 369 (1997) or Z. Bao, Advanced Materials 12, 227 (2000).

[0068] One of the important requirements for manufacturing printed TFTs with good stability and high ON-OFF current ratio is the good stability of the semiconductor material against unintentional doping by atmospheric oxygen and water during the processing and printing steps. The printed TFTs were manufactured with a strip of semiconductor polymers as the active semiconductor layer, such as F8T2 (see above) or regioregular PVT deposited from mixed xylene solution. In the case of P3HT TFTs prepared in the test device configurations under an inert atmosphere, the field effect mobility of 0.05 to 0.1 cm2 / Vs is somewhat higher than in the case of the F8T2. However, the regioregular P3HT is unstable against doping by oxygen and / or water, resulting in an increase in the conductivity of the film during the stages of air printing and a deficient ON-OFF current ratio. This is related to the relatively low ionization potential of P3HT, Ip ~

4.9 eV. High ON-OFF current ratios of> 106 have been demonstrated for ο P3HT, but this requires a reductive de-doping step after deposition, such as exposure to hydrazine vapor (H. Sirringhaus et al., Advances in Solid State Physics 39 , 101 (1999)). However, in the UP TFTs described above, this reductive post-processing step cannot be performed since it could also result in the PEDOT electrode de-doping and significantly reduce its conductivity. Therefore, to achieve current switching ratios

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22/50 high it is important that a polymeric semiconductor is used with good stability against unintentional doping by oxygen or water.

[0069] A preferred class of materials for achieving good environmental stability and high mobility are rigid rod AB block copolymers containing a regular ordered sequence of A and B blocks. Suitable A blocks are structurally well defined, ladder-like portions with a high bandwidth, which have high ionization potentials greater than 5.5 eV as a homopolymer and good environmental stability. Examples of suitable A blocks are fluorene derivatives (US 5,777,070), indenofluorene derivatives (S. Setayesh, Macromolecules 33, 2016 (2000)), phenylene or phenylene derivatives of the ladder type (J. Grimme et al., Adv. Mat. 7, 292 (1995)). Suitable B blocks are portions that carry a gap with lower band intervals that contain heteroatoms such as sulfur or nitrogen and as a homopolymer have ionization potentials less than 5.5 eV. Examples of gap-carrying B blocks are thiophene derivatives or triarylamine derivatives. The effect of block B is to decrease the ionization potential of the block copolymer. The ionization potential of the block copolymer is preferably in the range of 4.9 eV <Ip 5.5 eV. Examples of such copolymers are F8T2 (ionization potential 5.5 eV) or TFB (US 5,777,070).

[0070] Other suitable gap-carrying polymers are homopolymers of polythiophene derivatives with an ionization potential greater than 5 eV, such as polythiophenes with alkoxy or fluorinated side chains (R. D. McCullough, Advanced Materials 10, 93 (1998)).

[0071] Instead of semiconductor polymers that carry a gap, materials that transport soluble electrons can also be used. These require a high electron affinity, greater than 3 eV, preferably greater than 3.5 eV, to prevent impurities

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23/50 residual atmospheric elements such as oxygen act as loading traps. Suitable materials can include small molecule electron-carrying semiconductors, processable in solution (Η. E. Katz et al., Nature 404, 478 (2000)) or polythiophene derivatives with electron-deficient fluorinated side chains. Type AB block copolymers with a ladder type A block, structurally well defined with a high ionization potential greater than 5.5 eV and an electron carrier B block that increases the electron affinity of the copolymer to a more higher than 3 eV, preferably higher than 3.5 eV are also suitable. Block A examples are fluorene derivatives (US 5,777,070), indenofluorene derivatives (S. Setayesh, Macromolecules 33, 2016 (2000)), phenylene or ladder-type phenylene derivatives (J. Grimme et al., Adv Mat. 7, 292 (1995)). Examples of electron-carrying B blocks are derived from benzothiadiazole (US 5,777,070), perylene derivatives, naphthalenetetracarboxylic diimide derivatives (Η. E. Katz et al., Nature 404, 478 (2000)) or fluorinated thiophene derivatives .

[0072] For the fast operation of logic circuits the length of the L channel of the transistors and the overlap between the source / drain and the gate must be as small as possible, which are typically a few microns. The most critical dimension is L, because the operating speed of a transistor circuit is approximately proportional to L-2. This is particularly important for semiconductor layers with relatively low mobility.

[0073] Such high resolution standardization cannot be achieved with current inkjet printing technology, which is limited to characteristic sizes from 10 to 20 μιη even with UP technology in the state of the art (figure 6). If faster operation and denser packaging of features is required then a technique that allows for finer feature resolution should be used. The technique described below makes use of

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24/50 of ink surface interactions to confine inkjet droplets to the surface of a substrate. This technique can be used to obtain much shorter channel lengths than can be achieved by conventional inkjet printing.

[0074] This containment technique can be used to allow the deposition of fine resolution of a material deposited on a substrate. The substrate surface is first treated so as to take selected parts of it relatively attractive and relatively repellent to the material to be deposited. For example, the substrate can be pre-patterned to be partially hydrophobic in some areas and partially hydrophilic in other areas. With the pre-standardization step resumed in high resolution and / or accurate registration the subsequent deposition can be precisely defined.

[0075] A pre-standardized rehabilitation form is illustrated in figure 7. Figure 7 illustrates the formation of a device of the type shown in figure 1 (c) but with an especially thin L channel length. Similar parts are numbered as for figure 1 (c). Figure 7 (a) illustrates a method for making a pre-patterned substrate. Figure 7 (b) illustrates the printing and confinement of the ink on a pre-patterned substrate.

[0076] Before deposition of the source-drain electrodes 2, a thin layer of pobimide 10 is formed on the glass plate 1. This layer of pobimide is finely patterned to remove it in places where the source-drain electrodes should be trained. The removal step can be done by a photobtographic process to facilitate the definition of fine features and / or accurate registration. In an example of such a process, the pobimide can be covered with a layer of photoprotector 11. The photoprotector can be photohtographically patterned to remove it in the places where the pobimide is to be removed. Then the polyimide is removed by a process to which the photoprotector is resistant. Then the photoprotector can be

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25/50 removed to make the polyimide precisely standardized. Polyimide is selected because it is relatively hydrophobic, whereas the glassy substrate is relatively hydrophilic. In the next step, PEDOT material to form the source-drain electrodes is deposited by inkjet printing on the hydrophilic substrate areas 12. When the ink droplets that spread over the glass substrate areas reach the limit of one hydrophobic polyimide region 10 the ink is repelled and prevented from flowing on hydrophobic surface areas. Through this confinement effect, the ink is deposited only in the hydrophilic surface areas and high resolution patterns with small intervals and transistor channel lengths of less than 10 μιη can be defined (figure 7 (b)).

[0077] An example of a process by which the polyimide can be removed or which can be used to enhance the relative surface effects after removing the polyimide, is illustrated in figure 7 (a). The polyimide layer 10 and the photoprotector 11 are exposed to an oxygen plasma. Oxygen plasma records the thin polyimide layer (500 Å) faster than the thick photoprotective layer (1.5 μιη). The exposed exposed glass surface 12 in the area of the source-drain electrodes is made very hydrophilic by exposure to a 02 plasma before removal of the photoprotector. Note that during the removal of the polyimide, the surface of the polyimide is protected by the photoprotector and remains hydrophobic.

[0078] If required, the polyimide surface can be made even more hydrophobic by additional exposure to a CF4 plasma. CF4 plasma fluorine the surface of the polyimide, but does not interact with the hydrophilic glass substrate. This additional plasma treatment can be performed before removal of the photoprotector, in which case only the side walls of the polyimide pattern 10 become fluorinated or after removal of the protector.

[0079] The contact angle of PEDOT / PSS in water on glass 7059

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26/50 plasma treated with 02 is Ovidro ~ 20 ° compared to a contact angle of ΘΡΙ ~ 70 ° to 80 ° on the polyimide surface. The contact angle of PEDOT / PSS in water in the fluorinated polyimide is 120 °.

[0080] When PEDOT / PSS is deposited from an aqueous solution on the pre-standardized polyimide layer as described, the PEDOT / PSS paint is confined to the source-drain electrode areas even if the length of the L channel is just a few microns (figure 7 (b)).

[0081] To facilitate the confinement of the ink droplets the kinetic energy of the ink droplets is kept as small as possible. The larger the size of the droplets, the greater the kinetic energy and the greater the likelihood that the droplets that spread will 'ignore' the hydrophilic confinement structure and overflow over neighboring hydrophilic regions.

[0082] Preferably the deposition of the ink droplets 13 is on the areas of hydrophilic substrate 12 at a distance d between the center of the droplet and the polyimide limit. On the one hand, it needs to be small enough so that the limit is reached by the spreading ink and the PEDOT film extends all the way to the polyimide limit. On the other hand, d needs to be large enough so that the rapidly spreading paint does not “overflow” on hydrophobic surface areas. This could increase the risk of PEDOT deposition at the top of the polyimide region 10 that defines the TFT channel and can give rise to short circuits between the source and drain electrodes. For PEDOT droplets with a solids content of 0.4 ng deposited with a lateral intensity of 12.5 Nm between two successive droplets on 7059 glass treated with 02 plasma, a value of d ~ 30 to 40 μιη was considered adequate. The optimal d value depends on the wetting properties on the surface as well as the intensity of deposition, which is the lateral distance between droplets subsequently deposited, the frequency with which the droplets are deposited and the time of

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27/50 drying the solution.

[0083] The hydrophobic confinement layer to define the length of the transistor channel can also provide a second functionality. This can be used as an alignment pattern for the subsequent deposition of the semiconductor polymer in the transistor channel. The polyimide layer 10 can be mechanically rubbed or photoaligned and can then be used as an alignment layer 9 (figure 1 (b)) to provide mono-domain alignment of a liquid-crystalline semiconductor polymer 4.

[0084] The electrode port 6 can be similarly confined by a standardized layer 14 formed on top of the insulating layer port 5 which provides attractive and repellent surface areas for the solution from which the port electrode is deposited. The standardized layer 6 can be aligned with respect to the source-drain pattern to minimize the area of overlap between source / drain electrodes and port (figure 7 (c)).

[0085] Materials other than polyimide can be used for the pre-patterned layer. Precise pre-standard techniques other than photolithography can be used.

[0086] Figure 8 demonstrates the ability of a relatively hydrophobic and hydrophilic layer structure to confine liquid "Ink" deposited by inkjet printing. Figure 8 shows optical micrographs of substrates including thin strips of polyimide 10 that have been treated as described above to be relatively hydrophobic and larger regions of the uncovered glass substrate 12 that have been treated as described above to be relatively hydrophilic. PEDOT material for the source and drain electrodes was deposited by inkjet printing a series of droplets that run on lines 2 and 3 next to the strips

10. Although the sandblasted material shows low contrast, it can be seen from the abruptly finished shape of the surfaces of the

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28/50 ends 2 and 3 of the deposited material that the deposited material was confined by the strips 10 just below a strip thickness of L = 5 pm. [0087] Figure 9 shows photographs of the inkjet deposition process in the vicinity of a strip of polyimide 10. The images were taken with a strobe camera mounted under the transparent substrate. The edges of the polyimide pattern 10 can be seen as white nails. The ink droplets 21 are exposed from the nozzle of the inkjet head 20 and fall with its center at a distance d away from the polyimide strip 10. Images like these can be used to define the local alignment of the inkjet deposition with respect to the strip 10 pattern and can also be used to automate the local nesting procedure using pattern recognition (see below).

[0088] Figures 10 and 11 show the output and transfer characteristics of transistors formed as in figure 7 (c) and having L channel lengths of 20 pm and 7 pm, respectively, defined through the described differential wetting process above. In both cases the width of the W channel is 3 mm. Figure 10 (a) shows the output characteristics of the 20 pm device. Figure 10 (b) shows the output characteristics of the 7 pm device. Figure 11 (a) shows the transfer characteristics of the 20 pm device. Figure 11 (b) shows the transfer characteristics of the 7 pm device. The 7 pm device exhibits characteristic short channel behavior with reduced current at small source-drain voltage and finite output conductance in the saturation regime. The mobility and the ON-OFF current ratio of short channel devices are similar to those of the long channel devices discussed above, ie N = 0.005 to 0.01 cm2 / Vs and 1ON / 1OFF = 104 to 105.

[0089] Ink confinement is a result of the difference in wetting properties on hydrophobic and hydrophobic surfaces and not

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29/50 requires the existence of a topographic profile. In the above embodiment, the polyimide film can be made very thin (500 µm), which is much thinner than the size of the liquid inkjet droplets (several micrometers). Therefore, alternative techniques for making a pre-standardized substrate can be used, such as the functioning of the glassy substrate surface with a standardized self-assembled monolayer (SAM), for example a SAM containing hydrophobic alkyl or fluoro groups such as trifhioropropyl trimethoxysilane or polar groups such as alkoxy groups. SAM can be standardized by suitable techniques such as exposure to UV light through a shade mask (H. Sugimura et al., Langmuir 2000, 885 (2000)) or microcontact printing (Brittain et al., Physics World May 1998 , p. 31).

[0090] The pre-standardization of the substrate is easily compatible with the process flow described above since the pre-standardization is performed before the deposition of the TFT layers. Therefore, a wide range of standardization and printing techniques can be used to generate the high resolution pre-pattern without the risk of degradation of the active polymer layers.

[0091] Similar techniques can be applied to pre-standardize the surface of the insulating door layer or the surface modification layer before depositing the door electrode to obtain small overlap capacitance. As shown in figure 7 (c) the electrode port 6 can be confined by a standardized layer 14. One possible embodiment of such pre-standardization is the micro-contact printing or UV photopatterning of a self-assembled monolayer (SAM) chlorosilane or methoxy silane, such as octadecyltrichlorosilane. These molecules form stable monolayers on the surface of a SiO2 or glass substrate where they chemically bond to hydroxyl groups on the polar surface and take on the hydrophobic surface.

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30/50

We have found that it is possible to form similar monolayers on the surface of the dielectric polymer port such as PVP or PMMA. This is believed to be due to the attachment of the molecules to the hydroxyl groups on the surface of the PVP. A shallow white energy pattern consisting of a thin hydrophobic line with a small, well-defined overlap with the fontedreno electrodes surrounded by hydrophobic regions, coated by SAM can be easily defined by soft btographic printing. The stamping can be performed under an optical microscope or a mask aligner in order to align the pattern of the pattern with respect to the source-drain electrodes below. When a conductive water-based polymeric paint is deposited on top, deposition is confined to the thin hydrophobic line defined by the self-assembled monolayer. In this way, a smaller line width can be obtained than the normal line width in a non-standard door dielectric layer. This results in a reduction of the overlapping source / drain capacitance for door.

[0092] With the aid of pre-standardized substrates it is possible to manufacture high-speed logic circuits based on the TFT manufacturing processes and via the gap described here.

[0093] One of the crucial requirements for the fabrication of transistor circuits in large areas is the recording and abling of the deposition with respect to the pattern on the substrate. Obtaining the proper registration is particularly difficult on flexible substrates that exhibit distortions over large areas. If, between subsequent standardization steps, the substrate distorts, the next mask level in a photolithographic process will no longer overlap with the pattern underneath. The high resolution inkjet printing process developed here is suitable for obtaining accurate registration on large areas even on plastic substrates, since the position of the inkjet head can be adjusted locally with respect to the pattern on the substrate ( figure 9). This local nesting process can be

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31/50 automated using pattern recognition techniques using images such as the one in figure 9 combined with a feedback mechanism to correct the inkjet head position.

[0094] In order to form a multiple transistor integrated circuit using devices of the type described above, it is desirable to be able to perform gap path interconnections directly across the thickness of the device. This can allow such circuits to be formed in a particularly compact manner. One method of making such interconnections is by using solvent-borne gaps, as will now be described. The method takes advantage of the fact that none of the layers processed by solution of the TFTs described above have been converted into an insoluble form. This allows gaps to be opened by local solvent deposition.

[0095] In order to manufacture a gap formed by solvent (figure 12 (a)), an amount of a suitable solvent 29 is deposited locally on top of the layers through which the gap path must be formed. The solvent is selected so that it is able to dissolve the layers underneath through which the gap is to be formed. The solvent punctures through the layers by progressive dissolution until the gap is formed. The dissolved material is deposited on the side walls W of the gap. The type of solvent and the method of depositing it can be selected for individual applications. However, three preferred aspects are:

1. that the solvent and process conditions are such that the solvent evaporates or is otherwise easily removed so that it does not interfere with subsequent processing and does not cause excessive or dissolving the device and

2. that the solvent is deposited by a selective process such as UP, whereby precisely controlled volumes of the solvent can be precisely applied at the desired location on the substrate, and

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32/50

3. that the diameter of the gap is affected by the surface tension of the solvent droplet and by the solvent's ability to moisten the substrate, and

4. that the solvent does not dissolve the layer below which an electrical connection is to be made.

[0096] Figure 12 (a) illustrates the deposition of a droplet 29 of methanol solvent (containing 20 ng per droplet) on a partially formed transistor device of the general type illustrated in figure 1 (c). The partial device of figure 12 (a) includes a 1.3 μιη thick insulating layer of PVP 28, a F8T2 27 semiconductor layer, a PEDOT electrode layer 26 and a glass substrate 25. In this example it is desired to form a gap path through the PVP insulating layer. Methanol is selected as the solvent because of its ability to easily dissolve PVP; because it can easily evaporate so as not to hinder subsequent processing and because it has satisfactory wetting properties for PVP. In order to form the gap path in this example a printhead the UP is moved to the location on the substrate where it is desired that the gap path is formed. Then the required number of properly sized droplets of methanol are dripped from the UP head until the pathway is complete. The period between successive drops is selected for compatibility with the reason in which methanol dissolves the device's layers. It is preferred that each drop has evaporated completely or almost completely before the next drop is deposited. Note that when the gap reaches the bottom of the non-polar semiconductor layer, the recording stops so that the layers underneath are not removed. Other solvents such as isopropanol, ethanol, butanol or acetone can also be used. To obtain high yield it is desirable to complete the gap by depositing a single droplet of solvent. For a 300 nm thick film and a droplet with a

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33/50 volume of 30 μΐ and a diameter of 50 μιη this requires that the solubility of the layer in the solvent is greater than 1 to 2% by weight by volume. A higher boiling point is also desirable if formation of the gap with a single droplet is required. In the case of PVP, 1,2-dimentyl-2imidazolidinone (DMI) with a boiling point of 225 ° C can be used. [0097] Figure 12 (b) illustrates the effect of dripping several droplets of methanol in sequence on the location of the gap path. The panels on the right show micrographs of the device after 1, 3 and 10 droplets have been dripped. The panels on the left show Dektak surface profile measurements of the same devices through the gap as it is formed. (The location of the gap is generally indicated in the “V” position on each panel). When several droplets are deposited in sequence on the same location, a crater opens in the PVP film. The depth of the crater increases as the successive droplets act and after approximately 6 droplets the surface of the F8T2 layer underneath is discovered. The dissolved PVP material is deposited on a W wall on the sides of the gap. The diameter of the gap is 50 μιη limited by the droplet size. This size is suitable for many applications such as logic circuits and large area display devices.

[0098] The diameter of the gap is determined by the droplet size of the inkjet solvent. The gap diameter was observed to be directly proportional to the droplet diameter (see Fig. 12c). The outer diameter of the side wall is determined by the size and spread of the first droplet and is independent of the thickness of the polymeric layer that is dissolved. The inner diameter of the side wall decreases as the thickness of the polymer increases. For applications where even smaller gaps are required, such as high resolution display devices, even smaller droplet sizes can be used or the

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34/50 substrate surface can be pre-patterned by a suitable technique to confine the droplet on the surface as described above. Other solvents can also be used.

[0099] It will be observed from the measurements of the surface profile that the formation of the gap path causes the material to be dissolved and moved to the edges of the gap path, where it remains after the solvent has been evaporated (indicated in W in figure 12 (B)). It should be noted that the displaced material has a smoother formation than shown in figure 12 (b), the x and y axes of the surface profile points in figure 12 (b) being to dissolve the crusts (x in units of μιη, y in units of Â).

[00100] The mechanism for the formation of a gap, that is, the movement of material to the side walls, is believed to be similar to that of the well-known effect of coffee stain, which occurs if the contact line of a dry droplet containing a solute is tight. Tightening can occur for example due to surface wrinkling or chemical heterogeneity. Note that the deposition of a good solvent always causes the surface to wrinkle during dissolution. When the solvent evaporates, the capillary flow occurs in order to replace the solvent that evaporates close to the contact nail. More solvent is evaporating near the contact line because of the higher surface-to-load ratio near the contact line. The speed of the capillary flow is great compared to the typical diffusion speed, such that the solute is carried to the edges of the droplet and the solute deposition occurs only near the edge, but not in the center of the dry droplet (RD Deegan et al. , Nature 389, 827 (7997)). The diffusion of solute may tend to favor the homogeneous redeposition of the polymer over the entire area in the drying of the solvent, instead of the formation of a side wall. The theory predicts that the capillary flow velocity v (r) (r: distance from the center; R; droplet radius) is proportional to (R - r) -X, where λ = (π - 2θο) / (2π - 20c ). Therefore, v increases as λ

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35/50 increases, that is, the contact angle 0c decreases. Therefore, the smaller the contact angle, the faster the deposition of mass at the edges occurs. [00101] For the opening of gaps it is therefore important that (a) the contact nail of the initial droplet is tightened, (b) that the contact angle of the droplets on top of the polymer to be dissolved is sufficiently small and (c) that the evaporation of the solvent is fast enough that the diffusion of the pomeric solute can be neglected. In the case of IPA over PVP the contact angle is around 12 ° and the droplets typically dry within less than 1 s.

[00102] The smaller the contact angle, the faster the speed of the capillary flow inside the droplet, that is, the more reliable the formation of the side wall will be. However, on the other hand, the smaller the contact angle, the larger the droplet diameter. An optimal contact angle therefore exists to obtain via small diameter gaps with well-defined side walls. To obtain a greater contact angle for a good solvent, the substrate surface can be treated, for example with a self-assembled monolayer with greater solvent repellency. The self-assembled monolayer can be standardized, such as to provide hydrophobic and hydrophobic surface regions, in order to confine solvent deposition to a small area.

[00103] The depth and recording rate of the gap path can be controlled by a combination of the number of solvent drops that are dripped, the frequency at which they are deposited and the rate of solvent evaporation compared to the rate at which the it is even capable of dissolving the substrate. The environment in which deposition occurs and the temperature of the substrate can influence the rate of evaporation. A layer of material that is insoluble or only slowly soluble in the solvent can be used to limit the depth of dissolution.

[00104] Since the TFT layer sequence consists of alternating

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36/50 polar and non-polar layers, it is possible to choose solvents and solvent combinations such that the recording stops at well-defined depths.

[00105] In order to make contact through the gap, a conductive layer can be deposited on it so that it extends into the gap and makes an electrical connection with the material at the bottom of the gap. Figure 13 (a) shows a device of the type shown in figure 12 (a) but including a gold electrode 25 formed after fabricating a gap path as described above.

[00106] Figure 13 shows in curve 30 the current voltage characteristics measured between the bottom PEDOT electrode 26 and a conductive electrode 29 deposited on top of the PVP insulating layer 28. The gap path diameter was 50 pm. For comparison, curve 31 shows a reference sample, in which no gap is located in the overlapping region between the top and bottom electrodes. The characteristics clearly show that the current through the gap path is several orders of magnitude higher than the leakage current through the gate insulator in the absence of the gap path. The current measured through the gap path is limited by the conductivity of the PEDOT electrodes, as can be seen by conducting the conductivity measurements of the individual PEDOT electrodes. This is not limited by the resistance of the gap path, such that only an estimated lower limit for the resistance of the gap path Rv can be obtained from these measurements: Rv <500 kO.

[00107] The gap formation method described above in relation to figure 12 is directly applicable to devices of the depletion type without a diffusion barrier (as in figure 1 (c)) and to devices in which the diffusion barrier is deposited after opening gaps. Figure 14 (a) shows a device in which a gap path has been formed and the port electrode is then deposited without an intermediate layer diffusion barrier. Figure 14 (b) shows a similar device in which

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37/50 after gap formation a diffusion barrier polymer 7 was formed prior to deposition of the electrode 6. In this case the diffusion barrier layer needs to exhibit good load transport properties in order to minimize the resistance of the path gap Rv. A suitable diffusion barrier is a thin layer of TFB as shown in figure 5 (a). [00108] If an even lower contact resistance is required then the semiconductor layers can also be removed at the location of the gap path. This is preferably done after the diffusion barrier has been formed. The diffusion barrier 7 and the semiconductor polymer 4 can be dissolved locally by UP deposition of a good solvent for them such as xylene in this example. By mixing good solvents for both the semiconductor material and the insulator, both layers can be dissolved at the same time. A device in which this has been done followed by deposition of the port electrode is shown in figure 14 (c).

[00109] Solvent mixtures can also be used to reduce the gap gap diameter by increasing the contact angle of the solvent mixture in the layer to be dissolved.

[00110] An alternative technique for forming a gap interconnection and then depositing a conductive material to bridge it is to deposit locally a material that is capable of locally modifying the substrate layer (s) that is (are) ) underneath in order to make it conductive (s). An example is the deposition at a local IJP of a solution containing a mobile dopant that is capable of diffusing in one or several layers. This is illustrated in figure 14 (d), where region 32 indicates material that has been made conductive by treatment with a dopant. The dopant may be a small conjugated molecule such as a triarylamine such as N, N '-diphenyl-Ν, Ν' -bis (3-methylphenyl) - (1,1 '-biphenyl) -4,4' -diamine (TPD) . The dopant is preferably released as for the solvent.

[00111] The method of formation of gap via layers

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38/50 PVP dielectrics can be used to connect the TFT gate electrode to a source or drain electrode in the bottom layer as required, for example, for a logic inverter device as shown in Fig. 15. Gap path connections Similar features are required on most logic transistor circuits. Figure 16 shows points of the characteristic load-enhancing inverter devices formed with two transistor devices normally turned off as in figure 15 (b). Two inverters with different ratios of the channel width to channel length (W / L) ratio for the two transistors are shown (point 35 3: 1 ratio, point 36 5: 1 ratio)). It can be seen that the output voltage changes from a high logic state (-20 V) to a low logic 0 V) when the input voltage changes from low logic to high logic. The inverter gain, which is the maximum slope of the characteristics, is greater than 1, which is a necessary condition to facilitate the manufacture of more complex circuits such as ring oscillators.

[00112] Via gaps as described above can also be used to provide electrical connections between interconnecting lines in different layers. For complex electronic circuits, multi-level interconnection schemes are required. These can be manufactured by depositing a sequence of interconnections 72 and different dielectric layers 70, 71 deposited from compatible solvents (figure 15 (d)). Via gaps 73 can then be formed in the manner described above with interconnecting nails that provide automatic corrosion stop.

[00113] Examples for suitable dielectric materials are those polar polymers (70) such as PVP and non-polar dielectric polymers (71) such as polystyrene. These can alternatively be deposited from polar and non-polar solvents. The gaps can be opened by local deposition of good solvents in the respective dielectric layer while the dielectric layer underneath provides a layer

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39/50 recording stop.

[00114] In the selection of materials and deposition processes for devices of the type described above, it must be taken into account that several and enormous advantages can be obtained if each layer is deposited from a solvent that does not substantially dissolve the layer that is down immediately. In this way, successive layers can be formed by processing in solution. One way to simplify the selection of such materials and the process steps is to aim for the deposition of two or more layers alternately from polar and non-polar solvents, as exemplified for the layer sequence described above. In this way, multilayer devices having conductive, semiconductor and soluble insulating layers can be easily formed. This can avoid those problems of dissolution and swelling of the layers underneath. [00115] The structures, materials and device processes described above are merely illustrative. It will be assessed that they can be varied. [00116] Device configurations other than the top port configuration shown in figure 1 can be used. An alternative configuration is the more standard bottom door configuration shown in figure 17, in which it is also possible to incorporate a diffusion barrier 7 and surface modification layer 8 if required. In figure 17 similar parts are numbered as for figure 1. Other device configurations with different layer sequence can also be used. Devices other than transistors can be formed in an analogous manner. [00117] PEDOT / PSS can be replaced by any conductive polymer that can be deposited from the solution. Examples include polyaniline or polypyrrole. However, some of the attractive characteristics of PEDOT / PSS are: (a) a polymeric dopant (PSS) with an inherently low diffusivity, (b) good thermal stability and air stability and (c) a working function of = 5.1 eV, which is quite comparable to the potential

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40/50 ionization of common gap carrier semiconductor polymers allowing efficient gap loader injection.

[00118] Efficient charge charger injection is crucial, especially for short channel transistor devices having channel dimensions, L <10 pm. In such source-drain devices, contact resistance effects can limit the current of the TFT to small source-drain voltages (figure 10 (b)). In devices of comparable channel length it has been found that the injection of PEDOT source / drain electrodes is more efficient than the injection of inorganic gold electrodes. This indicates that a polymeric source-drain electrode with an ionization potential that is well matched to that of the semiconductor may be preferable to an inorganic electrode material.

[00119] The conductivity of PEDOT / PSS deposited from an aqueous solution (Baytron P) is in the order of 0.1 to 1 S / cm. Higher conductivities of up to 100 S / cm can be obtained with formulations containing a mixture of solvents (Bayer CPP 105T, containing isopropanol and N-methyl2-pyrrolidone (NMP)). Ultimately, care must be taken to ensure that the solvent combination of the formulation is compatible with the solubility requirements of the layer sequence. For applications where even higher conductivities are required, other polymeric conductors or solution-inorganic conductors, such as colloidal suspensions of metallic inorganic particles in a liquid, can be used.

[00120] The processes and devices described here are not limited to devices manufactured with polymers processed by solution. Some of the conductive electrodes of the TFTs and / or the interconnections in a circuit or display device (see below) can be formed from inorganic conductors, which can, for example, be deposited by printing a colloidal suspension or by electroplating on a

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41/50 previously standardized substrate. In those devices where not all layers are to be deposited from the solution, one or more PEDOT / PSS portions of the device can be replaced with an insoluble conductive material such as a vacuum deposited conductor.

[00121] The semiconductor layer can also be replaced by another semiconductor material processable by solution. Possibilities include small conjugated molecules with solubilizing side chains (JG Laquindanum et al., J. Am. Chem. Soc. 120, 664 (1998)), organic-inorganic hybrid materials self-assembled from the solution (CR Kagan et al. , Science 286, 946 (1999)) or inorganic semiconductors deposited by solution such as CdSe nanoparticles (Β. A. Ridley et al., Science 286, 746 (1999)).

[00122] The electrodes can be standardized by techniques other than inkjet printing. Suitable techniques include soft lithographic printing (JA Rogers et al., Appl. Phys. Lett. 75, 1010 (1999); S. Brittain et al., Physics World May 1998, p. 31), screen printing (Z. Bao et al., Chem. Mat. 9, 12999 (1997)), photolithographic standardization (see WO 99110939) or galvanizing or simple immersion coating of a substrate patterned with hydrophobic and hydrophilic surface regions. Inkjet printing is considered to be particularly suitable for standardizing large areas with good registration, in particular for flexible plastic substrates.

[00123] Instead of a glass plate, the device (s) can be deposited on another substrate material, such as Perspex or a flexible, plastic substrate such as polyethersulfone. Such material is preferably in the form of a sheet, is preferably of a polymeric material and can be transparent and / or flexible.

[00124] Although, preferably, all layers and components of the device and circuit are deposited and standardized by

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42/50 solution processing and printing techniques, one or more components, such as a semiconductor layer, can also be deposited using vacuum and / or standardized deposition techniques through a photobtographic process.

[00125] Devices such as TFTs manufactured as described above can be part of a more complex circuit or device in which one or more of such devices can be integrated with one another and or with other devices. Application examples include logic circuits and active matrix circuits for a display or a memory device or a user-defined port layout circuit.

[00126] The basic component of a logic circuit is the inverter shown in figure 15. If all the transistors on the substrate are of the type of depletion or of the type of accumulation, three possible configurations are possible. The load from the depleting inverter (figure 15 (a)) is suitable for the device that is normally connected, (figure 1 (c) and 3) and the enhancement configuration load (figure 15 (b)) is used for transistors normally turned off (figures 1 (a / b) and 4). Both configurations require a gap between the transistor's door electrode and its source and drain electrodes, respectively. An alternative configuration is the resistance load inverter (figure 15 (c)). The latter device can be manufactured by printing a thin, narrow PEDOT line of suitable length and conductivity like the load resistor. By reducing the conductivity of PEDOT, for example, by increasing the ratio of PSS to PEDOT, the length of the resistive nail can be minimized. The conductivity of Baytron P PEDOT / PSS with a PEDOT / weight ratio (PEDOT + PSS) of 0.4 was measured to be on the order of 0.2 S / cm for a film as deposited. Annealing at 280 ° C for 20 min under N2 atmosphere the conductivity increased to 2 S / cm. By diluting the solution with PSS, the conductivity can be decreased by orders of magnitude. For a relationship

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43/50 by weight of PEDOT / (PEDOT + PSS) of 0.04 a conductivity of 10-3 S / cm was measured after annealing at 280 ° C. Resistors with a resistance of 50 ΜΩ were manufactured by the jet printing of ink from a PEDOT line with a width of the order of 60 μιη and a length of 500 μιη. [00127] The different inkjet printing components that have been developed, ie transistors, gap interconnections, resistors, capacitors, multi-layer interconnection schemes, etc., can be integrated to manufacture integrated electronic circuits by a combination direct printing and solution processing. Inkjet printing can be used for all stages of processing where lateral standardization is required. The simple inverter circuits described above are the building blocks for more complex logic circuits. [00128] TFTs processed by solution as described above can be used as pixel switching transistors of active matrix display devices such as liquid crystal display (LCD) or electrophoretic devices (B. Comiskey et al., Nature 394, 253 (1998)) for which a suitable circuit is shown in figure 18 (a) and light-emitting diode display devices (H. Sirringhaus et al., Science 280, 1741 (1998), for which a suitable circuit shown in figure 18 (b); or as an active matrix communication element of a memory device, such as random access memory (RAM) In figures 18 (a) and (b) TI and / or T2 transistors can be formed from the transistors as described above Characteristics 40 represent a display or memory element with current and voltage supply blocks.

[00129] Examples of possible device configurations for controlling the voltage at the electrode of an LCD or an electrophoretic display device are shown in figure 19, where similar parts are numbered as for figure 1. In the drawings in figure 19 (as for figures 7, 14 and 17, for example) the insulating door layer may include a

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44/50 structure of the multiple layer containing a diffusion barrier and / or surface modification layer, as in figure 1 (a).

[00130] Referring to figure 19, the electrodes source and port 2, 6 of the TFT are connected to data lines 44 and address 43 of the active matrix, which can be manufactured from a different conductive material to obtain conductivity longer lengths. The drain electrode 3 of the TFT can also be the pixel electrode 41. The pixel electrode can be formed from a different conductive material as in figure 19. In devices that rely on the application of an electric field instead of an injection charge carrier is not required that this electrode 41 is in direct contact with the display element 40, such as a liquid crystal or electrophoretic ink, etc. In this configuration, the total pixel area occupied by the TFT and the interconnecting nails must be kept small in order to obtain an adequate aperture ratio and to reduce the potential crosstalk between the display element 40 and the signals in the data and address lines 43 and 44.

[00131] The configuration in figure 19 (b) is more complicated. However, the total pixels or a large part of the pixel area is available for TFTs and interconnecting lines and the display element is protected from signals in the data and address lines 44 and 43 by the pixel electrode 41. The fabrication of this configuration requires an additional dielectric layer 42 and a gap path filled with conductive material 45 to connect the pixel electrode 41 to the drain electrode of the TFT 3. The gap path can be fabricated by the procedure described above.

[00132] Note that in this configuration the opening ratio can be maximized and can be approximately 100%. This configuration can also be used for backlit display applications such as transmissive LCD display devices, since fully polymeric TFTs as manufactured here are highly transparent in

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45/50 visible spectral range. Figure 20 shows the optical absorption spectrum measured in an F8T2 polymer TFT, in which the polymer chains are uniaxially aligned by depositing the liquid-crystalline semiconductor polymer in a rubberized polyimide alignment layer that also serves as the pre-patterning layer for high resolution printing. It can be seen that the device is highly transparent over most of the visible spectral range because of the relatively high bandwidth of the F8T2. Even better transparency can be achieved if semiconductor layers such as F8 or TFB or another derivative of polyfluorenes (US 5,777,070) with higher band intervals are used. The alignment of the polymeric chains gives rise to optical anisotropy such that polarized light parallel to the direction of alignment (point labeled “I I”) is more strongly absorbed than polarized light perpendicular to the direction of alignment (point labeled “±”). Optical anisotropy can be used on an LCD display device to further increase the optical transparency of TFTs by guiding the direction of the alignment of normal polymer chains to the polarizer between the glass back plane and the light behind. Under polarized light, transistor devices appear almost colorless in visible light, if the F8T2 layer thickness is below 500 µm. All other TFT layers, including PEDOT, have low optical absorption in the visible spectral range.

[00133] Another advantage of the low optical absorption of the semiconductor layer is the reduced photosensitivity of the characteristic TFT to visible light. In the case of amorphous silicon TFTs, a black matrix should be used to avoid large OFF current under light illumination. In the case of polymeric TFTs with wide-band semiconductors it is not required to protect the TFTs from ambient light and the light behind the display device.

[00134] The configuration in figure 19 (b) is also well adapted for the

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46/50 TI impulse transistor of an LED display device (figure 18 (b)), as this allows the impulse current of the TFT to be increased by manufacturing an interdigitated series of source-drain electrode with large channel width W making use of the complete area located under the 41 pixel electrode.

[00135] Alternatively, the bottom door TFT configuration of figure 17 can also be used in all the above applications (figure 19 (c)). [00136] One of the important technological results for the manufacture of active matrix circuits is the contact between the PEDOT / PSS TFT and the 2,3,6 pixel electrodes and the metallic interconnecting lines 43, 44 and 41. Due to their strong acidic nature PEDOT / PSS is not compatible with many common inorganic metals such as aluminum. Aluminum 15 easily oxidized in contact with PEDOT / PSS. One possible solution is the manufacture of interconnecting nails and 43, 44 and 41 pixel electrodes from indium tin oxide (ITO) or tantalum, tungsten and other refractory metals or another material having more stability in this environment or the use of a suitable barrier layer.

[00137] In the case of an application on display it may also be desirable to manufacture TFTs with a small channel length by printing on a pre-patterned substrate indicated as 10 in figure 19, as described above.

[00138] Similar device configurations for active matrix transistor switches can also be used if the pixel element to be controlled is not a display element but a memory element such as a capacitor or diode, such as in a dynamic random access memory.

[00139] In addition to the conductive electrodes, some of the other layers of the TFTs can also be standardized by direct printing methods, such as screen printing or UP. Figure 21 (a) (in which parts

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Similar 47/50 are numbered as for figure 1) shows a device in which an active layer island of the semiconductor layer 4 and the insulating layer port 5 can be directly printed. In this case, no gap is required, but connections can be made by directly printing a suitable electrode pattern B. In areas where the communication or interconnecting nails 43, 44 overlap thick islands of a dielectric polymer 46 can be printed to provide electrical insulation (figure 21 (b)).

[00140] A plurality of devices formed as described above can be formed on a single substrate and interconnected by conductive layers. Devices can be formed on a single level or on more than one level, some devices being formed on top of others. Using interconnecting strips and via gaps as described above, especially compact circuit arrangements can be formed.

[00141] The technology developed here for the manufacture of inkjet printed transistors, via gaps and interconnecting lines can be used to manufacture electronic circuits integrated by inkjet printing. A prefabricated substrate containing an array of hydrophilic and hydrophobic surface regions can be used which defines the length of the transistor channel and / or the width of the interconnecting nails. The substrate may also contain an array of highly conductive metal interconnecting nails. Using a combination of inkjet printing and continuous layer deposition of the solution, a series of transistor devices are defined in custom-made locations and custom-made channel widths. An integrated circuit is then manufactured by forming electrical connections between pairs of transistors and suitable interconnections using inkjet printing via gaps and conductive lines.

[00142] It is also possible that said prefabricated substrate can already

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48/50 contain one or more of the components of the transistor devices. Said substrate may contain, for example, a series of completed inorganic transistor devices, each having at least one exposed electrode. In the present case, the inkjet manufacturing of an integrated circuit may comprise the formation of electrical connections between pairs of transistors and the deposition of a single or multiple level interconnection scheme, through the use of gaps, interconnecting lines and blocks of insulation printed in inkjet (see figure 15 (d)).

[00143] In addition to the transistor devices, said electronic circuit can also comprise other active and passive circuit elements such as those display or memory elements or capacitive or resistive elements.

[00144] Using the techniques described above a unit having a plurability of transistors can be formed and then configured for a specific subsequent use by means of solution-based processing. For example, a substrate having a plurality of transistors 50 of the type shown in figure 1 (a), (b) or (c), in the form of a door arrangement, for example, can be formed on a plastic plate (figure 22 ). Other devices such as diodes or capacitors can also be formed on the plate. Then the plate can be placed in an inkjet printer having a print head for a suitable solvent to form via gaps 52 (eg, methanol) and a suitable material to form conductive tracks 53 and to fill in gaps (eg example, PEDOT). The inkjet printer can be operated under the control of a properly programmed computer, with knowledge of the location and configuration of the transistors on the plate. Then, by a combination of gap formation and interconnection steps, inkjet printing can configure the circuit to perform a desired electronic or logical function, by interconnecting the transistors in the desired way. It is

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49/50 technology thus allows the formation of specific logic circuits on substrates using small, inexpensive equipment.

[00145] Examples of the application of such a circuit are for the printing of active electronic tickets, luggage tags, and identification. A printed ticket or label device can be loaded with a number of unconfigured units, each comprising a substrate that carries a plurality of transistors. Said ticket printing device includes a computer that is capable of controlling an inkjet printer as described above and of determining an electronic circuit that is indicative of the valid function of the ticket. When required to print a ticket the printing device sets up a substrate for the appropriate electronic circuit by printing gaps and / or conductive material so that the transistors on the substrate are properly configured. The substrate can then be encapsulated, for example by sealing with an adhesive plastic plate, leaving the electrical connection terminals 54, 55 exposed. The ticket is then dismissed. When this ticket must be validated, inputs are attached to one or more input terminals and the circuit outputs at one or more output terminals are monitored to verify their operation. Said tickets can preferably be printed on plastic and flexible substrates to make them convenient for use as tickets.

[00146] User-defined circuits other than for value or labeling purposes can be manufactured in a similar way. Verification and reading of circuits can also be done by remote probing using, for example, radio frequency radiation (Physics World, March 1999, page 31).

[00147] The ability of the end user to define circuits by simple inkjet printing of appropriate connections over a standard arrangement or arrangement offers significantly increased flexibility,

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50/50 compared to circuits planned at the factory.

[00148] The present invention is not limited to the preceding examples. Note that aspects of the present invention include all new and / or inventive aspects of the concepts described herein and all new and / or inventive combinations of the features described here.

[00149] The Applicants draw attention to the fact that the present invention may include any characteristic or combination of characteristics disclosed herein implicitly or explicitly or any generalization thereof, without limiting the scope of any definitions presented above. In view of the foregoing description, it will be apparent to a person skilled in the art that various modifications can be made within the scope of the invention from their appended claims.

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1/7

Claims (47)

1. Method for forming on an substrate an electronic device that includes a polymeric conductive material that can be deposited from the solution in a plurality of regions, the operation of the device using current flow from a first region to a second region, the method characterized by fact that you understand: forming a mixture by mixing the conductive polymeric material that can be deposited from the solution with water; form a containment structure on the substrate that includes a first zone (10) in a first area of the substrate and a second zone (12) in a second area of the substrate, the first zone (10) with greater repellency for the mixture than the second zone (12), and a third zone (12) in a third area of the substrate spaced from the second area by the first area, the first zone (10) with greater repellency for the mixture than the third zone ( 12); and depositing the material on the substrate by applying the solution on the substrate; whereby the deposited material is confined by the relative repellency of the first zone to the mutually spaced regions defining said first and second regions of the device and being electrically separated in its plane by means of the relative repellency of the first zone. 2. Method according to claim 1, characterized by the fact that the width of the first area (10) between the second and third areas (12) is less than 20 microns. 3. Method according to claim 1, characterized by the fact that the width of the first area (10) between the second and third areas (12) is less than 10 microns. 4. Method, according to any of the preceding claims, characterized by the fact that the material formed in the regions Petition 870170066371, of September 6, 2017, p. 62/74 2/7 mutually spaced form source and drain electrodes (2, 3) of a transistor. 5. Method, according to claim 4, characterized by the fact that it comprises the step of depositing an additional material (4) in the space between the mutually spaced regions. 6. Method, according to claim 5, characterized by the fact that the additional material (4) deposited in the space between the mutually spaced regions forms a channel of the transistor. 7. Method according to claim 6, characterized by the fact that said additional material (4) is semiconductor. Method according to any one of claims 5 to 7, characterized in that the additional material (4) is a polymeric material. Method according to any one of claims 5 to 8, characterized in that the additional material (4) is deposited from solution. 10. Method for forming an electronic switching device on a substrate that includes an electrically conductive material or semiconductor material (6) in a multitude of regions, the method characterized by the fact that it comprises: forming a mixture by mixing the material with a liquid; form a containment structure on the substrate that includes a first zone (14) in a first area of the substrate and a second zone in a second area of the substrate, the first zone having greater repellency by mixing than the second zone, and a third zone (14) in a third area of the substrate spaced from the first area by the second area, the third zone (14) having greater repellency by the mixture than the second zone; and depositing the material (6) on the substrate, applying the mixture on the substrate; Petition 870170066371, of September 6, 2017, p. 63/74 3/7 according to which the deposited material can be confined by the relative repellency of the first and third zones (14) to the second zone. 11. Method according to claim 10, characterized in that the width of the second zone between the first and the third zone (14) is less than 20 microns. Method according to claim 10, characterized in that the width of the second zone between the first and the third zone (14) is less than 10 microns. 13. Method according to any one of claims 10 to 12, characterized in that the material (6) is electrically conductive. 14. Method, according to claim 13, characterized by the fact that material (6) forms a transistor control electrode, the voltage on which it is likely to influence the current flow between contiguous regions of the device. 15. Method according to claim 13 or 14, characterized by the fact that the material (6) forms a transistor gate electrode. 16. Method according to claim 15, characterized by the fact that the width of the overlapping region between the gate electrode (6) of the transistor and the source and drain electrodes (2, 3), respectively, is less than 20 microns . 17. Method according to claim 15, characterized by the fact that the width of the overlapping region between the transistor gate electrode and the source and drain electrodes, respectively, is less than 10 microns. 18. Method according to any one of claims 10 to 17, characterized in that the substrate surface is provided by a self-assembled monolayer (14) and at least one of the first and Petition 870170066371, of September 6, 2017, p. 64/74 The second zone is defined by the configuration of the self-assembled monolayer. 19. Method, according to claim 18, characterized by the fact that the step of configuring the self-assembled monolayer is carried out by exposure to light through a shade mask. 20. Method, according to claim 19, characterized by the fact that the step of configuring the self-assembled monolayer is carried out by placing the substrate in contact with a soft stamp. 21. Method according to any of the preceding claims, characterized in that the first and second zones (10, 12, 14) are formed on the exposed surface of a layer (10, 14) deposited on a planar structural member . 22. Method according to any of the preceding claims, characterized in that the contact angle of the mixture in the first area (10) is 20 ° greater than the contact angle of the mixture in the second area. 23. Method according to any of the preceding claims, characterized by the fact that the contact angle of the mixture in the first area (10) is 40 ° greater than the contact angle of the mixture in the second area. 24. Method according to any of the preceding claims, characterized by the fact that the contact angle of the mixture in the first area (10) is 80 ° greater than the contact angle of the mixture in the second area. 25. Method according to any of the preceding claims, characterized in that the substrate surface is provided by a self-assembled monolayer (10, 14) and at least one of the first and second zones is defined by the configuration of the mono - self-assembled layer. 26. Method according to claim 25, characterized Petition 870170066371, of September 6, 2017, p. 65/74 by the fact that the step of setting up the self-assembled monolayer (10, 14) is accomplished by exposure to light through a shade mask. 27. Method, according to claim 25, characterized by the fact that the step of configuring the self-assembled monolayer (10, 14) is carried out by arranging the substrate in contact with a soft stamp. 28. Method according to any one of the preceding claims, characterized in that the substrate surface is provided by a non-polar material (10, 14) and at least one of the first and second zones is defined by the treatment of the surface of the substrate. non-polar polymer. 29. Method according to claim 28, characterized in that the non-polar material (10, 14) is a polyimide. 30. Method according to claim 29, characterized in that it comprises the step of mechanically polishing the polyimide (10, 14) to promote the molecular alignment of the polyimide. 31. The method of claim 29, characterized in that it comprises the step of optically treating the polyimide (10) to promote the molecular alignment of the polyimide. 32. Method according to claim 28, characterized by the fact that the surface treatment is chemical attack. 33. The method of claim 28, characterized by the fact that the surface treatment is plasma treatment. 34. Method according to claim 33, characterized by the fact that the plasma is carbon tetrafluoride and / or oxygen. 35. Method according to claim 28, characterized by the fact that the surface treatment comprises its exposure to ultraviolet light. 36. Method according to any of claims 28 to 35, characterized in that said one of the zones is the second zone (12). Petition 870170066371, of September 6, 2017, p. 66/74 6/7 37. Method according to any one of the preceding claims, characterized in that the first zone (10) induces an aligned molecular structure of the conductive polymeric material that can be deposited from the solution. 38. Method according to any one of the preceding claims, characterized in that the first zone (10) is capable of inducing the alignment of polymer chains in the conductive polymeric material that can be deposited from the solution. 39. Method according to any one of the preceding claims, characterized by the fact that the first zone (10) is capable of inducing the alignment of the chains of a polymeric material (4) deposited on the first zone. 40. Method, according to claim 38, characterized by the fact that the alignment is in a direction extending between the second and third zones (12). 41. Method according to claim 39, characterized in that the chains are chains of said additional material (4). 42. Method according to any one of the preceding claims, characterized in that the conductive polymeric material that can be deposited from the solution is deposited by droplet deposition (13). 43. Method according to any of the preceding claims, characterized in that the conductive polymeric material that can be deposited from the solution is deposited by inkjet printing (13). 44. Method according to claim 42 or 43, characterized in that the width of at least one of the zones (10) is less than the droplet diameter formed in the inkjet printing step. Petition 870170066371, of September 6, 2017, p. 67/74 7/7 45. Method according to claim 43 or 44, characterized in that the boundary area between the first and second zones (10, 12) is optically distinct, and the method includes the step of optically detecting the boundary area between the first and second zones second zones (10, 12) and locate the inkjet printing device in relation to the substrate depending on that detection. 46. Method according to any of the preceding claims, characterized in that the conductive polymeric material that can be deposited from the solution is a conjugated polymer. 47. Logic circuit and display or memory device (40), characterized by the fact that it comprises a set of active matrix of a plurality of transistors formed by the method according to any of the preceding claims. Petition 870170066371, of September 6, 2017, p. 68/74 1/19 1'ÒY