KR100927890B1 - Solution processing devices - Google Patents

Abstract

Depositing a first material from a solution using the first solvent to form a first layer of the transistor, and subsequently making the first material still soluble in the first solvent, A method of forming a transistor is disclosed that includes forming a second layer of the transistor by depositing a second material from a solution in a second solvent in which the first material is substantially insoluble.

Inkjet, Transistor, Solvent, Deposition, Plastic Substrate

Description

SOLUTION PROCESSED DEVICES

The present invention relates to solution processing devices and a method of forming the devices.

Recently, semiconducting conjugated polymer thin film transistors (TFTs) are inexpensive logic circuits integrated on a plastic substrate (see Dr. Drury et al. In APL 73, 108 (1998)), high-resolution active-matrix displays. Applications in pixel transistor switches and optoelectronic integrated devices (H. Shiringhouse et al. In Science 280, 1741 (1998) and A. Dodabarapur et al. In Appl. Phys. Lett. 73, 142 (1998)). I became interested in these fields. In testing, device configurations with polymer semiconductor and inorganic metal electrodes and gate insulating layers proved to be high performance TFTs. The charge carrier mobility up to 0.1 cm ² / Vs and the ON-OFF current ratio of 10 ⁶ -10 ⁸ were achieved, which is the result of the performance of amorphous silicon TFTs (H.S.H. et al. In Advances in Solid State Physics 39, 101 (1999)). Almost equal to).

Thin device-quality films of conjugated polymer semiconductors can be formed by coating a polymer solution of an organic solvent on a substrate. Thus, this technique is ideally suited for inexpensive and wide area solution processing that is compatible with flexible plastic substrates. In order to take full advantage of the potential cost and ease of processing, it is desirable to allow all components of the device to be deposited by solution, including semiconductor layers, insulator layers, conductive electrodes and interconnects.

In order to fabricate all-polymer TFT devices and circuits, the following main problems must be solved:

Integrity of the multi-layer structure: During solution deposition of subsequent semiconductor, insulating and / or conductive layers, the underlying layers must not dissolve or be expanded by the solvent used for the deposition of subsequent layers. This expansion occurs when the solvent is mixed in the lower layer, which generally degrades the properties of the layer.

High resolution patterning for the electrodes: The conductive layers need to be patterned to form TFT channels with well defined interconnects and a channel length of L ≦ 10 μm.

To manufacture TFT circuits, vertical interconnect areas (via holes) need to be formed to electrically connect the electrodes of different layers of the device.

In WO 99/10939 A2 a method for manufacturing all polymer TFTs is disclosed, which method relies on the conversion of the solution processing layers of the device to insoluble form before depositing subsequent layers of the device. This overcomes the problems of dissolution and expansion of the underlying layers. However, this lowers the selectability of semiconductor materials that can be used and extremely limited to a class of precursor polymers that are undesirable in some aspects. In addition, cross-coupling of the gate insulating layer of the dielectric makes it difficult to manufacture via holes through the dielectric layers and therefore must use techniques such as metal punching (WO 99/10939 A1).

According to aspects of the present invention, there is provided the device (s) and method (s) set forth in the independent claims of the appended claims. Preferred features are described in the dependent claims.

According to a first aspect of the invention, there is provided a method, comprising depositing a first material from a solution using a first solvent to form a first layer of a transistor; And depositing a second material from a solution in a second solvent in which the first material is substantially insoluble on the first material, while still allowing the first material to dissolve in the first solvent. A method of forming a transistor is provided that includes forming two layers.

Preferably, the method comprises a third material from a solution in a third solvent in which the second material is substantially insoluble on the second material, while still allowing the second material to be soluble in the second solvent. And forming a third layer of the transistor by depositing.

Suitably, at least one layer of the transistor is formed by ink jet printing (IJP). This layer can be, for example, a layer providing an electrode of a transistor such as a gate, source or drain electrode.

Advantageously, the method comprises forming a functional layer of said transistor; Forming an isolation layer on the functional layer; And forming a gate of the transistor on the insulating layer. The isolation layer may provide a diffusion barrier and / or a surface modification layer that are separate or identical layers.

According to a second aspect of the present invention, there are provided methods of limiting solution deposition of a material to defined regions on a substrate. The method includes patterning the surface of the underlying substrate into regions with different surface free energy. The substrate has surface areas that are hydrophobic, and remaining surface areas that are hydrophilic. Such solution deposition includes inkjet printing and the limitation of the ink to hydrophobic or hydrophilic surface regions.

Preferably, the pattern on the substrate is preferably source and drain electrodes of a transistor having a small channel length of L <20 μm, gate electrodes having a well defined overlap with the source and drain electrodes, and interconnects. Define them.

According to a third aspect of the invention, a method of forming via holes defining electrical connections between interconnects and electrodes in different layers is provided. This method preferably involves dissolution or doping of the layers by local deposition of solvents or dopant solutions by inkjet printing.

According to another aspect of the present invention, there is provided a method of manufacturing an integrated circuit of transistor devices in which some and / or other circuit elements of the transistor devices are formed by inkjet printing.

According to another aspect of the invention, a method of manufacturing an array of electronic devices having at least one exposed electrode is provided. The method includes interconnecting electronic devices by inkjet printing a conductive material in such a way that an electronic circuit having a user-defined function is obtained.

Preferably, one of the first and second solvents is a polar solvent, and the other of the first and second solvents is a nonpolar solvent.

Preferably, one of the first or second materials is a semiconductor material and the other of the first or second materials is a dielectric material.

Preferably, the second material is a dielectric material, one of the first and third materials is a semiconductor material, and the other of the first or third materials is a conductive material.

One of the first and second layers may be a nonpolar polymer layer that is soluble in the nonpolar solvent. The other of the first and second layers may be a polar polymer layer soluble in a polar solvent. The interaction parameter (D) for the nonpolar polymer and the polar solvent is suitably greater than 5, preferably greater than 10 and most preferably greater than 15. The interaction parameter (D) for the polar polymer and the nonpolar solvent is suitably greater than 5, preferably greater than 10 and most preferably greater than 15.

Suitably, one of the second and third solvents is a polar solvent and the other of the second and third solvents is a non-polar solvent.

Suitably, the second solvent is a moderately polar solvent comprising polar and nonpolar groups, and one of the first and third solvents is a highly polar solvent containing only polar groups to be.

The second polymer layer may be a normal polar polymer layer that is soluble in a polar solvent. In this case, one of the first or third polymer layers is a normal nonpolar polymer layer and the other of the first or third polymer layers is a polar polymer layer. The interaction parameter (D) for the nonpolar polymer and the solvent of normal polarity is greater than 5, preferably greater than 10 and most preferably greater than 15. The interaction parameter (D) for the polar polymer and the common polar solvent is greater than 5, preferably greater than 10 and most preferably greater than 15. Usually polar solvents can be, for example, alcohols or acetates.

The first layer is soluble in nonpolar solvents, and the second layer is soluble in common polar solvents including hydrophilic and hydrophobic groups. The third layer is soluble in polar solvents. Alternatively, the third layer may be soluble in nonpolar solvents.

The second layer may be an active layer of a transistor.

Suitably, one of the first and second layers is a source and / or drain electrode layer of the transistor and the other of the first and second layers is a semiconductor layer of the transistor.

Suitably, one of the first and second layers is a semiconductor layer of a transistor and the other of the first and second layers is an insulating layer of a transistor.

The semiconductor layer can be a conjugated polymer, preferably a conjugated block copolymer.

The semiconductor layer has a block copolymer having an electron affinity of at least 3.0 eV or 3.5 eV, the block copolymer having a first block of conjugated monomer units each connected by at least two covalent bonds, and a first copolymer of monomer units. Contains 2 blocks.

The semiconductor layer has a block copolymer having an ionization potential in the range of 5.5 eV to 4.9 eV, the block copolymer having a first block of conjugated monomer units each connected by at least two covalent bonds, and a first block of monomer units. Contains 2 blocks.

The first block of conjugated monomer units comprises one or more groups comprising fluorene derivatives, phenyline derivatives and indenofluorene derivatives, and the second block of monomer units is a thiophene derivative, a tree One or more groups including triarylamine derivatives and benzothioadiazole derivatives.

The semiconductor polymer may be F8T2 or TFB.

Preferably, the semiconductor layer comprises a liquid crystal conjugated polymer. The method includes heating the liquid crystal polymer to its liquid crystal state. The method preferably comprises the step of aligning the liquid crystal polymer uniaxially. Aligning the liquid crystal polymer includes depositing the liquid crystal polymer on a layer having an aligned molecular structure. Aligning the molecular structure of the layer is performed by mechanically rubbing the layer. The method preferably includes aligning the molecular structure of the layer by optically treating the layer.

The semiconductor layer suitably has a bandgap of at least 2.3 eV, preferably at least 2.5 eV and is optically transparent. The semiconductor layer suitably has an ionization potential of 4.9 eV or 5.1 eV or more. The semiconductor layer suitably has an electron affinity of 3.0 eV or 3.5 eV or more.

One of the first and second layers is an insulator layer of the transistor, and the other of the first and second layers is a gate electrode layer of the transistor.

One of the first and third layers is an insulator layer of the transistor, and the second of the first and third layers is an isolation layer of the transistor. This isolation layer can be a diffusion barrier layer. This diffusion barrier layer may comprise a nonpolar polymer. The diffusion barrier layer may comprise a polyfluorene derivative. The polyfluorene derivative may be F8, F8T2 or TFB. The isolation layer may be a surface modification layer, preferably as described above.

The method includes modifying the surface of the first layer before depositing the second layer. The surface modification of the first layer is to provide a contact angle of 100 ^o , 80 ^o or 60 ^o or less for depositing the second layer on the first layer. In this case, the smaller the contact angle is, the better the wettability of the layer deposited on top of the first layer is.

Deforming the surface of the first layer suitably includes treating the surface of the first layer.

Deforming the surface of the first layer suitably includes depositing a surface modification material on the surface of the first layer. This surface modification material may be deposited from a solution in a suitably polar solvent.

Suitably, the first layer is deposited on a surface, and the method includes heating the substrate before depositing the second or third layer.                 

At least one of the first, second and third layers is formed by ink jet printing.

Suitably, at least one of the source, drain or gate electrode of the transistor is formed by ink jet printing.

Suitably, the transistor has a source, drain or gate electrode formed of a conductive polymer. Suitably, the electrode is formed of an optically transparent conductive polymer. Suitably, the conductive polymer comprises a polymeric counterion dopant.

Suitably, the material of one of the first and second layers is PEDOT / PSS.

Suitably, the transistor has an insulator layer formed of nonconjugated or partially conjugated polymer. Suitably, the insulating layer comprises hydrophilic and hydrophobic groups, and is usually soluble in polar solvents.

Suitably, the material of one of the first and second layers is PVP.

According to another aspect of the invention, the first active layer soluble in the first solvent; And a second active layer adjacent to the first active layer, the second active layer being soluble in a second solvent in which the first material is substantially insoluble.

The transistor preferably comprises a third active layer adjacent to the second active layer and soluble in a third solvent in which the second material is substantially insoluble. Preferably, one of the first and second layers comprises a polar polymer soluble in a polar solvent, and the other of the first and second layers is a nonpolar polymer soluble in a nonpolar solvent. Suitably, one of the second and third layers comprises a polar polymer soluble in a polar solvent, and the other of the second and third layers is a nonpolar polymer soluble in a nonpolar solvent. Suitably, one of the solvents is alcohol.

Suitably, one of the first and second layers is a source and / or drain electrode layer of the transistor and the other of the first and second layers is a semiconductor layer of the transistor.

Suitably, one of the first and second layers is a semiconductor layer of the transistor and the other of the first and second layers is an insulator layer of the transistor.

Suitably, the material forming the semiconductor layer is a polyfluorene derivative.

Suitably, the semiconductor layer has a bandgap of at least 2.3 eV, preferably at least 2.5 eV and is optically transparent. The semiconductor layer suitably has an ionization potential of 4.9 eV or more, preferably 5.1 eV or more.

The semiconductor layer comprises a block copolymer having an electron affinity of at least 3.0 eV or 3.5 eV, the block copolymer comprising a first block of conjugated monopolymer units each connected by at least two covalent bonds, and a monopolymer A second block of units.

The semiconductor layer comprises a block copolymer having an ionization potential in the range of 5.5 eV to 4.9 eV, the block copolymer comprising a first block of conjugated monopolymer units each connected by at least two covalent bonds, and a monopolymer A second block of units.

The first block of monomer units comprises one or more groups comprising fluorene derivatives, phenyline derivatives and indenofluorene derivatives, and the second block of monomer units comprises thiophene derivatives, triarylamine derivatives and One or more groups comprising benzothioadiazole derivatives.

The polyfluorene derivative is suitably F8T2 or TFB.

The semiconductor layer preferably has an ionization potential of greater than 4.9 eV or 5.1 eV.

Preferably, one of the first and second layers is an insulating layer of a transistor, and the other of the first and second layers is a gate electrode layer of the transistor.

Preferably, one of the first and third layers is an insulating layer of a transistor, the other of the first and third layers is a gate electrode layer of the transistor, and the second layer is an isolation layer of the transistor. The isolation layer may be a surface modification layer.

Preferably, the isolation layer is a diffusion barrier layer. The diffusion barrier layer may include a polyfluorene derivative. The polyfluorene derivative may be F8T2 or TFB.

The first or second layer can be formed by ink-jet printing. The third layer can be formed by ink jet printing.

One of the first, second and third layers is a source layer of a transistor, another one of the first, second and third layers is a drain layer of the transistor, and the first, second and third layers The other of the three layers is preferably the gate layer of the transistor.                 

The material of one of the first and second layers may be PEDOT / PSS.

The material of one of the first and second layers may be PVP.

The transistor can be optically transparent.

The transistor may be a thin film transistor.

According to another aspect of the present invention, there is provided a logic circuit, a display portion or a memory device comprising the above-described transistor.

According to another aspect of the present invention, there is provided a logic circuit, a display or a memory device comprising an active matrix array of a plurality of the above presented transistors.

According to another aspect of the invention, there is provided a display comprising a plurality of display elements, at least one of which is switched by an optically transparent thin film transistor.

The presented transistor is preferably located at the rear of the display member.

Such display portion may comprise an optically active area that may be switched by the transistor, the transistor being optically active by means of a conductive object located in a via hole formed through at least one layer of the transistor. Electrically coupled with the area.

The invention will be explained by way of example with reference to the accompanying drawings.                 

1 shows different device configurations of solution treated all-polymer TFTs.

FIG. 2 shows the transfer characteristics of the polymer TFTs according to FIG. 1C with an F8T2 active layer, a PVP gate insulating layer, and a PEDOT / PSS gate electrode.

FIG. 3 shows the transfer characteristics of the polymer TFTs according to FIG. 1C with the F8T2 active layer, PVP gate insulating layer and PEDOT / PSS gate electrode deposited with the sample maintained at room temperature (a) and about 50 ° C. (b). .

4 shows the output (a) and transfer characteristics (b) of an F8T2 full-polymer TFT comprising an F8 diffusion barrier layer and a PVP surface modification layer as in FIG. 1 (a).

FIG. 5 shows the transfer characteristics of F8T2 all-polymer TFTs as in FIG. 1 (a) with TFB (a) and polystylene (b) diffusion barriers and PVP surface modification layers.

FIG. 6 shows an optical micrograph of the full-polymer TFT according to FIG. 1 (a) with F8T2 active layer and source-drain electrodes printed directly on a bare glass substrate.

FIG. 7 shows the formation of TFTs with small channel length and small overlap capacitance passing through the patterning of the substrate surface up to hydrophobic and hydrophilic regions.

FIG. 8 is an optical micrograph of a transistor channel region having L = 20 μm (a) and L = 5 μm (b) after IJP deposition of PEDOT / PSS source / drain electrodes in the vicinity of a hydrophobic polyimide bank. Illustrated.

9 shows an optical micrograph taken during the deposition of ink drops in the vicinity of the polyimide bank.

10 and 11 show the output and transfer characteristics of transistors formed as in FIG. 7 (c) with channel lengths L = 20 μm and L = 7 μm, respectively.

FIG. 12 is a simplified diagram (a), Dektak profilometry and optical micrographs (b) of the process of forming via holes by successive deposition of methanol droplets on a 1.3 μm thick PVP gate dielectric layer, and inkjet The dependence (c) of the via hole outer diameter and inner diameter on the diameter of the drops and the thicknesses of the PVP layer is shown.

13 shows current-voltage characteristics through a via hole having a bottom PEDOT electrode and a top electrode.

14 illustrates different processes for forming via holes.

Figure 15 shows logic inverters (depletion-load (a), enhancement-load (b) and resistance-load (c)), and multilevel interconnect configurations. Application of via holes such as (d) is shown.

FIG. 16 shows the characteristics of the improved-load inverter circuits as in FIG. 1 (a) formed of printed full-polymer TFTs having two resistors having different W / L size ratios.

17 illustrates an alternative base-gate device configuration.

18 shows a simplified diagram of an active matrix pixel, wherein the display or memory component is controlled by voltage (a) or current (b).

19 shows a possible configuration of pixels of an active matrix.                 

20 shows polarized optical absorption of an aligned F8T2 TFT.

FIG. 21 shows an overlap region between (a) polymer TFTs having patterned active layer islands formed by printing of semiconductor and dielectric layers and (b) conductor interconnects separated by printed insulating layer islands. do.

FIG. 22 shows a matrix of transistor devices connected by a network of IJP interconnects for forming user defined electronic circuits. FIG.

The preferred formation methods described herein allow for the formation of solution-processed thin film transistors of fully organic matter, where no layer is converted or crosslinked into an insoluble form. Each layer of such a device can maintain a form that can be dissolved in the solvent from where it is deposited. This enables a simple method of forming via holes through the dielectric insulating layers based on local deposition of a solvent, which is described in detail below. Such a device may include, for example, one or more of the following components.

Patterned conductive source-drain, gate electrodes and interconnects.

A semiconductor layer having charge carrier mobility in excess of 0.01 cm 2 / Vs and fast on-off current switching in excess of 10 ⁴ .

Thin gate insulation layer

A diffusion barrier layer that protects the semiconductor layer and the insulating layer from being inadvertently doped by impurities and ion diffusion.

A surface modification layer which enables high resolution patterning of the gate electrode by printing techniques.

Via holes for interconnects through the dielectric layers.

However, the method described herein is not limited to the formation of devices having all the features described above.

Formation of the first exemplary device will now be described with reference to FIG. 1. The device of FIG. 1 is a thin film field effect transistor (TFT) configured to have a top-gate structure.

An aqueous solution containing conductive polymer polyethylenedioxythiophene / polystyrolsulfonate (PEDOT (0.5% by weight) / PSS (0.8% by weight)) was placed on top of the cleaned 7059 glass substrate 1. Inkjet printing deposits source-drain electrodes 2, 3 and interconnection lines and contact pads (not shown) between the electrodes. Other solvents such as methanol, ethanol, isoprophenol or acetone may be added to affect the surface tension, viscosity and wetting properties of the ink. PEDOT / PSS is available from Bayer (available under the trade name "Baitron P"). The IJP printer is piezoelectric. It is equipped with a precision two-dimensional analysis stage and a microscope stage that allows the alignment of patterns printed sequentially for each. The IJP head is driven by a voltage pulse. Suitable driving conditions for spraying 0.4 ng drops of typical solid content per drop can be achieved with a pulse height of 20 V, a rise time of 10 ms and a fall time of 10 ms. After drying the glass substrate tops, they produce a PEDOT dot having a typical diameter of 50 μm with a typical thickness of 500 mm 3.

IJP of the source-drain electrodes is performed in air. The samples are then transferred to an inert atmosphere glove box system. The substrates are then spun-dryed in an organic solvent such as mixed xylenes in the case of polyfluorene polymers, which will then be used for deposition of the active semiconductor layer. They are then heat treated at 200 ° C. for 20 minutes in an inert nitrogen atmosphere to remove residual solvents and other nonvolatile species in the PEDOT / PSS electrodes. Then, by spin-coating, the active semiconductor polymer 4 is deposited into a thick film of 200-1000 GPa. Various semiconductors such as regioregular poly-3-hexylthiophene (P3HT) and polyfluorene co-polymers such as poly-9,9'-dioctylfluorene-co-dithiophene (F8T2) Polymers have been used. F8T2 is a preferred choice because it shows good stability in air during deposition of the gate electrode. A 5-10 mg / ml solution (purchased from Romil) of F8T2 in anhydrous, mixed xylenes is spin-coated at 1500-2000 rpm. In the case of P3HT, a 1% solution by weight is used in the mixed xylenes. Lower PEDOT electrodes are insoluble in nonpolar organic solvents such as xylene. The films are then spun-dried in a solvent such as isoprophenol or methanol which can then be used for the deposition of the gate insulator layer 5.

Subsequent heat treatment steps may then be performed to improve the charge transfer properties of the semiconductor polymer. In polymers exhibiting a liquid crystalline phase at a high temperature heat treatment at the temperature, the direction of the polymer chains is parallel to each other as a result of the liquid crystal transition. In the case of F8T2, the heat treatment is carried out at 275-285 ° C. for 5-20 minutes under an inert N ₂ atmosphere. The samples are then quickly cooled to room temperature to fix the orientation of the chains and to make amorphous glass. If the samples are provided on a flat glass substrate without an alignment layer, the polymer adopts a multidomain configuration, wherein liquid crystal domains with random orientation are located inside the TFT channel. Transistor devices in which F8T2 is provided in the glassy state by rapid cooling from a liquid crystal state exhibiting mobility on the order of 5-10 ^-3 cm 2 / Vs are at least one order of magnitude larger than the mobility measured in devices with the spun F8T2 films. In addition, the deposited devices exhibit a high turn-on voltage (Vo). This is because the density of the local electron trap state in the glassy state is lower compared to the deposited state which is partially crystal.

If the polymer is provided in a monodomain state with the uniaxial of the polymer chains parallel to the transistor channel, the mobility by a factor of 3-5 can be further improved. This is accomplished by coating the glass layer with a suitable alignment layer, such as a mechanically polished polyimide layer (9 in FIG. 1 (b)). In the single domain state, the polymer chains are aligned to be uniaxially parallel to the polishing direction of the underlying polyimide layer. This further improves the charge carrier mobility of the devices, where the TFT channel is parallel to the alignment direction of the chains. This process is described in more detail in British Patent Application No. 9914489.1, which is co-pending with the present application.

After deposition of the semiconductor layer, the gate insulating layer 5 is deposited by spin coating a solution of polyhydroxystyrene (also called polyvinylphenol (PVP)) from a polar solvent, wherein the lower semiconductor The polymer is insoluble. Preferred solvent choices are alcohols such as methanol, 2-propenol or butanol, where nonpolar polymers such as F8T2 with particularly low solubility do not swell. The thickness of the gate insulating layer is between 300 nm (solution concentration is 30 mg / ml) and 1.3 μm (solution concentration is 100 mg / ml). Poly-vinylalcohol (PVA) to water, or poly-methyl-methacrylate to butyl acetate or propylene glycol methyl ether acetate Other insulating polymers and solvents that meet solubility requirements such as methacrylate (PMMA) may also be used.

Then, a gate electrode 6 is deposited on the gate insulating layer. The gate electrode layer is deposited directly on the gate insulating layer (see FIG. 1 (c)) or for one or more intermediate layers (FIG. 1 (a)) due to process reasons such as surface modification, diffusion barrier or solvent compatibility. (b)) may be present.

+20V(상향 삼각형)에서 턴온된다. 그러나, 역방향 스캔(scan)에서(하향 삼각 형) 상기 트랜지스터는 V^f _o>+35V에서만 턴오프된다.To form the simple device of FIG. 1C, the PEDOT / PSS gate 6 can be printed directly on top of the PVP insulating layer 5. The substrate is transferred back to the IJP station in air where the PEDOT / PSS gate electrode pattern is printed with an aqueous solution. The lower PVP gate insulating layer has low solubility in water, whereby the integrity of the gate electrode is preserved during printing of the PEDOT / PSS gate electrode. Although PVP contains high density polar hydroxyl groups, its solubility in water is low because of a backbone similar to nonpolar polystyrene. Similarly, PMMA is insoluble in water. 2 shows the transfer characteristics of an IJP TFT having an F8T2 semiconductor layer, a PVP gate insulating layer, and an IJP PEDOT / PSS source-drain and gate electrodes. The device properties are measured in a nitrogen atmosphere. Successive measurements show the rise (up triangle) and fall (down triangle) of the gate voltage, respectively. The properties belonging to the devices were obtained by the newly prepared group (a) of PEDOT / PSS (Baitron P) and group (b) one year later. Transistor operation can be clearly shown. However, these devices exhibit unusually normally-on operation at positive threshold voltage (Vo)> 10V, while reference devices formed by depositing gold source-drain and gate electrodes are normally-off. It was found that the behavior Vo <0. In devices formed from the “old” group of PEDOT (FIG. 2B), high hysteresis effects are observed due to the high concentration of mobile ionic impurities (see below). If the sweep begins at deep depletion (Vg = + 40V), the transistor will be V ^f _o

Turns on at + 20V (up triangle). However, in the reverse scan (scan) (down-triangle), the transistor is turned off only V ^f _o> + 35V.

The normal-on operation and hysteresis effects may be caused by diffusion of ionic species of one of the layers of the device. The unusually large positive value of Vo suggests that the ion is negative. Positive species can be expected to compensate for some of the mobile charge in the cumulative layer and shift Vo to a more negative value. To identify the source of these ion species, the other layers and PEDOT source / drain electrodes were formed as described above, while the top-gate IJP PEDOT electrode was replaced with a deposited gold electrode to form devices. It has been found that in this structure the devices are normally off and exhibit a stable threshold voltage. This means that the doping and hysteresis effects of the full-polymer device are related to the solution deposition of the conductive polymer upper gate electrode and the migration from the PEDOT solution / film to the lower layers of the device, the possible diffusion of ionic impurities.

It has been found that by depositing a gate electrode on a heated substrate it is possible to control the value of the threshold voltage and to reduce the amount of hysteresis. This reduces the drying time of the droplets on the substrate. 3 (b) shows the transfer characteristics of the TFT device, for which the substrate was heated to a temperature of 50 ° C. during the deposition of the gate electrode. It can be seen that the hysteresis effect is significantly smaller than the deposition of the gate at room temperature (FIG. 3b) and that Vo has a relatively small positive value of 6V. By controlling the deposition temperature, the threshold voltage can be adjusted in the region of Vo = 1-20V.                 

As shown in FIG. 1C, a device having gate electrodes deposited directly on a PVP layer is a depletion type device. Its normal-on operation is useful for depletion type logic circuits such as a simple depletion-load logic inverter (FIG. 14 (a)).

In order to form an improved type of normal-off TFTs, doping of the semiconductor during deposition of the gate can be prevented by bonding of a diffusion barrier layer. In the device of FIGS. 1 (a) and (b), a thin layer 7 of nonpolar polymer is deposited over the PVP gate insulating layer prior to the deposition of the conductor polymer gate electrode. This layer will act as a diffusion barrier that blocks the diffusion of ionic species through weakly polarized PVP insulators. PVP includes groups of high density polar high-strength seals that tend to improve the conductivity and diffusion of ions through the membrane. Poly-9,9'-dioctylfluorane (F8), polystyrene (PS), poly (9, '9-dioctyl-fluorene-N- (4-butylphenyl) diphenylamine) (TFB) or F8T2 Several nonpolar polymers have been used. Thin films of these polymers of about 50-100 nm may be deposited on the surface of the PVP gate insulating layer from a solution of a nonpolar organic solvent such as xylene, where PVP is insoluble.

It has been found that PEDOT / PSS direct printing from a polar aqueous solution on top of a nonpolar diffusion barrier layer or on top of a weakly polar polymer such as PMMA has been problematic due to poor wettability and wide contact angles. To treat this, a surface modification layer 8 is deposited on top of the nonpolar polymer. The layer provides a hydrophilic surface rather than a hydrophobic surface, where the PEDOT / PSS can be more easily formed. This enables high resolution printing of the gate electrode pattern. To form the surface modification layer, a thin layer of PVP can be deposited from isoprophenol solution, where the lower diffusion barrier layer is insoluble. The thickness of the PVP layer is preferably 50 nm or less. High resolution printing of PEDOT / PSS is possible on the surface of the PVP. Alternative surface modification layers can be used. These include thin layers of surfactants or polymers, such as soaps, including hydrophilic and hydrophobic functional groups. These molecules tend to be phase separated into hydrophobic and hydrophilic groups that are attracted to the underlying nonpolar polymer and the interface with the free surface, respectively. Another possibility is to briefly expose the surface of the nonpolar diffusion barrier to a weak O ₂ plasma that makes the surface hydrophilic. A suitable plasma treatment that does not reduce the TFT device performance is exposure to a 13.5Mhz O ₂ plasma at 50W power for 12 seconds.

If the gate electrode is printed from a solvent that is less polar than water, including alcohol (isopropanol, methanol, etc.), a surface modification layer on top of the nonpolar diffusion barrier may be needed.

The integrity of the layer sequence depends on the alternate deposition of polymeric materials extracted from polar and nonpolar solvents. The first layer in the solvent used to deposit the second layer is less than 0.1 w% per unit volume, preferably less than 0.01 w%.

Criteria for solvent suitability can be quantified using Hildebrand solubility parameters for quantification of polarity (DW van Krevelen, Properties of polyners, Elsevier, Amsterdam (1990)). The solubility of each polymer (solvent) can be described by parameters δ _d , δ _p , δ _h indicating the interaction, polarity, and hydrogen bond interaction between liquid polymer (solvent) molecules. If the molecular structure is known by adding donations of polymers of different functional groups, the values for the three parameters can be calculated. These polymers are mostly common polymers. Often δ _p and δ _d are combined such that δ _v ² = δ _d ² + δ _p ² .

The mixing free energy is given by ΔG _m = ΔH _m -TΔS _m , where the mixing entropy is ΔSm> 0 and the mixing enthalpy is ΔH _m = V * φ _p * φ _s * ((δ _v ^p -δ _v ^s ) ² + (δ _h ^p −δ _h ^s ) ² ). From this the polymer (P) dissolves better than the solvent (S), i.e., the less ΔH _m , the more D = ((δ _v ^p -δ _v ^s ) ² + (δ _h ^p -δ _h ^s ) ^1/2 Also decreases. As an approximate criterion, if the interaction parameter (D) is less than approximately 5, the polymer may be dissolved in the solvent. If D is 5-10, swelling is often observed. If D is greater than 10, the polymer is generally insoluble in the solvent and there is no swelling.

In order to obtain a thermal insulation interface in the melt-treated TFT device, the D value for the solvent of each polymer layer and the next layer must be approximately greater than 10. This is particularly important for solvents in semiconductor polymer layers and gate dielectrics. For F8T2 and isopropanol (butyl acetate), the D value is approximately 16 (12).

For some device configurations, the overall multilayer structure alternates between polymers, including polar groups that are well soluble in polar solvents such as water, and polymers that are soluble in nonpolar solvents such as xylene, with little or no polar groups of materials. It may be in stacked form. In this case the interaction parameter D is larger because of the difference in δp between the polymer layer and the next solvent. PEDO's high polarity electrode, nonpolar semiconductor layer like F8T2, high polar dielectric layer like polyvinyl alcohol deposited from water soluble material, TFB's nonpolar diffusion barrier layer serving as buffer layer to enable a series of stacking, PEDO The / PSS gate electrode is an example.

However, it is often convenient to separate the nonpolar semiconductor layer and the polar gate electrode layer by a single dielectric layer. This layer sequence is possible by allowing a slightly polar polymer material deposited from a slightly polar solvent to be placed between the highly polar or nonpolar polymer. Polymers with some polarity are polymers comprising polar and nonpolar groups and do not melt well in polar solvents. With regard to the solubility parameter, it can be defined that the solubility parameter δ _H of the solvent having a slight polarity is significantly different from the base polymer. In this case, although the polar solubility parameter δ _P (δ _V ) of the solvent is similar to the base polymer layer, bulging (large D) can be prevented. The slightly polar polymer layer may include specific functional groups such as hydroxy groups, and the hydroxy groups function to dissolve the polymer well in a solvent containing a functional group that attracts the functional groups of the polymer well. This attraction can be hydrogen bond interactions. Due to the functionality of the polymers, the polymers are well soluble in materials with moderate polarity and are poorly soluble in polar solvents. An example of a polymer with suitable polarity is a PVP gate dielectric layer (FIG. 1) lying between a nonpolar semiconductor layer and a PEDOT / PSS gate electrode layer. An example of a solvent having a suitable polarity is IPA (δ _h ; F 8 T 2: δ _h ≒ 0).

FIG. 4 shows the output (a) and transfer (b) properties of all F8T2 IJT TFT polymer layers having a PVP gate insulating layer, an F8 barrier layer, and a PVP surface modification layer as disclosed in FIG. The device has a pure, quasi-ideally normal-off transistor action at V ₀ ≦ 0V. The threshold voltage shift between the upper (top triangle) and lower (bottom triangle) voltages is ≤ 1v. The properties of the device are very similar to standard devices fabricated under inert atmospheric pressure using Au drain and gate electrodes. The field effect fluidity is 0.005-0.01 cm ² / Vs, and the on / off current ratio measured between V _g = 0 and -60 V is 10 ⁴ -10 ⁵ .

The device is fabricated using a wide range of nonpolar diffusion barrier layers such as F8, TFB (FIG. 5 (a) shows the transfer properties) and PS (FIG. 5 (b) shows the transfer properties). In each case, pure clean-off behavior and hysteresis effects and limit voltage shifts can be observed, which is quantitatively the same as the reference device with Au drain electrodes. This supports the interpretation that the insertion of a nonpolar polymer under the gate electrode prevents the diffusion of ionic impurities during and after the melt deposition of the gate insulating layer. It is known that this regenerates the TFT limit voltage and results in good operating stability. Normally-off devices with diffusion barriers are preferred over depletion-type devices described above, since normally-off devices with diffusion barriers have better long-term limit voltage stability and longer lifetimes as ions are prevented from diffusing. A meltable composite polymer or oligomeric material can be used as the semiconductor layer, in which case the polymer or oligomeric material has a suitable field effect fluidity of greater than 10 ⁻³ cm / Vs, preferably 10 ⁻² cm / Vs. . Suitable materials are found in Chem. Che. 7,369 (1997) or in the name Z. bao is illustrated in Advanced Materials 12, 227 (2000).

One of the key requirements for processing printed TFTs with good stability and high on-off current ratios is the excellent stability of the semiconductor material against accidental doping due to atmospheric oxygen and water in the processing and printing steps. Printing TFTs have been processed using regologular P3HT semiconductor polymers deposited from F8T2 (see above) or mixed xylene solutions as active semiconductor layers. In the case of P3HT TFTs provided in the test device under inert atmospheric pressure, the field effect fluidity in the range of 0.05-0,1 cm ² / Vs is slightly higher than in the case of F8T2. However, regloregular P3HT is unstable to doping with oxygen and / or water, thereby increasing film conductivity during the fritting step performed at low on-off current ratios with air. This is related to the low ionization potential of P3HT in the I _P ≒ 4.9 eV range. P3HT with higher on-off current ratios greater than 10 ⁶ has been tested, but in this case a reduction doping step such as exposing to hydrazine vapor after deposition was required (H. Sirringhaus et al., Advances in Solid State Physics 39, 101 (1999). Announced)). However, in the case of the above-mentioned IJP TFTs, this post-treatment reduction step cannot be performed because the PEDOT electrode is doped and the conductivity is significantly reduced. Therefore, in order to obtain a high current conversion ratio, it is important that the polymer semiconductor is used with excellent stability against accidental doping with oxygen or water.

Groups of materials having good ambient stability and high flowability are preferably AB hard rod block copolymers comprising a regularly arranged series of A and B blocks. Suitable A blocks are structurally well defined, ladder-like polymers with large band spacing, ionization potentials greater than 5.5 eV as a single polymer, and have good ambient stability. Suitable A blocks include fluorene derivatives (US 5,777,070), indine fluorene derivatives (S. Setayesh, Macromolecules 33, 2016 (2000)), phenyl or ladder phenyl derivatives (J, Grimme et al., Adv. Mat. 7 , 292 (1995)). Suitable B blocks include hole transport moieties with small band spacings containing heteroatoms such as sulfur or nitrogen, and ionization potentials less than 5.5 eV as a single polymer. The role of the B block is to lower the ionization potential of the block copolymer. The ionization potential of the block copolymer is preferably 4.9 eV ≦ I _p ≦ 5.5 eV. Examples of such copolymers are F8T2 (ionization potential 5.5eV) or TFB (US 5,777,070).

 Other suitable hole transporting polymers are homopolymers of polythiophene derivatives with ionization potentials greater than 5 eV, such as alkoxy or polythiophene with fluorine and side chains (RD McCullough published in Advanced Materials 10, 93 (1998)). ).

Instead of the hole transport semiconductor polymer, a molten electron transport material can be used. They require an electron affinity greater than 3 eV to prevent the retention of atmospheric impurities such as oxygen, which acts as a carrier trap. Small molecule semiconductors for electron transport (H.E. Katz et al., Published in Nature 404, 478 (2000)) soluble in suitable materials or polythiophene derivatives having a fluorinated side chain can be included. Also suitable are structurally well-defined AB type block copolymers, ladder type A blocks with ionization energy greater than 5.5 eV, and electron transport B blocks that increase the electron affinity of the copolymer to 3 eV, preferably greater than 3.5 eV. Do. Examples of A blocks include fluorene derivatives (US 5,777,070), idenofluorene derivatives (S. Setayesh published in Macromolecules 33, 2016 (2000)), phenyline or ladder phenyline derivatives (J. Frimme et al. Mat. 7,292 (1995). B-blocks for electron transport include benzothiadiazole derivatives (US 5,777,00), phenyl derivatives, naphthalenetetracarboxylic dimid derivatives (HE Katz et al., Published in Nature 404, 478 (2000)) or fluorinated thiopine derivatives. have.

For fast operation of the logic circuit, the channel length L of the transistor and the overlap d between the source / drain-in and the gate should be as small as possible. Critical dimension is L. This is because the operating speed of the transistor circuit is approximately proportional to L ⁻² . This is important for semiconductor layers with relatively low fluidity.

Such high resolution patterns are not achievable with current inkjet printing techniques, and are limited to feature sizes 10-20 μm even with the latest IJP techniques (FIG. 6). If fast action and high density packing are required, then a technique must be employed that allows for finer feature resolution. The technique described below uses ink surface interactions to define inkjet droplets on the substrate surface. Smaller channel lengths can be achieved by the technique than by the prior art.

The confinement technique can deposit the deposition material on the substrate with high resolution. First, the surface of the substrate is treated such that the selected surface is less repulsive with relatively attractive force to the material to which it is deposited. For example, some surfaces are hydrophobic while others are prepatterned. The preliminary patterning step is performed with high resolution and / or accurate registration so that subsequent deposition can be made accurately.

7 shows one embodiment of preliminary pattern processing. FIG. 7 shows forming the device of FIG. 1 (c) with a particularly fine channel length L. FIG. The same reference numerals are used as in Fig. 1 (c). 7 (b) shows printing and ink limitations on the pretreated substrate.

Before deposition of the source-drain electrodes 2, 3, a thin polyimide layer 10 is formed over the glass sheet 1. The polyimide layer 10 is finely patterned to be removed at the location where the source-drain electrode is formed. The removal step may be performed by photolithography which enables high resolution and / or accurate registration. In one example of such treatment, the polyimide may be covered with a layer of photoresist 11. The photoresist is patterned by photolithography so that it can be removed where the polyimide is removed. The polyimide is then removed by a process in which the photoresist is resistant. The polyimide is selected because the glass substrate has hydrophobicity as opposed to being relatively hydrophilic. Next, a PEDOT material forming a source-drain electrode is deposited over the hydrophilic substrate region 12 by ink jet printing. When ink droplets spread over the glass substrate region touch the boundaries of the hydrophobic polyimide region 10, the ink is repelled and does not flow into the hydrophobic surface region. By this limiting effect, the ink is deposited only on the hydrophilic surface, and a high resolution pattern having a small gap and a transistor channel length smaller than 10 mu m can be formed (Fig. 7 (b)).

Figure 7 (a) shows an embodiment of a process in which the relative surface effect is increased after the polyimide is removed or the polyimide is removed. The polyimide layer 10 and the photoresist 11 are exposed to an oxygen plasma. The oxygen plasma etches the thin (500 μs) polyimide layer faster than the thick (1.5 μm) photoresist layer. The exposed glass surface 12 in the source-drain electrode region becomes hydrophilic by exposure to oxygen plasma prior to removal of the photoresist. It is worth noting that during the removal of the polyimide, the surface of the polyimide is protected by the photoresist and retains hydrophobicity.

If desired, the surface of the polyimide can be made more hydrophobic by further exposure to CF ₄ plasma. CF ₄ plasma only fluorinates the polyimide surface and does not interact with the hydrophilic glass substrate. This additional plasma treatment may be performed before removing the photoresist to fluorenize only the side surface of the polyimide pattern 10 or after removing the photoresist.

The contact angle of PEDOT / PSS in water in oxygen plasma treated 7059 glass is θ _glass ≒ 20 °, in contrast to the contact angle θ _PI ≒ 70-80 ° on the polyimide surface. The contact angle of PEDOT / PSS in water in fluorinated polyimide is 120 °.

As described above, when a PEDOT / PSS layer is deposited from an aqueous solution into a pre-patterned polyimide layer, the PEDOT / PSS ink is source-drain, even though the channel length L is only a few microns (Fig. 7 (b)). It is limited to the electrode region.

In order to facilitate the definition of ink droplets, the kinetic energy of the ink droplets is kept as small as possible. The larger the droplet size, the greater the likelihood that the spreading droplet will ignore the hydrophilic confinement structure or spill into neighboring hydrophilic regions.

Deposition of the ink droplets 13 is preferably done to the substrate 12 at a distance d between the center of the ink droplets and the polyimide boundary. On the one hand, d needs to be small enough to allow the spreading ink to reach the border and allow the PEDOT film to extend to the polyimide border end. On the other hand, d needs to be large enough so that ink that spreads quickly does not spill into the hydrophobic region. This increases the risk that PEDOT deposition on the polyimide 10 limits the TFT length, and can form a short circuit between the source and drain electrodes. D ≒ 30-40 μm was found to be suitable for depositing PEDOT droplets containing 0.4 ng of solid components with 7059 glass treated with oxygen plasma with a horizontal distance between adjacent droplets of 12.5 μm. The optimal value of d depends on the wettability of the surface as well as the deposition pitch, which means the horizontal distance between successively deposited droplets, the period at which the droplets are deposited and the drying time of the solution.

The hydrophobic confinement layer that defines the channel length of the transistor can provide a second function. In a subsequent deposition step of depositing a semiconductor polymer into the channel of the transistor, it can be used as an aligning tool. The polyimide layer 10 may be mechanically polished or photoaligned and used as an alignment layer 9 (Fig. 1 (b)) to provide a single region alignment of the liquid crystal semiconductor polymer 4.

Similarly, gate electrode 6 may be defined by patterned layer 14 formed on top of gate insulating layer 5. The gate insulating layer 5 has a surface area which attracts or repels the solution against which the gate electrode is deposited. The patterned layer 14 may be aligned along the source-drain pattern to minimize the overlapping region between the source / drain and the gate electrode (FIG. 7C).

Materials other than polyimide can be used as the prepatterned layer. Sophisticated preliminary pattern processing techniques other than photolithography may be used.

Figure 8 illustrates the ability of a relatively hydrophobic and hydrophilic layer structure to define a liquid "ink" deposited by inkjet printing. FIG. 8 shows an optical microstructure of a substrate comprising a thin polyimide strip 10 treated to be relatively hydrophobic as described above and a wide glass substrate region 12 treated to be relatively hydrophilic as described above. Indicates. PEDOT material used as the source-drain electrode is deposited by inkjet printing a series of droplets flowing in lines 2 and 3 proximate the strip 10. Although the inkjet material shows a low contrast, it can be seen that at the end surfaces 2 and 3 of the deposited material, the deposited material is confined to the strip 10 to reach a strip thickness (L = 5 μm). have.

9 shows an inkjet deposition process in the vicinity of the polyimide strip 10. The image was taken with a stroboscope camera mounted under a transparent substrate. The end portion of the polyimide pattern 10 is represented by a white line. The ink droplets 21 are ejected from the nozzles of the inkjet head 20 and landed with the droplet center separated by the distance d from the polyimide strip 10. This image can be used to finely localize the inkjet deposition along the strip pattern 10 and to automate a local alignment process using pattern recognition (see description below).

10 and 11 show the output and transfer characteristics of transistors formed by the method of FIG. 7 (c), each channel length L of which is defined by the aforementioned differential wetting process, 20 μm, 7 μm. In each case, the channel width is 3 mm. 10 (a) shows the output characteristics of a 20 μm device. 10 (b) shows the output characteristics of a 7 μm device.

11 (a) shows the transfer characteristics of a 20 μm device. 11B shows the transfer characteristics of a 7 μm device. The 7 μm devices show characteristic short channel operation with reduced current at small source-drain voltages and limited output conductance at saturation. The mobility of the short channel and the on-off current ratio are similar to that of the long channel device discussed above. That is ^{μ = 0.005 - 0.01 cm 2 /} Vs, I ON / I OFF = 10 4 - 10 5 to be.

Ink restriction is the result of the difference in the moist properties of the hydrophobic and hydrophilic surfaces and does not require the presence of a topographic profile. In the above embodiment, the polyimide film can be made very thin (500 mm 3). This is much smaller than the size of the ink droplets in the liquid state (several micrometers). Thus, other methods for forming substrate pre-patterns, such as polarized groups such as fluorine groups or alkoxy groups, such as patterned magnetically bonded monolayers (SAMs) such as hydrophobic alkyl or trifluoropropyl-trimethoxysilane, etc. The method of functionalizing the surface of a glass substrate with SAM containing a group can be used. SAM can be applied by appropriate methods such as UV light exposure through shadow masks (H. Sugimura et al., Published in Langmuir 2000, 885 (2000)) or microcontact printing (Britain et al. Published in Physics World May 1998, p.31). Can be patterned.                 

Since the pre-patterning is performed prior to the deposition of the layer of the TFT, the pre-patterning of the substrate is easily compatible with the processing flow described above. Thus, a wide range of patterning and printing methods can be used to generate high resolution pre-patterns without the risk of degrading the polymer layer.

Similar methods can be applied to pre-pattern the surface of the gate insulating layer or surface modification layer prior to the deposition of the gate electrode so that small overlapping performance can be achieved. As shown in FIG. 7C, the gate electrode 6 may be defined by a patterned layer 14. One example of such pre-patterning is microcontact printing or UV photopatterning of magnetically bonded monolayers (SAMs) containing methoxysilane groups such as chlorosilanes or octadecyltrichlorosilanes. These molecules form stable monolayers on the surface of SiO ₂ or glass substrates, where the molecules chemically bind to hydroxy groups on the polar surface to render the surface hydrophobic. The inventors have found that it is possible to form similar monolayers on the surface of gate dielectric polymers such as PVP or PMMA. It is believed that this is due to the binding of molecules to the hydroxy group on the PVP surface. The surface free energy pattern, consisting of fine hydrophobic lines with well-defined small overlapping portions surrounded by source-drain electrodes surrounded by SAM coated hydrophobic regions, can be easily defined by soft slab stamping. Stamping may be performed under an optical microscope or mask alignment device to align the stamp pattern with respect to the underlying source-drain electrode. When induction is made, water-based polymer inks are confined to the fine hydrophilic lines defined by self-aligning monolayers (SAMs). In this way, a line width smaller than the typical line width on the gate dielectric layer in which the pattern is not formed can be obtained. As a result, the source-drain to gate overlap capacitance is reduced.

With the help of a pre-patterned substrate, it is possible to assemble a high speed logic circuit based on the assembly process through the TFTs and via holes described herein.

One of the important requirements for the assembly of transistor circuits over large areas is the matching and alignment of the deposition on the pattern on the substrate. It is particularly difficult to achieve proper registration on a flexible substrate that exhibits distortion over a large area. If the substrate is warped between subsequent patterning steps, the next mask level in the lithographic printing process no longer overlaps with the pattern below. Since the position of the inkjet head can be locally adjusted relative to the pattern on the substrate, the high resolution inkjet printing process developed here is suitable for achieving accurate registration over a large area on a plastic substrate (FIG. 9). This local alignment process can be automated using a pattern recognition technique using an image as in the case of FIG. 9 combined with a feedback mechanism to correct the position of the inkjet head.

In order to form a multi-transistor integrated circuit using a device of the type described above, it is desirable for the via holes to be directly interconnected through the thickness of the device. Thereby, such a circuit can be formed particularly small. One way to achieve such interconnection is to use a via hole formed of a solvent. This will be described in detail later. This method has the advantage that none of the solution treatment layers of the TFTs described above are converted to an insoluble form. This opens the via holes by local deposition of the solvent.

In order to make the via holes (FIG. 12A) formed by the solvent, an appropriate amount of solvent 29 is deposited locally on top of the layer where the via holes are to be formed. The solvent is selected to melt the lower layer where the via holes are formed. The solvent seeps into the layer by gradual dissolution until the via hole is formed. The dissolved material is deposited on the sidewalls W of the via holes. The type of solvent and its deposition method can be selected according to the individual application. However, the following four cases are preferable.

1. Solvent and process conditions should be such that the solvent can be easily removed so that it does not evaporate or otherwise interfere with subsequent processes and cause excessive or incorrect dissolution of the device.

2. The solvent must be deposited by an optional process such as IJP, whereby a precisely controlled amount of solvent can be applied exactly to the desired point on the substrate.

3. The diameter of the via hole is affected by the surface tension of the solvent droplet and the ability to wet the substrate of the solvent.

4. The solvent does not dissolve the lower layer to which the electrical connection should be made.

FIG. 12A shows depositing a methanol solvent droplet 29 (containing 20 ng per droplet) on the partially formed transistor device of the general type illustrated in FIG. 1C. The partial device of FIG. 12A includes a 1.3 μm thick PVP insulating layer 28, an F8T2 semiconductor layer 27, a PEDOT electrode layer 26, and a glass substrate 25. In this example, it is desirable to form via holes through the insulating PVP layer. Methanol is chosen as a solvent because of its ability to easily dissolve PVP. The reason is that it can easily evaporate so as not to interfere with subsequent processes and has the satisfactory wet nature of PVP. In this example, to form a via hole, the IJP printing head moves to the point on the substrate where the via hole should be formed. The required number of appropriately sized droplets of methanol then falls from the IJP until the via holes are formed. The interval of successive drop drops is chosen to match the rate at which methanol dissolves the layer of the device. Each drop is preferably evaporated completely or almost completely before the next drop is deposited. It should be noted that when the via holes reach the bottom nonpolar semiconductor layer, the etching process is stopped so that the underlying layer is not removed. Other solvents such as isopropanol, ethanol, butanol or acetone can also be used. In order to increase the throughput, it is preferable to form via holes by deposition of a single solvent droplet. For 300 nm thick films and droplets with a volume of 30 pl and a diameter of 50 μm, the dissolution capacity of the layer in the solvent should be higher than 1-2 wt% by volume. If it is necessary to form a via hole with a single drop, a higher boiling point is required. For PVP, 1,2-dimethyl-2-imidazolidinone (DMI) with a boiling point of 225 ° C. may be used.

FIG. 12B shows several drops of methanol sequentially over the point where the via holes were formed. The right panel shows micrographs of the device after dropping 1, 3 and 10 drops. The left panel shows the Dektak surface profile measurement of the same device across the via holes when via holes were formed. (The point of the via hole is indicated by the position "V" in each panel.) When several drops are sequentially deposited at the same point, a hollow hole is formed in the PVP film. The depth of the indentation increases as the drops drop continuously, and after approximately six drops fall the surface of the underlying F8T2 layer is exposed. This dissolved PVP material is deposited in the wall W of the side of the via hole. The diameter of the via hole is approximately 50 μm, which is limited by the size of the droplets. This size is suitable for many applications such as logic circuits and large display devices.

The diameter of the via hole is determined by the size of the ink jet solvent droplet. The depth of the hole was observed to be proportional to the diameter of the drop (see FIG. 12C). The outer diameter of the sidewalls is determined by the size and sparging of the first drop, which is independent of the thickness of the polymer layer being dissolved. As the thickness of the polymer increases, the inner diameter of the sidewalls decreases. In applications where smaller holes are required, such as high resolution display devices, smaller droplet sizes may be used and the substrate surface may be prepatterned by a suitable method of confining droplets on the surface as described above. Other solvents may also be used.

The measurement of the surface profile allows the material to dissolve and displace to the edge of the via hole by the formation of the via hole and remain intact after the solvent has evaporated (as indicated by W in FIG. 12B). It should be noted that the displaced material is of a smoother shape than illustrated in FIG. 12B. The scales of the x and y axes of the surface profile graph of FIG. 12b are different (x is μm, y is Å).

The mechanism for the formation of via holes, ie the movement of material about the sidewalls, is believed to be similar to that of the well-known coffee-stain effect. This effect occurs when the contact lines of the dried droplets containing the solute are stuck. Sticking may also occur due to, for example, surface roughness or chemical heterogeneity. It should be noted that deposition of good solvents always results in surface roughness during dissolution. As the solvent evaporates, a capillary flow occurs to replace the solvent that evaporates near the contact line. Because of the large surface-to-bulk ratio near the contact line, more solvent evaporates near the contact line. Capillary flow rates are large compared to conventional diffusion rates. Thus, solutes are transferred to the edges of the droplets, solute deposition occurs only near the rim and not at the center of the droplets being dried (RD Deegan et al., Nature 389, 827 (1997)). Diffusion of solutes tends to encourage homogeneous redeposition of the polymer over the entire area as the solvent dries, rather than forming sidewalls. Capillary flow velocity v (r) is proportional to (where, r:: distance from the center, the radius R of the drops) is (Rr), ^-λ _{(where, λ = (π-2θ c} ) / (2π-2θ c)) Is predicted by theory. Therefore, v increases as lambda increases. In other words, the contact angle θ _c decreases. Thus, the smaller the contact angle, the faster deposition at the edges occurs.

Thus, when forming via holes, (a) the contact lines of the initial droplets are fixed, (b) the contact angles of the droplets on top of the polymer being dissolved are sufficiently small, and (c) the solute diffusion of the polymer is negligible. It is important that the evaporation be fast enough. For IPA on PVP, the contact angle is about 12 ° and the droplets are dried within less than 1 second.

The smaller the contact angle, the faster the rate of capillary flow in the droplet. In other words, the formation of the side walls becomes more certain. On the other hand, however, the smaller the contact angle, the larger the diameter of the droplet. Thus, the optimum contact angle is the angle at which a small diameter via hole with well defined sidewalls can be obtained. In order to obtain a larger contact angle in a good solvent, the surface of the substrate may be treated with, for example, a magnetically bonded monolayer which is highly resistant to penetration of the solvent. The magnetically bonded monolayer may be patterned to provide hydrophobic and hydrophilic surface regions to limit deposition of the solvent to small regions.

The depth and etch rate of the via hole can be controlled by the combination of the number of drops of solvent falling, the deposition frequency and the evaporation rate of the solvent compared to the substrate dissolution rate. The environment in which the deposition takes place and the temperature of the substrate may affect the evaporation rate. Layers of materials that do not dissolve in the solvent or dissolve very slowly may be used to limit the depth of dissolution.

Since the layer of the TFT is configured by alternately arranging the polar layer and the nonpolar layer, the solvent and the solvent combination can be selected so that the etching is stopped at a well defined depth.

A conductor layer may be deposited thereon to extend into the via hole and to be electrically connected to the material at the bottom of the via hole to allow contact through the via hole. FIG. 13A shows a device of the type shown in FIG. 12A but includes a gold electrode 25 formed after forming the via hole as described above.

FIG. 13 shows a curve 30 showing the current voltage characteristics measured between the bottom PEDOT electrode 26 and the conductor electrode 29 deposited on top of the PVP gate insulating layer 28. The diameter of the via hole was 50 μm. For comparison, curve 31 shows the reference sample. In this curve, no via hole is located in the overlap region between the top and bottom electrodes. The characteristic clearly shows that the current through the via hole is several times the leakage current through the gate isolation device without the via hole. The current passing through the measured via hole is limited by the conductivity of the PEDOT electrode, as can be seen by performing the conductivity measurement of the individual PEDOT electrode. Since this is not limited by the resistance of the via hole, only the lower limit of the via hole resistance R _V can be obtained from these measurements: R _V <500 kΩ.

The via hole forming method described above with respect to FIG. 12 can be applied directly to consumable devices that do not have a diffusion barrier (as shown in FIG. 1C) and to devices in which the diffusion barrier is deposited after via holes are formed. FIG. 14A shows a device in which via holes are formed, and then gate electrodes are deposited without interposing a diffusion barrier layer. FIG. 14B shows the device in which the diffusion barrier polymer 7 is formed after the formation of the via hole but before the gate electrode 6 is deposited. In this case, the diffusion barrier layer needs to exhibit good charge transport properties in order to minimize the via hole resistance R _V. A suitable diffusion barrier is a thin TFB layer as shown in FIG. 5A.

If low contact resistance is required, the semiconductor layer can also be removed at the via hole location. This is preferably done after the diffusion barrier is formed. The diffusion barrier 7 and the semiconductor polymer 4 can be dissolved locally by IJP deposition of a good solvent-in this example xylene. By mixing good solvents for both the semiconductor material and the insulating material, both of these layers can be dissolved simultaneously. The device followed by the deposition of the gate electrode is shown in FIG. 14C.

The mixture of solvents can also be used to reduce the diameter of the via holes by increasing the contact angle of the solvent mixture on the layer to be dissolved. Another method of depositing a conductor material to form interconnects after via holes is to deposit locally a material that can locally deform the substrate of the underlying layer to become a conductor. One example is local IJP deposition of a solution containing movable impurities that can diffuse into one or multiple layers. This is illustrated in Figure 14d. Region 32 indicates a material that has been treated with impurities to become a conductor. Impurities may be small conjugated molecules such as triarylamines such as N, N'-diphenyl-N, N'-bis (3-methylphenyl)-(1.1'-biphenyl) -4,4'-diamine (TPD) Can be. Impurities are preferably delivered as in the case of solvents.

A method of forming a via hole through a PVP dielectric layer can be used to connect the gate electrode of a TFT to a source or drain electrode in a lower layer required in a logic inverter device as shown, for example, in FIG. Similar via hole connections are required in most logic transistor circuits. FIG. 16 graphically illustrates the characteristics of an enhancement-load inverter device formed with two normal off transistor devices as in FIG. 15B. Two inverters with different ratios of channel width to channel length ratio (W / L) are shown (graph 35 ratio 3: 1, graph 36 ratio 5: 1). It can be seen that when the input voltage changes from logic low to logic high, it changes from logic high (-20V) to logic low (≒ 0V). The gain of the inverter, that is, the maximum slope of the characteristic is greater than one. This is a necessary condition to allow assembly of more complex circuits such as ring oscillators.

Via holes as described above may also be used to provide electrical connections between interconnect lines in other layers. For complex electronic circuits, multiple levels of interconnect structure are required. This is formed by depositing a series of interconnects 72 and different dielectric layers 70, 71 deposited from compatible solvents (FIG. 15D). The via hole 73 is then formed in the manner described above. The interconnect lines provide automatic etch stops.

Examples of suitable dielectric materials include polar polymers 70 such as PVP and nonpolar dielectric polymers 71 such as polystyrene. They can be deposited alternately from polar and nonpolar solvents. As long as the bottom dielectric layer provides an etch stop layer, the via holes can be formed by local deposition of a good solvent of each dielectric layer.

In selecting the material and deposition process of the device of the type described above, it should be noted that a great advantage can be obtained if each layer is deposited from a solvent that virtually does not dissolve the layer immediately below. In this way, layers can be formed continuously by treatment of the solution. One way to simplify the selection of such materials and process steps is to deposit two or more layers alternately from polar and nonpolar solvents, as illustrated by the continuous layers described above. This makes it easy to form a multilayer device comprising soluble conductor, semiconductor and insulator layers. This avoids the problem of dissolution and expansion of the underlying layer.

The structure, materials, and processes of the devices described above are merely examples for describing the present invention, and thus various modifications are possible.

Device configurations other than the top-gate configuration shown in FIG. 1 may be used. Another configuration is the more standard bottom-gate configuration shown in FIG. 17. If necessary, a diffusion barrier 7 and a surface modification layer 8 may be included. In Fig. 17, similar parts are designated by the reference numerals used in Fig. 1. Other device configurations with different layer order may also be used. Devices other than transistors may be formed in an analog manner.

PEDO / PSS can be replaced with any conductive polymer that can be attached from solution. Examples of such include polyaniline or polypyrrole. However, some of the interesting features of PEDO / PSS include: (a) inherently low diffusible polymeric dopant (PSS), (b) good thermal stability and stability in air, And (c) an operating function of about 5.1 eV well suited to the ionization potential of a common hole transfer semiconductor polymer allowing efficient hole charge carrier injection.

Efficient charge carrier injection is particularly important for short channel transistor devices where the channel length L is less than 10 μm. In such devices, the source drain contact resistance effect can limit the TFT current for small source drain voltages (see FIG. 10B). For devices with significant channel lengths, it has been found that implantation from PEDOT source / drain electrodes is more efficient than implantation from inorganic gold electrodes. This indicates that as the inorganic electrode material, a polymer source-drain electrode having an ionization potential well suited to the ionization potential of a semiconductor is preferable.

The conductivity of PEDOT / PSS attached from aqueous solution [Baytron P] is at a level of 0.1 to 1 S / cm. Higher conductivity with an upper limit of 100 S / cm is achieved by formulations containing mixed solvents (Bayer CCP 105T containing isopropanol and N-methyl-2-pyrrolidone (NMP)). Can be obtained. In the latter case, care should be taken that the solvent combination of the formulation is compatible with the solubility requirements of the layer arrangement. In applications where higher conductivity is required, other conductive polymers, or solution treatable inorganic conductors such as gelatinous suspensions in which the metal inorganic particles remain in a liquid state, may be used.

The processes and devices described herein are not limited to devices made of solution processing polymers. Some of the conductive electrodes and / or interconnections of the TFT in a circuit or display device (see below) may be attached, for example, by printing or electroplating a gelatinous suspension onto a pre-patterned substrate. It can be formed of a conductor. For devices where not all layers are attached from solution, one or more PEDOT / PSS portions of the device may be replaced with poorly soluble conductive material, such as a vacuum deposition conductor.

The semiconductor layer may also be replaced with other solution treatable semiconductor materials. Small conjugated molecules with solubilizing side chains [Journal 120, 664 (1998), American Chemistry Society, Author: J .. G. J. G. Laquindanum et al.], Semiconducting organic-inorganic hybrid materials self-bonded from solution (Science 286, 946 (1999), author: Poem. egg. C. R. Kagan et al., Or solution-attached inorganic semiconductors such as CdSe nanoparticles (Science 286, 746 (1999), author: B.A. It is possible to include Ridley et al.

The electrodes can be patterned by techniques other than ink jet printing. Suitable techniques include soft lithographic printing [Physics Letter 75, 1010 (1999), author: Jay. a. J. A. Rogers et al .; Physics World May 1998, p. 31, author. S. Brittain et al.] Or screen printing (Chemical Material 9, 12999 (1997), author: rat. Z. Bao et al.], Or photolithographic patterning (see International Publication WO 99/10939) or plating, or simple immersion coating of patterned substrates with hydrophobic and hydrophilic surface regions, and the like. Ink jet printing is particularly suitable for patterning large areas, especially rigid plastic substrates, while maintaining good printing consistency.

Such devices may be attached to flexible plastic substrates such as polyethersulfone or other substrate materials such as Perspex (trade name) instead of glass plates. Such a material is preferably in the form of a plate, preferably a polymeric material, and may also be transparent and / or flexible.

While all layers and components of the device and circuit are preferably attached and patterned by solution processing and printing techniques, one or more components, such as semiconductor layers, may be attached by vacuum deposition techniques and / or subjected to photolithographic processes. By patterning.

A device such as a TFT manufactured as described above may be part of a more complex circuit or device in which one or more of these devices are integrated with each other and / or with other devices. Examples of the application device include logic circuits and active matrix circuits for display and memory devices, or user-defined gate array circuits.

The basic component of the logic circuit is the inverter shown in FIG. When all the transistors on the substrate are of the depletion type or the accumulation type, there are three possible configurations. A depletion-load inverter (see FIG. 15A) is suitable for devices that normally turn on (see FIGS. 1C and 3) and an improved load configuration (see FIG. 15B) is used for a normal off transistor (FIG. 15B). 1a, FIG. 1b, FIG. 4). These two configurations require via holes between the gate electrode of the load transistor and each of its power supply and drain electrodes. Another configuration is a resistive load inverter (see FIG. 15C). The latter device can be manufactured by printing a thin and wide PEDOT line with suitable length and conductivity as a load resistor. For example, reducing the conductivity of the PSSPEDOT by increasing the ratio of PSS to PEDOT can minimize the length of the resistor line. The conductivity of the Baytron P PEDOT / PSS with a PEDOT / (PEDOT + PSS) weight ratio of 0.4 was measured at a level of 0.2 S / cm for conventional deposited films. Annealing to 280 ° C. for 20 minutes under N ₂ atmosphere led to an increase in conductivity to 2 S / cm. The conductivity could be reduced to that level by diluting the solution with PSS. When the PEDOT / (PEDOT + PSS) weight ratio was 0.04, the conductivity after annealing at 280 ° C. was measured to be 10 ⁻³ S / cm. A resistor having a resistance of 50 mA was produced by inkjet printing a line of PEDOT having a width of 60 µm and a length of 500 µm.

Other inkjet printing components that have already been developed, such as transistors, via hole interconnects, resistors, capacitors, and multilayer interconnect schemes, may be used to fabricate integrated electronic circuits by a combination of direct printing and solution processing. Can be integrated. Inkjet printing can be used for all processing steps that require side patterning. The simple inverter circuit already described is the building block for more complex logic circuits.

The solution treatment TFT as described above is a liquid crystal (LCD) or electrophoretic display (Nature 394, 253 (1998), author: B., in which a suitable circuit is shown in Fig. 18A). An active matrix display such as B. Comiskey et al. And a suitable circuit are shown in FIG. 18B (Science 280, 1741 (1998), author: H. C.). H. Sirrinhaus et al.] Or as an active matrix addressing element of a memory device such as random access memory (RAM). 18A and 18B, transistors T1 and T2 may be formed with transistors as described above. Reference numeral 40 denotes a display or memory element with current and voltage supply pads.

An example of a possible device configuration for controlling the voltage on an electrode of an LCD or electrophoretic display is shown in FIG. 19, in which the same elements as in FIG. 1 are given the same reference numerals. In the relevant drawings of FIG. 19 (eg, FIGS. 7, 14, 17), the gate insulating layer may include a multilayer structure including a diffusion barrier and / or a surface modification layer as in FIG. 1A.

Referring to Fig. 18, the power supply and gate electrodes 2 and 3 of the TFT are composed of the data line 43 and the addressing line of the active matrix, which can be made of different conductive materials to obtain proper conductivity over a longer length. 44). The drain electrode 3 of the TFT may be the pixel electrode 41. The pixel electrode may be formed of another conductive material as in FIG. 19. In devices that depend on the application of an electric field rather than charge carrier injection, the electrode 41 need not be in direct contact with the display element 40, such as liquid crystal or electrophoretic ink. In such a configuration, the total pixel area occupied by the TFT and the interconnect line must be kept small so that an appropriate aperture ratio can be obtained and the signals and display on the data line 43 and the addressing line 44 can be obtained. Potential crosstalk between devices 40 can be reduced.

The configuration of Fig. 19B is more complicated. However, the entire pixel or most of the pixel area can be used for the TFT and the interconnect line, and the display element is shielded from the signal on the data line 43 and the addressing line 44 by the pixel electrode 41. In manufacturing such a configuration, a via hole filled with an additional dielectric layer 42 and a conductive material 45 is required to connect the pixel electrode 41 to the TFT drain electrode 3. Via holes may be manufactured by the procedure as described above.

In such a configuration, the aperture ratio may be minimized or may be nearly 100%. This configuration can also be used for display application devices with a backlight, such as a transmissive LCD display, since all polymer TFTs as manufactured herein have high transparency in the visible spectral region. FIG. 20 shows the optical absorption spectrum measured on the F8T2 polymer TFT, wherein the polymer chains are uniaxially aligned by attaching the liquid crystal semiconductor polymer on a friction polyimide alignment layer which also serves as a pre-patterned layer for high resolution printing. It can be seen that the device is very transparent in most visible spectral regions because of the relatively high band gap of F8T2. If a semiconductor layer with a larger band gap is used, such as F8 or TFB or other polyfluorene derivatives (see US Pat. No. 5,777,070), even better transparency can be achieved. The alignment of the polymer chains provides optical anisotropy, such that light polarized parallel to the alignment direction (shown by the "" mark) is absorbed more strongly than light polarized perpendicularly to the alignment direction (shown by the "⊥" mark). Cause. Optical anisotropy can be used in LCD displays to further increase the optical transparency of the TFT by orienting the alignment direction of the polymer chain perpendicular to the polarizing prism between the glass backside and the backlight. Under the polarized state, when the thickness of the F8T2 layer is 500 mW or less, the transistor device appears mostly colorless in visible light. All other layers of the TFT including PEDOT have low optical absorption in the visible spectral region.

Another advantage of low optical absorbance semiconductor devices is that the photosensitive characteristics of the TFTs are reduced to visible light. In the case of amorphous silicon TFTs, a black matrix must be used to prevent large OFF currents under light illumination. In the case of a polymer TFT semiconductor with a wide band gap, it is not necessary to protect the TFT from ambient light and the backlight of the display.

The configuration of Fig. 19B is suitable for the driving transistor T1 (see Fig. 18B) of the LED display because the source drain electrode having the large channel width W using the entire area under the pixel electrode 41 is used. This is because the driving current of the TFTs can be increased by manufacturing them in an interlocking arrangement.

Alternatively, the bottom gate TFT configuration of FIG. 17 can be used in all of the above applications (see FIG. 19C).

One of the important technical issues in the fabrication of an active matrix circuit is the contact between the PEDOT / PSS TFT and pixel electrodes 2, 3, 6 and the metal interconnect lines 43, 44, 41. Due to the strongly acidic nature, PEDOT / PSS is incompatible with many common inorganic metals such as aluminum. Aluminum easily oxidizes in contact with PEDOT / PSS. One possible solution is to fabricate the interconnect lines and pixel electrodes 43, 44, 41 with indium tin-oxide (ITO) or tantalum, tungsten, and refractory metals or other materials that are more stable in these environments. Or use an appropriate barrier layer.

When applied to a display, it is also preferable to manufacture a TFT having a short channel length by printing on the prepatterned substrate indicated by reference numeral 10 in FIG. 19 as described above.

If the pixel elements to be controlled are not only display elements but also memory elements such as capacitors or diodes, for example in dynamic random access memories, similar device configurations for active matrix transistor switches can also be used.

In addition to the conductive electrodes, some other layers of TFTs can also be patterned by screen printing or direct printing techniques such as IJP. FIG. 21A (in this figure with the same reference numerals as for FIG. 1) shows a device in which the active layer islands of the semiconductor layer 4 and the gate insulating layer 5 are printed directly. In this case, the via hole is not necessary, but the connection portion can be formed by direct printing of the appropriate gate electrode pattern 6. A thick island of dielectric polymer 46 can be printed to provide electrical insulation when the addressing or interconnect lines 43, 44 overlap (see FIG. 21 (b)).

Multiple devices formed as described above may be formed on one substrate and interconnected by conductive layers. The devices may be formed on one level or above one or more levels, while some devices may be formed on top of other levels. The use of interconnect strips and via holes as described above results in a particularly compact circuit structure.

The technology developed in the present invention for the manufacture of inkjet printing transistors, via holes, and interconnect lines can be used to fabricate integrated electronic circuits by inkjet printing. Prefabricated substrates comprising rows of hydrophilic and hydrophobic surface regions can be used to define the channel length of the transistor and / or the width of the interconnect line. The substrate may also include a row of highly conductive metal interconnect lines. Using a combination of ink jet printing and the attachment of a continuous layer from solution, the rows of transistor devices are partitioned by order channel width at order locations. Integrated circuits are then fabricated by forming electrical connections between pairs of transistors and appropriate interconnects using inkjet printing of via holes and conductive lines.

It is also possible for the prefabricated substrate to already include one or more components of the transistor device. The substrate may include, for example, a row of completed inorganic transistor devices each having at least one exposed electrode. In this case, inkjet manufacturing of the integrated circuit includes forming an electrical connection between the pair of transistors and one or multiple levels of interconnection scheme using inkjet printing via holes, interconnect lines, and blocking pads (see FIG. 15D). .

In addition to transistor devices, electronic devices include other active and passive circuit elements such as display or memory elements or capacitive or resistive elements.

The technique as described above can be used to form a unit with a plurality of transistors, which can then be formed for a particular subsequent use through solution based processing. For example, a substrate including a plurality of transistors 50 in the form shown in FIG. 1A, 1B, or 1C as an example of a gate array may be formed on a plastic plate (see FIG. 22). Other devices such as diodes or capacitors can also be formed on the plastic plate. The plate then has an ink having a suitable solvent for forming the via holes 52 (for example methanol) and a printing head for forming a conductive track 53 and a suitable material for filling the via holes (for example PEDOT). Place in a jet printer. Ink jet printers have knowledge of the position and configuration of transistors on a plate and can operate under the control of a properly programmed computer. Subsequently, by a combination of the via hole forming step and the interconnecting step, the ink jet printer interconnects the transistors in a predetermined manner, thereby forming a circuit for performing a predetermined electronic or logic function. This technique thus allows logic specific circuitry to be formed on a substrate even using small, inexpensive devices.

Applications of such circuits include the printing of active electronic tickets, luggage, and identification tags. The ticket or tag printing device is equipped with a plurality of non-configured units, each containing a substrate supporting a plurality of transistors. The ticket printing device includes a computer capable of controlling the inkjet printer as described above and displaying the valid function of the ticket. If printing of the ticket is necessary, the printing device forms a substrate for a suitable electronic circuit by printing via holes and / or conductive materials, whereby a transistor on the substrate is appropriately formed. The substrate can then be sealed and covered with an adhesive plastic sheet, for example, leaving the electrical connection terminals 54 and 55 exposed. The ticket is then distributed. When attempting to validate a ticket, input values are applied to one or more input terminals and the output values on one or more output terminals are monitored to validate the function. The ticket is preferably printed on a flexible plastic substrate for convenient use.

User-defined circuits that are not for price and tagging can also be manufactured in a similar manner. Validation and reading of the circuit can also be accomplished by remote metering using, for example, radio frequency radiation (Physics World, March 1999, page 31).

Simply ink jet printing of the appropriate connections onto a standard array gives the end user the ability to define the circuit, providing significantly increased flexibility over factory design circuits.

The present invention is not limited to the above embodiments. Features of the invention include all new and advanced features of the concepts described herein and all new and advanced combinations of those features described herein.

The Applicant intends to note that the present invention implicitly, explicitly, or generally includes any or any combination of the features disclosed herein without being limited to the scope of any limitations set forth above. do. In view of the above description, it will be apparent to those skilled in the art that various modifications can be made within the scope of the present invention.

Claims (112)

In the transistor forming method comprising a transistor layer and a semiconductor layer, Depositing a first material from a solution in the first solvent to form a first layer of the transistor; And And depositing a second material from a solution in a second solvent on the first material to form a second layer of the transistor, The first substance is soluble in the first solvent, but not soluble in the second solvent, And the first layer of the transistor is one of a gate insulating layer and the semiconductor layer, and the second layer of the transistor is the other of the gate insulating layer and the semiconductor layer. The method of claim 1, Depositing a third material from a solution in a third solvent on the second material to form a third layer of the transistor, Wherein the second material is soluble in the second solvent, but not soluble in the third solvent. The method of claim 1, One of the first solvent and the second solvent is a polar solvent, the other is a non-polar solvent forming method. delete The method of claim 2, The second material is a dielectric material, Wherein one of the first material and the third material is a semiconductor material and the other is a conductive material. The method of claim 1, Wherein one of the first and second layers is a nonpolar polymer layer soluble in a nonpolar solvent, and the other layer is a polar polymer layer soluble in a polar solvent. The method of claim 6, The interaction parameter (D) for the nonpolar polymer and the polar solvent is 5 or more. The method of claim 6, The interaction parameter (D) for the nonpolar polymer and the polar solvent is 10 or more. The method of claim 6, The interaction parameter (D) for the nonpolar polymer and the polar solvent is 15 or more. The method of claim 6, The interaction parameter (D) for the polar polymer and the nonpolar solvent is 5 or more. The method of claim 6, The interaction parameter (D) for the polar polymer and the nonpolar solvent is 10 or more. The method of claim 6, The interaction parameter (D) for the polar polymer and the nonpolar solvent is 15 or more. The method of claim 3, wherein One of the second solvent and the third solvent is a polar solvent, the other is a non-polar solvent. The method of claim 2, The second solvent is a moderately polar solvent containing polar and nonpolar groups, Wherein one of the first solvent and the third solvent is a highly polar solvent containing only a polar group. The method of claim 14, The second layer is a normal polar polymer layer soluble in the normal polar solvent, Wherein one of the first and third layers is a nonpolar polymer layer and the other is a polar polymer layer. The method of claim 15, And the interaction parameter (D) for the non-polar polymer and the solvent of normal polarity is 5 or more. The method of claim 15, The interaction parameter (D) for the non-polar polymer and the solvent of normal polarity is 10 or more. The method of claim 15, The interaction parameter (D) for the non-polar polymer and the solvent of normal polarity is 15 or more. The method of claim 15, The interaction parameter (D) for the polar polymer and the solvent of the normal polarity is 5 or more. The method of claim 15, The interaction parameter (D) for the polar polymer and the solvent of the normal polarity is 10 or more. The method of claim 15, The interaction parameter (D) for the polar polymer and the solvent of the normal polarity is 15 or more. The method of claim 14, And said common polar solvent is an alcohol. The method of claim 14, The method of forming a transistor, wherein the solvent of the usual polarity is acetate. The method of claim 2, The first layer is soluble in a nonpolar solvent, And said second layer is an isolation layer soluble in a solvent of moderate polarity containing hydrophilic and hydrophobic groups. The method of claim 24, And the third layer is soluble in a polar solvent. The method of claim 24, And the third layer is soluble in a nonpolar solvent. The method of claim 24, And the second layer is an active layer of the transistor. delete delete The method of claim 1, And the semiconductor layer comprises a conjugated polymer. The method of claim 1, The semiconductor layer is a transistor forming method, characterized in that it comprises a conjugated block copolymer (conjugated block copolymer). The method of claim 1, The semiconductor layer has a block copolymer having an electron affinity of at least 3.0 eV or 3.5 eV, Wherein said block copolymer comprises a first block of conjugated monomer units each connected by at least two covalent bonds, and a second block of monomer units. The method of claim 1, The semiconductor layer has a block copolymer having an ionization potential in the range of 5.5 eV to 4.9 eV, Wherein said block copolymer comprises a first block of conjugated monomer units each connected by at least two covalent bonds, and a second block of monomer units. The method of claim 33, wherein The first block of conjugated monomer units comprises one or more groups comprising a fluorene derivative, a phenyline derivative and an indenofluorene derivative, And the second block of monomer units comprises one or more groups comprising a thiophene derivative, a triarylamine derivative and a benzothiadiaxole derivative. The method of claim 1, And the semiconductor layer is F8T2 or TFB. The method of claim 1, And the semiconductor layer comprises a liquid crystal conjugated polymer. The method of claim 36, And heating the liquid crystal conjugated polymer to a liquid crystal state. The method of claim 36, And uniaxially aligning the liquid crystal conjugated polymer. The method of claim 38, Aligning the liquid crystal conjugated polymer comprises depositing the liquid crystal conjugated polymer on a layer having an aligned molecular structure. The method of claim 39, Mechanically rubbing the layer to align the molecular structure of the layer. The method of claim 39, Optically treating the layer to align the molecular structure of the layer. The method of claim 1, And the semiconductor layer has a bandgap of 2.3 eV or more and is optically transparent. The method of claim 1, And the semiconductor layer has an ionization potential of 4.9 eV or more. The method of claim 1, And the semiconductor layer has an ionization potential of 5.1 eV or more. The method of claim 1, And the semiconductor layer has an electron affinity of 3.0 eV or more. The method of claim 1, And said semiconductor layer has an electron affinity of at least 3.5 eV. delete The method of claim 1, The transistor further comprises an isolation layer between the gate electrode layer and the gate insulating layer. 49. The method of claim 48 wherein And the isolation layer is a diffusion barrier layer. The method of claim 49, And wherein said diffusion barrier layer comprises a nonpolar polymer. The method of claim 49, Wherein said diffusion barrier layer comprises a nonpolar conjugated polymer. The method of claim 49, And the diffusion barrier layer comprises a polyfluorene derivative. The method of claim 52, wherein Wherein said polyfluorene derivative is F8, F8T2 or TFB. 49. The method of claim 48 wherein And the isolation layer is a surface modification layer. The method of claim 1, Modifying the surface of the first layer prior to depositing the second layer. The method of claim 55, Wherein the surface modification of the first layer is to provide a contact angle greater than 0 ^{o and no} greater than 100 ^o to deposit the second material on the first layer. The method of claim 55, Wherein the surface modification of the first layer is to provide a contact angle greater than 0 ^{o and no} greater than 80 ^o to deposit the second material on the first layer. The method of claim 55, Wherein the surface modification of the first layer is to provide a contact angle greater than 0 ^{o and no} more than 60 ^o to deposit the second material on the first layer. The method of claim 55, Deforming the surface of the first layer comprises treating the surface of the first layer. The method of claim 55, And modifying the surface of the first layer comprises depositing a surface modification material on the surface of the first layer. The method of claim 60, And the surface modification material is deposited from a solution in a solvent of normal polarity. The method of claim 2, The first layer is deposited on a substrate, And heating the substrate prior to depositing the second or third layer. The method of claim 2, At least one of the first layer and the second layer is formed by inkjet printing. The method of claim 63, wherein At least one of a source, a drain, or a gate electrode of the transistor is formed by the inkjet printing. The method of claim 1, And the transistor comprises a source, drain or gate electrode formed of a conductive polymer. 66. The method of claim 65, And the electrode is formed of an optically transparent conductive polymer. 66. The method of claim 65, Wherein the conductive polymer comprises a polymeric counterion dopant. The method of claim 1, Wherein the material of one of the first and second layers is PEDOT / PSS. The method of claim 1, And the gate insulating layer is formed of a nonconjugated or partially conjugated polymer. The method of claim 69, Wherein the gate insulating layer comprises hydrophilic and hydrophobic groups and is soluble in a solvent of normal polarity. The method of claim 1, And the material of one of said first and second layers is PVP. A first layer soluble in the first solvent; And A second layer adjacent to the first layer and soluble in a second solvent in which the first material is not soluble; And the first layer is one of a semiconductor layer and a gate insulating layer, and the second layer is another one of the semiconductor layer and the gate insulating layer. The method of claim 72, And a third layer adjacent to the second layer and soluble in a third solvent in which the second material is not soluble. The method of claim 72, Wherein said one of said first and second layers comprises a polar polymer soluble in a polar solvent and the other is a nonpolar polymer soluble in a nonpolar solvent. The method of claim 73, wherein Wherein said one of said second and third layers comprises a polar polymer soluble in a polar solvent and the other is a nonpolar polymer soluble in a nonpolar solvent. The method of claim 73, wherein One of said solvents is an alcohol. delete delete The method of claim 72, And the material forming the semiconductor layer is a polyfluorene derivative. The method of claim 72, The semiconductor layer has a bandgap of 2.3 eV or more and is optically transparent. The method of claim 72, And the semiconductor layer has an ionization potential of 4.9 eV or more. The method of claim 72, And the semiconductor layer has an ionization potential of 5.1 eV or more. The method of claim 72, The semiconductor layer has a block copolymer having an electron affinity of at least 3.0 eV or 3.5 eV, Wherein said block copolymer comprises a first block of conjugated monomer units each connected by at least two covalent bonds, and a second block of monomer units. The method of claim 72, The semiconductor layer has a block copolymer having an ionization potential in the range of 5.5 eV to 4.9 eV, Wherein said block copolymer comprises a first block of conjugated monomer units each connected by at least two covalent bonds, and a second block of monomer units. 84. The method of claim 83 wherein The first block of conjugated monomer units comprises one or more groups comprising a fluorene derivative, a phenyline derivative and an indenofluorene derivative, And the second block of monomer units comprises one or more groups comprising a thiophene derivative, a triarylamine derivative and a benzothiadiazole derivative. 80. The method of claim 79 wherein The polyfluorene derivative is a transistor, characterized in that F8T2 or TFB. The method of claim 72, And the semiconductor layer has an ionization potential of 4.9 eV or more. The method of claim 72, And the semiconductor layer has an ionization potential of 5.1 eV or more. delete The method of claim 73, wherein And the transistor further comprises an isolation layer between the gate electrode layer and the gate insulating layer. 92. The method of claim 90, And the isolation layer is a diffusion barrier layer. 92. The method of claim 91 wherein And the diffusion barrier layer comprises a polyfluorene derivative. 93. The transistor of claim 92 wherein the polyfluorene derivative is F8T2 or TFB. 92. The method of claim 90, And the isolation layer is a surface modification layer. The method of claim 72, The first or second layer is formed by inkjet printing. The method of claim 73, wherein And the third layer is formed by inkjet printing. delete The method of claim 72, And the material of one of said first and second layers is PEDOT / PSS. The method of claim 72, And wherein the material of one of said first and second layers is PVP. The method of claim 72, And the transistor is optically transparent. The method of claim 72, The transistor is a thin film transistor. A logic circuit comprising the transistor of any of claims 72-76, 79-88, 90-96, 98-101. 99. An apparatus comprising an active matrix array of a plurality of transistors according to any one of claims 72-76, 79-88, 90-96, 98-101. Logic circuit. A display comprising a plurality of display elements, At least one of the display elements is switched by a transistor according to any one of claims 72 to 76, 79 to 88, 90 to 96 and 98 to 101. , And said transistor is an optically transparent thin film transistor. 105. The method of claim 104, And the transistor is located behind the display element. 105. The method of claim 105, The display element comprises an optically active area switchable by the transistor, And wherein the transistor is electrically coupled to the optically active region by a conductive material located in a via hole formed through at least one layer of the transistor. A display comprising the transistor of any of claims 72-76, 79-88, 90-96, 98-101. A memory device comprising the transistor of any of claims 72-76, 79-88, 90-96, 98-101. 99. An apparatus comprising an active matrix array of a plurality of transistors according to any one of claims 72-76, 79-88, 90-96, 98-101. Display. 99. An apparatus comprising an active matrix array of a plurality of transistors according to any one of claims 72-76, 79-88, 90-96, 98-101. Memory device. delete delete

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