KR20020058369A - array panel of liquid crystal display and manufacturing method thereof - Google Patents

Abstract

PURPOSE: An array substrate of a liquid crystal display and a method of fabricating the array substrate are provided to reduce the number of fabrication processing steps and to prevent poor products from being manufactured. CONSTITUTION: An array substrate of a liquid crystal display includes a plurality of gate lines formed on a substrate(110), a gate electrode connected to each gate line, a gate pad placed at one end of each gate line, and a gate link(124) connecting the gate line and the gate pad. The array substrate further includes a semiconductor layer formed on a gate insulating layer(130), and an ohmic contact layer formed on the semiconductor layer. The array substrate further has a data line that is formed on the ohmic contact layer and intersects each gate line to define a pixel region, source and drain electrodes, and a data pad located at one end of the data line. The array substrate further includes a passivation layer that is formed on the data line, source and drain electrodes and has a contact hole exposing a portion of the drain electrode, a pixel electrode formed at the pixel region and connected to the drain electrode through the contact hole, and a protection pattern(184) placed on the gate insulating layer to cover the gate link. The semiconductor layer has the same shape as the shape of the data line, source and drain electrodes. The semiconductor layer and the passivation layer have the same shape.

Description

Array substrate for liquid crystal display device and manufacturing method thereof

The present invention relates to an array substrate for a liquid crystal display device and a method of manufacturing the same.

In general, a liquid crystal display device arranges two substrates on which electrodes are formed so that the surfaces on which the two electrodes are formed face each other, injects a liquid crystal material between the two substrates, and applies a voltage to the two electrodes to generate an electric field. By moving the liquid crystal molecules, the image is expressed by the transmittance of light that varies accordingly.

Liquid crystal displays may be formed in various forms. Currently, an active matrix LCD (AM-LCD) having a thin film transistor and pixel electrodes connected to the thin film transistors arranged in a matrix manner has excellent resolution and video performance. It is most noticed.

The liquid crystal display has a structure in which a pixel electrode is formed on a lower array substrate and a common electrode is formed on a color filter substrate, which is an upper substrate, and drives liquid crystal molecules by an electric field in a direction perpendicular to an up and down substrate. to be. This is excellent in characteristics such as transmittance and aperture ratio, and the common electrode of the upper plate serves as a ground, thereby preventing the destruction of the liquid crystal cell due to static electricity.

The upper substrate of the liquid crystal display may further include a black matrix to prevent light leakage occurring in portions other than the pixel electrode.

The array substrate, which is a lower substrate of the liquid crystal display, is formed by repeatedly depositing a thin film and performing a photolithography process using a mask several times. Typically, 5 to 6 masks are used, and the number of masks is an array substrate. Represents the number of processes to manufacture.

Hereinafter, a conventional array substrate for a liquid crystal display device and a method of manufacturing the same will be described with reference to the accompanying drawings.

1 is a plan view of a conventional array substrate for a liquid crystal display device, and FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1.

1 and 2, in the array substrate for a liquid crystal display device, a gate wiring 21 having a horizontal direction on the transparent insulating substrate 10, a gate electrode 22 extending from the gate wiring 21, The gate pad 23 located at one end of the gate wiring 21 is formed.

The gate insulating layer 30 is formed on the gate wiring 21, the gate electrode 22, and the gate pad 23, and the active layer 41 and the ohmic contact layers 51 and 52 are sequentially formed thereon. have.

On the ohmic contact layers 51 and 52, the data line 61 orthogonal to the gate line 21, the source electrode 62 extending from the data line 61, and the source electrode 62 around the gate electrode 22. The drain electrode 63 and the data pad 64 positioned at one end of the data line 61 are formed to face each other.

The data line 61, the source and drain electrodes 62 and 63, and the data pad 64 are covered with a protective layer 70, and the protective layer 70 is together with the gate insulating layer 30 and the drain electrode 63. And first to third contact holes 71, 72, and 73 exposing the gate pad 23 and the data pad 64, respectively.

Next, the pixel electrode 81, the auxiliary gate pad 82, and the auxiliary data pad 83 made of a transparent conductive material are formed on the passivation layer 70. The pixel electrode 81 is positioned in the pixel area defined by the gate line 21 and the data line 61 intersecting, and is connected to the drain electrode 62 through the first contact hole 71, and part of the gate electrode 81 is connected to the drain electrode 62. The storage capacitor overlaps with the wiring 21 to form a storage capacitor. The auxiliary gate pad 82 and the auxiliary data pad 83 are connected to the gate pad 23 and the data pad 64 through the second and third contact holes 72 and 73, respectively.

3A to 3E illustrate a manufacturing process of such an array substrate for a liquid crystal display, and correspond to a cross section taken along line II-II of FIG. 1. Next, a method of manufacturing a conventional array substrate for a liquid crystal display device will be described with reference to FIGS. 3A to 3E.

As shown in FIG. 3A, a metal material is deposited on the substrate 10 and patterned using a first mask to form the gate wiring 21, the gate electrode 22, and the gate pad 23.

Next, as shown in FIG. 3B, the gate insulating layer 30, amorphous silicon, and amorphous silicon containing impurities are sequentially deposited, and then the active layer 41 and the impurities are subjected to a photolithography process using a second mask. The semiconductor layer 53 is formed.

Subsequently, as shown in FIG. 3C, a metal layer is deposited and patterned using a third mask, thereby forming a data line (61 of FIG. 1), a source electrode 62, a drain electrode 63, and a data pad 64. The impurity semiconductor layer 53 exposed between the source electrode 62 and the drain electrode 63 is etched to complete the ohmic contact layers 51 and 52.

Next, as shown in FIG. 3D, the protective layer 70 is deposited and the protective layer 70 and the gate insulating film 30 are patterned by using a fourth mask, whereby the drain electrode 63 and the gate pad 23 and First to third contact holes 71, 72, and 73 respectively exposing the data pads 64 are formed.

Next, as illustrated in FIG. 3E, the pixel electrode 81, the auxiliary gate pad 82, and the auxiliary data pad 83 are formed by depositing a transparent conductive material and performing a photolithography process using a fifth mask.

As described above, an array substrate may be manufactured by a photolithography process using five masks. The photolithography process involves various processes such as cleaning, photoresist coating, exposure and development, and etching. Therefore, even if the photolithography process is shortened only once, manufacturing time can be considerably reduced, manufacturing cost can be reduced, and defect occurrence rate is reduced. Therefore, it is desirable to manufacture an array substrate by reducing the number of masks.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide an array substrate for a liquid crystal display device and a method of manufacturing the same, which can reduce a manufacturing process and prevent defects.

1 is a plan view of an array substrate for a general liquid crystal display device.

FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1. FIG.

3A to 3E are cross-sectional views showing a process of manufacturing a conventional array substrate for a liquid crystal display device.

4 is a plan view of an array substrate for a liquid crystal display according to a first embodiment of the present invention.

FIG. 5 is a cross-sectional view taken along the line VV of FIG. 4. FIG.

6A-6E are cross-sectional views illustrating a process of fabricating an array substrate in accordance with the present invention.

7 is a plan view of an array substrate for a liquid crystal display according to a second embodiment of the present invention.

FIG. 8 is a cross-sectional view taken along the line VII-VII of FIG. 7. FIG.

9 is a cross-sectional view illustrating a case where disconnection occurs in the gate link unit in the present invention.

10 is a cross-sectional view of a gate link portion of an array substrate according to a third embodiment of the present invention.

In the array substrate for a liquid crystal display device according to the present invention for achieving the above object, a plurality of gate wirings and gate electrodes connected to the gate wirings, gate pads located at one end of the gate wirings, and gate wirings and gates on the substrate. A gate link portion connecting the pad is formed. A gate insulating film is formed thereon and covers them, and the gate insulating film has an opening that partially exposes the gate pad. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer, and a data wiring defining a pixel region intersecting with the gate wiring, a source electrode extending from the data wiring, a drain electrode positioned opposite the source electrode, and data A data pad located at one end of the wiring is formed. A protective layer having a contact hole exposing a part of the drain electrode is formed on the data line and the source and drain electrodes. Next, a pixel electrode connected to the drain electrode through the contact hole is formed in the pixel area, and a protective pattern covering the gate link part is formed on the gate insulating layer. Here, the semiconductor layer has the same shape as the data line and the source and drain electrodes except between the source and drain electrodes, and has the same shape as the protective layer.

In the present invention, the protective pattern may be made of the same material as the pixel electrode, or may be made of the same material as the protective layer.

Meanwhile, in the method of manufacturing a liquid crystal display device according to the present invention, a gate electrode including a substrate and connected to a plurality of gate wires and gate wires on the substrate, a gate pad positioned at one end of the gate wire, and a gate wire and a gate pad Form a gate link portion connecting the. Subsequently, a gate insulating film, an amorphous silicon layer, an impurity amorphous silicon layer, and a metal layer are sequentially deposited on the gate wiring, and then the metal layer and the impurity amorphous silicon are patterned to intersect with the gate wiring to define a pixel region in the data wiring and data wiring. An extended source electrode, a drain electrode positioned opposite the source electrode, a data pad positioned at one end of the data line and an ohmic contact layer are formed. Next, an insulating material is deposited on the substrate on which the data line is formed, and patterned together with the semiconductor layer to form a protective layer and an active layer. Next, a protective pattern covering the gate link part is formed on the gate insulating layer, and a pixel electrode connected to the drain electrode is formed in the pixel region through the contact hole.

Here, the protective pattern may be formed in the same process as the pixel electrode, or may be formed in the same process as the protective layer.

As described above, in the present invention, when the protective layer and the active layer are formed in the same process to reduce the manufacturing process, when the protective layer is not formed on the gate link portion, a protective pattern covering the gate link portion is formed to form a pixel electrode etchant. The disconnection of the gate link portion can be prevented.

Hereinafter, an array substrate for a liquid crystal display device and a manufacturing method thereof according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

First, FIG. 4 is a plan view of an array substrate for a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 5 is a cross-sectional view taken along the line VV of FIG. 4.

As shown in FIGS. 5 and 6, the gate wiring 121 and the gate electrode 122 extending from the gate wiring 121 in one direction on the substrate 110 and positioned at one end of the gate wiring 121 are positioned. The gate pad 123 is formed.

A gate insulating layer 130 formed of a silicon nitride film (SiN _x ) or a silicon oxide film (SiO ₂ ) is formed on the entire surface of the substrate 110 on the gate wiring 121 to form the gate wiring 121, the gate electrode 122, and the gate pad. The gate insulating layer 130 may cover the first and second gates 123 and 123 to expose the gate pad 123.

Next, an active layer 141 made of amorphous silicon is formed on the gate insulating layer 130, and ohmic contact layers 151 and 152 made of amorphous silicon containing impurities are formed thereon.

The data line 161, the source and drain electrodes 162 and 163, and the data pad 164 are formed on the ohmic contact layers 151 and 152. The data line 161 defines a pixel area orthogonal to the gate line 121, the source electrode 162 extends from the data line 161, and the drain electrode 163 is separated from the source electrode 162. The data pad 164 is positioned at one end of the data line 161 to face the source electrode 162 with respect to the gate electrode 122, and receives an image signal from an external driving circuit.

Here, the ohmic contact layers 151 and 152 have the same shape as the data line 161, the source and drain electrodes 162 and 163, and the data pad 164.

Next, a passivation layer 171 is formed on the data line 161, the source and drain electrodes 162 and 163, and the data pad 164 to cover the passivation layer 171. The second and third contact holes 172 and 173 respectively expose the data pad 164. Here, the protective layer 171 has the same shape as the active layer 141, and the active layer 141 has the data line 161, the source and drain electrodes 162 except between the source and drain electrodes 162 and 163. , 163, and the data pad 164.

The protective layer 171 is removed from the pad portion where the gate pad 123 is located.

Next, a pixel electrode 181 made of a transparent conductive material is formed in the pixel area, and an auxiliary gate pad 182 and an auxiliary data pad 183 are formed on the gate pad 123 and the data pad 164, respectively. have. The pixel electrode 181 is connected to the drain electrode 163 through the second contact hole 172, and partially overlaps the gate wiring 121 to form a storage capacitor. Meanwhile, the auxiliary gate pad 182 contacts the gate pad 123 through the first contact hole 131 of the gate insulating layer 130, and the auxiliary data pad 183 receives data through the third contact hole 173. It is in contact with the pad 164.

Here, the storage capacitor is formed using only the pixel electrode 181 and the gate wiring 121, but a capacitor electrode overlapping the gate wiring 121 is formed of the same material as the data wiring 161, and the capacitor electrode and the pixel electrode 181 are formed. By connecting, you can increase the capacity of the storage capacitor. In this case, an amorphous silicon layer and an impurity amorphous silicon layer are positioned under the capacitor electrode.

A manufacturing process of such an array substrate for a liquid crystal display will be described in detail with reference to FIGS. 6A to 6E.

First, as illustrated in FIG. 6A, a metal material is deposited on the transparent substrate 110 and patterned by using a first mask, thereby forming the gate wiring 121, the gate electrode 122, and the gate pad 123 in one direction. Form.

Subsequently, as shown in FIG. 6B, the gate insulating layer 130 formed of the silicon nitride film or the silicon oxide film, the amorphous silicon layer 140, and the amorphous silicon layer doped with impurities are sequentially deposited, and then the metal layer is deposited by sputtering. The photoresist is coated and patterned with a second mask to form data lines (161 of FIG. 5), source and drain electrodes 162 and 163, data pads 164, and ohmic contact layers 151 and 152.

Next, as shown in FIG. 6C, a protective layer 170 is formed by depositing a silicon nitride film, a silicon oxide film, or an organic insulating film, and then applying a photoresist film, exposing with a third mask, and developing the photoresist film patterns 191 and 192. To form.

Here, the third mask includes a quartz substrate 210, a light blocking film 230 that completely blocks the light formed thereon, and a semi-transmissive film 220 that transmits only part of the light. Both the transflective film 220 and the light blocking film 230 are formed in the region A corresponding to the portion where the protective layer 170 remains in the third mask, and the contact holes 131, 172, and 173 are formed. Both layers do not exist in the region C corresponding to the portion to be formed, and only the transflective layer 220 is formed in the region B corresponding to the remaining portion. Accordingly, the photoresist patterns 191 and 192 developed after exposure with the third mask have a first thickness in the A region, a second thickness smaller than the first thickness in the B region, and all of the photoresist patterns are removed in the C region. have.

Next, as illustrated in 6d, the photoresist patterns 191 and 192, the protective layer 170, the amorphous silicon layer 140, and the gate insulating layer 130 are patterned to form the protective layer 171 and the active layer 141. The first to third contact holes 131, 172, and 173 are formed.

Subsequently, as illustrated in FIG. 6E, a transparent conductive material such as indium-tin-oxide (ITO) is deposited and patterned by a photolithography process using a fourth mask to form the pixel electrode 181, the auxiliary gate pad 182, and the auxiliary. The data pad 183 is formed. The pixel electrode 181 is connected to the drain electrode 163 through the second contact hole 172 and partially overlaps the gate wiring 121.

Here, the auxiliary gate pad 182 and the auxiliary data pad 183 may be omitted to protect the pad.

As described above, in the present invention, an array substrate may be manufactured using four masks, thereby reducing manufacturing processes and costs.

In the array substrate according to the present invention, only the gate insulating layer 130 is positioned on the gate link portion L to which the gate pad 123 and the gate wiring 121 of the pad part are connected.

However, in the array substrate, a pin hole may occur when the gate link portion L is formed, which weakens the gate link portion L and subsequently gates when etching to form the pixel electrode 181. Since only the gate insulating layer 130 is positioned on the upper portion L, the etchant penetrates into the portion weakened by the pinhole, and disconnection of the gate link portion L occurs.

Therefore, in order to prevent such a problem, in the second embodiment of the present invention, a protective pattern made of the same material as the pixel electrode is formed on the gate link part when the pixel electrode is formed.

7 and 8 show a second embodiment of this invention.

7 is a plan view of an array substrate according to a second exemplary embodiment of the present invention, and FIG. 8 is a cross-sectional view taken along the line VII-VII of FIG. 7.

Here, since the second embodiment has the same structure and manufacturing method as the first embodiment except for the gate link portion, the description of the same parts will be omitted.

As shown in FIGS. 7 and 8, a gate insulating layer 130 is formed on the gate link portion 124 positioned between the gate pad 123 and the gate wiring 121, and the pixel electrode 181 is disposed thereon. A protective pattern 184 made of a transparent conductive material such as is formed. The protection pattern 184 covers the gate link part 124, thereby preventing the etchant used to form the pixel electrode 181 from penetrating into the gate link part 124 through the gate insulating layer 130.

Meanwhile, in the second embodiment of the present invention, when disconnection occurs in the gate link unit, the disconnection may be repaired by using a protection pattern.

FIG. 9 is a cross-sectional view illustrating a disconnection occurring in the gate link unit, and corresponds to a cross section taken along the line VII-VII in FIG. 7.

As shown in FIG. 9, when the gate link unit 124 is disconnected, the disconnection may be repaired by shorting the protective patterns 184 at both ends and the upper end of the disconnected gate link unit 124 using a laser. .

Here, although the protective pattern is formed of a transparent conductive material on the gate link portion, the protective pattern may be formed of the same material as the protective layer to prevent damage to the gate link portion.

10 illustrates a gate insulating film 130 formed on the gate link portion 124 on the substrate 110, and a semiconductor layer 144 and a protective layer (made of amorphous silicon) formed thereon. A protective pattern 174 made of the same material as 171 is formed.

Here, since the protective layer 171 and the active layer 141 of FIG. 7 are formed in the same process, the semiconductor layer 144 having the same shape as the protective pattern 174 is positioned under the protective pattern 174.

As described above, in the present invention, a protection pattern may be formed on the gate link part to prevent disconnection from being generated by the pixel electrode etchant.

The present invention is not limited to the above embodiments, and various changes and modifications can be made without departing from the spirit of the present invention.

In the present invention, in manufacturing the array substrate using four masks to reduce the manufacturing cost, when the protective layer and the active layer are formed in the same process and do not form a protective layer on the gate link portion, the protection that covers the gate link portion A pattern may be formed to prevent the gate link unit from being disconnected by the pixel electrode etchant.

On the other hand, when the protective pattern is formed of the same material as the pixel electrode, when the gate link unit is disconnected, the disconnection may be repaired by shorting the conductive pattern and the gate link unit using a laser.

Claims (6)

Board; A plurality of gate wires formed on the substrate and gate electrodes connected to the gate wires, a gate pad positioned at one end of the gate wires, and a gate link unit connecting the gate wires and the gate pads; A gate insulating layer covering the gate line, the gate electrode, the gate pad, and the gate link portion, and having an opening partially exposing the gate pad; A semiconductor layer formed on the gate insulating layer; An ohmic contact layer formed on the semiconductor layer; A data wiring formed on the ohmic contact layer and defining a pixel region crossing the gate wiring, a source electrode extending from the data wiring, a drain electrode positioned opposite the source electrode, and one end of the data wiring; A data pad located at; A protective layer formed on the data line and the source and drain electrodes and having a contact hole partially exposing the drain electrode; A pixel electrode formed in the pixel region and connected to the drain electrode through the contact hole; A protection pattern on the gate insulating layer and covering the gate link portion Including; And the semiconductor layer has the same shape as the data line and the source and drain electrodes except between the source and drain electrodes, and has the same shape as the protective layer. The method of claim 1, And the protection pattern is formed of the same material as the pixel electrode. The method of claim 1, And the protective pattern is formed of the same material as the protective layer. Providing a substrate; Forming a plurality of gate wires and gate electrodes connected to the gate wires, a gate pad positioned at one end of the gate wires, and a gate link portion connecting the gate wires and the gate pads on the substrate; Sequentially depositing a gate insulating film, an amorphous silicon layer, an impurity amorphous silicon layer, and a metal layer on the gate wiring; A data line defining the pixel region by patterning the metal layer and the impurity amorphous silicon to define a pixel region, a source electrode extending from the data line, a drain electrode located opposite the source electrode, and one end of the data line Forming a data pad and an ohmic contact layer at a location; Depositing an insulating material on the substrate on which the data line is formed and patterning the semiconductor layer together with the semiconductor layer to form a protective layer and an active layer; Forming a protective pattern on the gate insulating layer to cover the gate link portion; Forming a pixel electrode connected to the drain electrode through the contact hole in the pixel area Method of manufacturing an array substrate for a liquid crystal display device comprising a. The method of claim 4, wherein And said protective pattern is formed in the same process as said pixel electrode. The method of claim 4, wherein The protective pattern is a manufacturing method of an array substrate for a liquid crystal display device formed in the same process as the protective layer.