KR20020056205A - Method of manufacturing a capacitor in a semiconductor device - Google Patents

Abstract

PURPOSE: A method for fabricating a capacitor of a semiconductor device is provided to guarantee process stability in forming a dielectric thin film and an upper electrode, by minimizing a step between the upper and lower portions of a lower electrode. CONSTITUTION: An interlayer dielectric(12) is formed on a semiconductor substrate(11) having a predetermined structure. A predetermined region of the interlayer dielectric is etched to form a contact hole exposing a predetermined region of the semiconductor substrate. A contact plug is formed to fill the contact hole. A seed layer(16) is formed on the resultant structure including the contact plug. The first dummy pattern(17) is formed in a portion corresponding to the contact plug. The second dummy pattern(18) having the same height as the first dummy pattern is formed in a portion except the first dummy pattern. The first dummy pattern is removed to expose the seed layer and the lower electrode is formed on the exposed seed layer. The second dummy pattern is eliminated. A dielectric layer and an upper electrode are sequentially formed on the lower electrode.

Description

Method of manufacturing a capacitor in a semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor device. In particular, in a capacitor manufacturing method for forming a lower electrode of a capacitor using an electroplating method, a first dummy pattern is formed in advance on a portion where a lower electrode is to be formed and a first dummy is formed. After depositing and polishing the second dummy pattern to cover the pattern, the first dummy pattern is removed and the lower electrode is formed by using an electroplating method, thereby minimizing the upper and lower steps of the lower electrode to be formed in a subsequent process. The present invention relates to a method for manufacturing a capacitor of a semiconductor device to ensure process stability when forming a dielectric and an upper electrode.

In general, a capacitor having a lower electrode formed of a noble metal such as Pt is widely used to realize characteristics of high dielectric constant and low leakage current. In order to use a precious metal such as Pt as a lower electrode of a capacitor, a generalized electroplating method (hereinafter referred to as "ECD") is commonly used.

In order to selectively deposit Pt at a predetermined site using ECD, a dummy pattern is required to deposit Pt at a predetermined site. In general, an oxide film is used as a material for the dummy pattern, and a part of the dummy pattern is patterned to expose Pt formed in a previous process to act as a seed. Pt is deposited by ECD between the dummy patterns patterned so that Pt formed to act as a seed is exposed.

Here, the dummy pattern is formed by a dry etching process, and a predetermined etching slope is generated by the slope of the sensory pattern used as a mask during the dry etching process of the dummy pattern. The widths of the upper and lower portions are etched unevenly with each other. As a result, when the lower electrode is formed by using the ECD between the dry-etched dummy patterns, the width of the upper and lower portions of the lower electrode is changed, and there are many difficulties in depositing the dielectric and the upper electrode sequentially formed in subsequent processes. Derived.

This will be described in detail with reference to FIGS. 1 (a) to 1 (c) as follows. Only a description will be given of a method of manufacturing a capacitor having a stack structure.

Referring to FIG. 1A, an interlayer insulating layer 2 is first formed on a semiconductor substrate 1 on which a predetermined structure for manufacturing a semiconductor device is formed. The interlayer insulating layer 2 is patterned so that a predetermined portion of the semiconductor substrate 1 is exposed so that contact holes are formed in a predetermined portion thereof. The contact plug 50 is formed on the semiconductor substrate 1 on which the contact hole is formed to fill the contact hole. The contact plug 50 is composed of a polysilicon film 3, an ohmic contact layer 4, and a diffusion barrier film 5.

Referring to FIG. 1B, a seed layer 6 and a dummy oxide layer are sequentially deposited on the entire structure including the contact plug 50 to serve as a seed. Here, the seed layer 6 is made of a precious metal material such as Pt. The dummy oxide film deposited as described above is etched by a dry etching process so that the seed layer 6 of the predetermined portion is exposed to form the dummy pattern layer 7. In this case, the upper width W1 and the lower width W2 of the dummy pattern layer 7 formed by the dry etching process are different from each other. That is, the lower width W2 between the dummy pattern layers 7 is formed wider than the upper width W1. This is because a predetermined etching slope is generated by the slope of the sensory film pattern used as a mask during the dry etching process as described above.

Referring to FIG. 1C, Pt is deposited between the dummy pattern layers 7 formed by the dry etching process using ECD. Subsequently, the dummy pattern layer 7 is removed to expose Pt by a wet etching process to form the lower electrode 8. In this case, the lower electrode 8 has a lower width that is smaller than the upper width so as to correspond to the dummy pattern layer 7. Subsequently, an unillustrated dielectric and an upper electrode are sequentially formed on the semiconductor substrate 1 so as to cover the lower electrode 8. Here, the lower electrode 8, the dielectric, and the upper electrode operate as a capacitor.

As described above, in the capacitor manufacturing method of the semiconductor device according to the prior art, a dummy pattern layer for forming the lower electrode of the capacitor is formed in advance. However, the top and bottom steps of the dummy pattern layer are generated by the slope of the sensory film pattern used in the dry etching process for forming the dummy pattern layer. As a result, in the subsequent process, a significant step occurs in the upper and lower portions of the lower electrode formed between the dummy pattern layers, resulting in many difficulties in forming the dielectric and the upper electrode on the upper part thereof.

Accordingly, an object of the present invention is to provide a method of manufacturing a capacitor of a semiconductor device for reducing the upper and lower steps of the dummy pattern generated during the dummy pattern process for forming the lower electrode of the capacitor.

It is still another object of the present invention to form a first dummy pattern in a portion where a lower electrode is to be formed in advance, deposit and polish a second dummy pattern so as to cover the first dummy pattern, and then use a predetermined etching process to form a first dummy pattern. By removing the pattern and forming the lower electrode on the site by using the electroplating method, it minimizes the upper and lower steps of the lower electrode to ensure the process stability when forming the dielectric thin film and the upper electrode formed in the subsequent process It is to provide a method of manufacturing a capacitor of the device.

1 (a) to 1 (c) are cross-sectional views of a semiconductor device for explaining step by step a capacitor manufacturing method of a semiconductor device according to the prior art;

2 (a) to 2 (e) are cross-sectional views of a semiconductor device for explaining step by step a capacitor manufacturing method of a semiconductor device according to one embodiment of the present invention;

<Explanation of symbols for the main parts of the drawings>

1,11 semiconductor substrate 2,12 interlayer insulating layer

3,13 polysilicon film 4,14 ohmic contact layer

5,15: diffusion barrier 6,16: seed layer

7,17,18: dummy pattern layer 8,19: lower electrode

20: dielectric 21: upper electrode

Accordingly, the present invention includes forming a contact hole for exposing a predetermined region of the semiconductor substrate by forming at least one insulating layer on a semiconductor substrate having a predetermined structure and then etching a predetermined region of the insulating layer; Stacking the contact holes with a polysilicon layer, an ohmic contact layer, and a diffusion barrier to fill the contact holes; Forming a seed layer to cover the contact hole; Forming a first dummy pattern on a portion corresponding to the seed layer; Forming a second dummy pattern at the same height as the first dummy pattern in portions except the first dummy pattern; Removing the first dummy pattern to expose the seed layer and forming a lower electrode at a portion thereof; Removing the second dummy pattern; And sequentially forming a dielectric thin film and an upper electrode on the lower electrode.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2 (a) to 2 (e) are cross-sectional views of semiconductor devices sequentially shown to explain a method of manufacturing a capacitor of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 2A, first, an interlayer insulating layer 12 is formed on a semiconductor substrate 11. The interlayer insulating layer 12 is formed of a stacked structure of an oxide film and a nitride film having excellent etching selectivity with the oxide film. Here, the interlayer insulating layer 12 is deposited to a thickness of 300 to 1000 GPa. Subsequently, the interlayer insulating layer 12 is patterned so that a predetermined portion of the semiconductor substrate 11 is exposed to form contact holes in its predetermined portion. Here, the contact holes are formed to a depth of 2000 to 3000 Pa. The contact plug 100 is formed on the semiconductor substrate 11 on which the contact hole is formed to fill the contact hole. The contact plug 100 includes a polysilicon film 13, an ohmic contact layer 14, and a diffusion barrier 15. The polysilicon film 13 is formed from the top of the contact hole to a depth of 500-1500 kV using CVD.

Here, the process of forming the polysilicon film 13 formed in the contact hole will be briefly described. After the polysilicon is deposited on the semiconductor substrate 11 on which the interlayer insulating layer 12 is formed, the semiconductor substrate 21 is formed on the semiconductor substrate 21. The polysilicon film 13 is applied to a predetermined portion of the contact hole by performing a front overetch process so that a part of the polysilicon deposited on the interlayer insulating layer 12 and the polysilicon embedded in the contact hole are removed. Is formed.

Subsequently, a Ti film or a Co film is formed on the entire structure including the contact hole at a thickness of 100 to 300 m 3. Titanium silicide film as an ohmic contact layer 14 formed by reacting the polysilicon film 13 on the polysilicon film 13 inside the contact hole by performing a heat treatment process on the semiconductor substrate 11 on which the Ti film or the Co film is formed. Or a cobalt silicide film is formed. Here, the Ti film or Co film remaining on the interlayer insulating layer 12 without reacting with the polysilicon film 13 is removed by a predetermined etching process. In addition, any one of the TiN film, the TiSiN film, the TiAlN film, the TaSiN film and the TaAlN film is formed as the diffusion barrier film 15 on the entire structure including the contact hole by the PVD method or the CVD method.

Referring to FIG. 2 (b), the seed layer 16 composed of a noble metal such as Pt in a thickness of 50 to 1000 μs is used to form a lower electrode in a subsequent process on the entire structure including the contact plug 100. Is formed. Subsequently, polysilicon is deposited on the entire structure including the seed layer 16 to a thickness of 2000 to 15000 mm, and the first dummy pattern 17 is formed in the remaining portions except for the portions corresponding to the contact holes in the polysilicon. Here, the upper portion of the first dummy pattern 17 is formed to be thinner than the lower portion due to the etching slope margin during the dry etching process. In addition, a dopant of polysilicon, which is a constituent of the first dummy pattern 17, is set to any one of P and B.

Referring to FIG. 2C, a dummy oxide film is deposited on the entire structure including the first dummy pattern 17 to a thickness of 500 to 20,000 GPa so as to cover the first dummy pattern 17. At this time, the dummy oxide film deposited on the first dummy pattern 17 of the dummy oxide film is removed by a predetermined etching process to form the second dummy pattern 18. In addition, the upper surface of the second dummy pattern 18 is polished by a CMP process to expose the first dummy pattern 17.

Referring to FIG. 2 (d), the first dummy pattern 17 between the second dummy pattern 18 is removed by a wet etching process so that a part of the seed layer 16 is exposed. In order to remove the dummy pattern 17, any one of an HF / H202 mixed solution, an HF / HNO3 mixed solution, and a NH4OH / H2O mixed solution is used as an etching solution. At this time, the selection ratio between the first dummy pattern 17 and the second dummy pattern 18 is set to 100: 1 or more, so that the second dummy pattern 18 is hardly affected when the first dummy pattern 17 is etched. Will not. Then, between the second dummy pattern 18 from which the first dummy pattern 17 has been removed, any one of Pt, Ir, Os, W, Mo, Co, Ni, Au, and Ag by ECD has a thickness of 3000 to 20,000 mm 3. The material of is deposited. In addition, these materials are deposited at current densities in the range of 0.01 to 100 mA / cm 2.

Referring to FIG. 2E, the second dummy pattern 18 is removed by a wet etching process to deposit the noble metal material. In this case, as the etching solution used in the wet etching process, HF / H 2 O mixed solution or HF / NH 4 F mixed solution is used. In addition, the noble metal material formed on the portion corresponding to the interlayer insulating layer 12 is removed by a dry etching process to insulate the lower electrodes. When this process is completed, the lower electrode 19 made of a noble metal material of a predetermined form is formed. Subsequently, on the semiconductor substrate 11 on which the lower electrode 19 is formed, BST is deposited to a thickness of 150 to 500 kPa in a temperature range of 300 to 600 ° C. by CVD and nitrogen in a temperature range of 500 to 700 ° C. through RTP. In the atmosphere, the dielectric 20 is formed by crystallizing BST in the range of 30 to 180 seconds. Subsequently, an upper electrode 21 is formed on the dielectric 20.

As described above, in the method of manufacturing a capacitor of a semiconductor device according to an embodiment of the present invention, a first dummy pattern is formed in advance on a portion where a lower electrode is to be formed, and a second dummy pattern is deposited and polished to cover the first dummy pattern. After that, the first dummy pattern is removed using a predetermined etching process, and a lower electrode is formed on the site by using an electroplating method, thereby minimizing upper and lower steps of the lower electrode, thereby forming a dielectric thin film and an upper electrode. In the formation of the process stability can be ensured.

As described above, the present invention provides a capacitor manufacturing method for forming a lower electrode of a capacitor using an electroplating method, wherein the second dummy pattern is formed in advance on a portion where the lower electrode is to be formed and the second dummy pattern is covered. After depositing and polishing the dummy pattern, the first dummy pattern is removed by using a predetermined etching process and a lower electrode is formed on the site by using an electroplating method, thereby minimizing upper and lower steps of the lower electrode in a subsequent process. When forming the dielectric thin film and the upper electrode to be formed to ensure process stability it can be produced an excellent capacitor.

Claims (16)

Forming an interlayer insulating film over the semiconductor substrate having a predetermined structure, and then forming a contact hole exposing a predetermined region of the semiconductor substrate by etching a predetermined region of the interlayer insulating film; Forming a contact plug to fill the contact hole; Forming a seed layer over the entire structure including the contact plug; Forming a first dummy pattern in a portion corresponding to the contact plug, and then forming a second dummy pattern at the same height as the first dummy pattern in portions except the first dummy pattern; Removing the first dummy pattern to expose the seed layer, and then forming a lower electrode at a portion thereof; After removing the second dummy pattern, sequentially forming a dielectric and an upper electrode on the lower electrode. The method of claim 1, The interlayer insulating film is a capacitor manufacturing method of a semiconductor device, characterized in that formed in a thickness of 300 to 1000Å. The method of claim 1, The contact hole is a capacitor manufacturing method of the semiconductor device, characterized in that formed in the upper portion of the depth of 2000 to 3000Å. The method of claim 1, The contact plug may have a polysilicon layer, an ohmic contact layer, and a diffusion barrier layer in a stacked structure. The method of claim 4, wherein The polysilicon film is a capacitor manufacturing method of a semiconductor device, characterized in that formed in the depth of 500 to 1500Å from the top of the contact hole. The method of claim 4, wherein The ohmic contact layer is a capacitor of a semiconductor device, characterized in that any one of the Ti and Co film is formed to a thickness of 100 to 300Å, and is formed of any one of a titanium silicide film and a cobalt silicide film by reacting with the polysilicon film during the heat treatment process. Manufacturing method. The method of claim 4, wherein The diffusion barrier is a capacitor manufacturing method of a semiconductor device, characterized in that formed of any one of TiN, TiSiN, TiAlN, TaSiN and TaAlN. The method of claim 1, The seed layer is a capacitor manufacturing method of the semiconductor device, characterized in that the Pt is formed to a thickness of 50 to 1000Å. The method of claim 1, The first dummy pattern is a method of manufacturing a capacitor of a semiconductor device, characterized in that the polysilicon is formed to a thickness of 2000 to 15000Å. The method of claim 9, The polysilicon is a capacitor manufacturing method of a semiconductor device, characterized in that the dopant is set to any one of phosphorus and boron. The method of claim 1, The second dummy pattern is a silicon oxide capacitor manufacturing method of a semiconductor device, characterized in that formed to a thickness of 500 to 20000Å. The method of claim 1, Removing the first dummy pattern is a capacitor manufacturing method of a semiconductor device, characterized in that by removing any one of the mixed solution of HF / HNO 3 mixed solution, HF / H202 mixed solution and NH40H / H2O mixed solution. The method of claim 1, The lower electrode is characterized in that any one of Pt, Ru, Ir, Os, W, Mo, Co, Ni, Au and Ag is deposited to a thickness of 3000 to 20000 Å by a current density of 0.01 to 100 ㎃ / ㎠ A method for producing a capacitor of a semiconductor device. The method of claim 1, Removing the second dummy pattern is a capacitor manufacturing method of a semiconductor device, characterized in that by removing any one of the mixed solution of HF / H 2 O mixed solution and HF / NH4F mixed solution. The method of claim 1, The dielectric thin film is a capacitor manufacturing method of a semiconductor device, characterized in that the BST is formed in a thickness of 150 to 500Å over a temperature range of 300 to 600 ℃. The method of claim 15, The BST is a capacitor manufacturing method of a semiconductor device, characterized in that the crystallization in the range of 30 to 180 seconds in a nitrogen atmosphere of the temperature range of 500 to 700 ℃.