JP2000269424A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable to process in fine structure while using a conductive metallic oxide as the storage node by forming a capacitor electrode at a position opposite to the conductive metallic oxide with a capacitor insulation film, which is formed on the surface of the conductive metallic oxide being sandwiched between the conductive metallic oxide and capacitor electrode. SOLUTION: A storage node contact 24 is a lamination of a tungsten film 41 and a titanium nitride 40. On the top of a layer insulation film 27, a storage node 25 which is electrically connected to the storage node contact 24, is formed. The storage node 25 is formed in and on a metallic film 67 made of ruthenium, etc., in a self-alignment process, and is made of a metallic oxide 28 such as strontium oxide having metallic elements common to the metallic film 67. A highly dielectric film 29 such as BSTO covers the storage node 25, and functions as a capacitor insulation film. Further, a metallic oxide 30 such as a strontium oxide covers the highly dielectric film 29, and functions as a plate electrode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a structure of a capacitor of a semiconductor device and a method of manufacturing the same.

[0002]

2. Description of the Related Art As the miniaturization of semiconductor devices has progressed, it has become necessary for capacitors to obtain a large capacitance with a smaller area. For example, DRAM (Dynamic Random Acc
In the case of ess memory, a NO film has conventionally been used as a capacitor insulating film. Instead of this, a tantalum oxide film (Ta ₂ O ₅ ) having a higher dielectric constant has been developed. A BSTO film having a higher dielectric constant ((Ba, S
r) Application of a high dielectric film such as TiO ₃ ) is being studied. However, in order to maximize the performance of these high dielectric films, an SRO film (S
It has been reported that it is desirable to use a conductive metal oxide such as rRuO ₃ ). Here, a first conventional technique (FIGS. 1 to 6) and a second technique using a metal oxide electrode are used.
Of the related art (FIGS. 7 to 10) will be described. First
In the prior art, first, as shown in FIG. 1, a storage node contact, for example, a titanium nitride film 3 is formed on an interlayer insulating film, for example, a silicon oxide film 2 on a semiconductor substrate 1. Next, as shown in FIG. 2, a metal oxide, for example, an SRO film 4 is formed on the entire surface by using a sputtering method. Next, as shown in FIG. 3, the SRO film 4 is processed into a desired shape of the storage node using lithography and RIE. Next, as shown in FIG. 4, a high dielectric film, for example, a BSTO film 5 is formed on the entire surface by using the CVD method. This becomes a capacitor insulating film. Next, as shown in FIG.
A metal oxide, for example, S
An RO film 6 is formed. This becomes a plate electrode. Next, as shown in FIG. 6, the BSTO film 5 and the SRO film 6 are processed using lithography and RIE. Thereby, a capacitor is formed.

In the second prior art, first, as shown in FIG. 7, a storage node contact, for example, a tungsten film 7 is formed on an interlayer insulating film, for example, a silicon oxide film 2 on a semiconductor substrate 1. Next, as shown in FIG.
An interlayer insulating film, for example, a silicon oxide film 8
To form Then, a contact hole 9 is formed in the silicon oxide film 8 by using lithography and RIE. Next, as shown in FIG. 9, a metal oxide, for example, an SRO film 10 is formed only in the contact hole 9 by using the CVD method and the CMP method. This is the storage node. Next, as shown in FIG. 10, a high-dielectric film to be a capacitor insulating film, for example, a BSTO film 1 is formed by a CVD method.
Then, a metal oxide serving as a plate electrode, for example, an SRO film 12 is formed. Thus, a capacitor structure is formed.

[0004]

In the first prior art as described above, it is necessary to process the SRO film, which is a metal oxide, twice (see FIGS. 3 and 6). Of these, the processing described in FIG. 6 is processing of a plate electrode, and therefore does not need to be a fine pattern. Therefore, a desired shape can be obtained by using a wet etching method. On the other hand, the processing shown in FIG. 3 is a step of forming a storage node, and therefore generally needs to be processed into a fine shape for one bit of a memory cell. For this reason, it is desirable to use an anisotropic etching method, especially RIE. However, the RIE technology of the SRO film, which is a metal oxide, is very difficult, and high-precision processing of the storage node cannot be realized by the current technology. Further, in the second conventional technique, when forming a storage node, the RIE of the silicon oxide film 2 is performed.
With the technology and the CMP technology of the SRO film 10, fine processing can be performed. As a result, the above-described problem of the first related art is solved. However, there are the following problems in order to further miniaturize and speed up the semiconductor device. First, in order to increase the speed of the semiconductor device, it is necessary to reduce the resistivity of the storage node contact and the storage node as much as possible. In the second conventional technique described above, a tungsten film 7 having a lower resistivity than a titanium nitride film is used as a storage node contact. Thus, the speed of the semiconductor device can be increased, but the tungsten film 7 and the SRO film 10 are brought into direct contact. When the tungsten film 7 and the SRO film 10 are brought into direct contact with each other, an interfacial reaction occurs in a subsequent heat process, and the tungsten film 7 may be oxidized or a strontium-tungsten compound (Sr-W compound) may be formed. Can be This increases the resistivity of the storage node contact. Therefore, when a metal having low resistivity is used for the storage node contact, a thin barrier metal layer, for example, a titanium nitride film needs to be formed at the interface between the storage node contact and the storage node. This leads to an increase in the number of manufacturing steps.

A metal oxide such as the SRO film 10 generally has a higher resistivity than a pure metal. Therefore, when the semiconductor device is operated at a high speed, there is a possibility that an effective capacitor capacity cannot be obtained in the upper part 13 of the SRO film 10 which is a storage node in the structure shown in FIG. For this reason, the expected capacity cannot be obtained in high-speed operation, which causes a reduction in the reliability of the semiconductor device.
The present invention has been made in view of the above drawbacks, and has as its object to enable miniaturization while using a conductive metal oxide for a storage node. It is another object of the present invention to increase the speed of a semiconductor device.

[0006]

SUMMARY OF THE INVENTION A semiconductor device according to the present invention is provided.
The stacked structure includes a plurality of conductive films containing a common metal element.
A first capacitor electrode, and the first capacitor
A capacitor insulating film formed on the surface of the
A pair with the first capacitor electrode with a capacitor insulating film interposed therebetween.
And a second capacitor electrode formed facing the second capacitor electrode.
And features. Here, the first capacitor electrode
Should have a laminated structure containing a conductive oxide.
No. Further, the first capacitor electrode includes a metal film and a conductive film.
It is desirable to be a laminated film made of an electrically conductive oxide. Ma
Further, the capacitor insulating film may be a high dielectric film.
desirable. The metal film is a Ru (ruthenium) film.
And the conductive oxide is SRO (SrRuO₃) With membrane
Desirably. Further, the metal film is made of Ru (ruthene).
) Film, and the conductive oxide is SRO (SrRu).
O ₃) Film, wherein the capacitor insulating film is a BSTO film
Desirably. Further, the conductive oxide is perov.
It is desirable to have a skyte-like structure. Book
The first method for manufacturing a semiconductor device according to the present invention includes a method including a metal.
Forming a film, and coating the surface of the film containing the metal
Forming a metal-containing film by heat treatment;
Reacting the coating film to form a conductive oxide;
Removing the unreacted one of the insulating films;
Forming a capacitor insulating film on the surface of conductive oxide
And the conductive oxide with the capacitor insulating film interposed therebetween.
Forming a capacitor electrode at a position facing the
It is characterized by having.

According to a second method of manufacturing a semiconductor device according to the present invention, there is provided a step of forming a film containing a metal, forming a film on the surface of the film containing the metal, and simultaneously forming the film containing the metal and the film. And forming a conductive oxide, forming a capacitor insulating film on the surface of the conductive oxide, and forming a capacitor at a position facing the conductive oxide with the capacitor insulating film interposed therebetween. Forming an electrode. Here, it is preferable that the film containing the metal and the conductive oxide have a common metal element. It is preferable that both the conductive oxide and the capacitor insulating film have a perovskite structure. Preferably, the capacitor insulating film is a high dielectric film. The metal is Ru (ruthenium), and the conductive oxide is S
It is desirable to use an RO (SrRuO ₃ ) film. By adopting the above configuration, the present invention enables miniaturization while using a conductive metal oxide for a storage node, and enables high-speed semiconductor devices.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) The first embodiment of the present invention
An embodiment will be described with reference to the drawings (FIGS. 11 to 22). In the first embodiment, the present invention relates to COB (Cap
acitor over bitline) type DRAM. The present invention can be applied not only to the COB type DRAM but also to DRAMs and FRAMs of other structures without departing from the spirit of the invention. FIG.
Shows the COB according to the first embodiment of the present invention.
2 is an upper surface layout of a memory cell region of a type DRAM.
The gate electrode of the MOS transistor MQ constituting the DRAM cell is continuously arranged in one direction to form a word line 21. This MOS transistor MQ is for information transfer. Further, storage nodes 25 of capacitors MC constituting the DRAM cell are arranged. This storage node 25 is electrically connected to one of the source / drain regions of MOS transistor MQ via storage node contact 24. A bit line 23 arranged crossing the word line 21 is electrically connected to the other of the source / drain regions of the MOS transistor MQ via a bit line contact 22.

FIG. 12 is a circuit diagram of the COB type DRAM of FIG.
FIG. 3 also shows a cross section at the position of −A ′ and a cross section of one transistor portion in the peripheral circuit region. In the cell array region, a MOS transistor MQ for information transfer is formed. A storage node contact 24 electrically connected to one of the source and drain diffusion layers 26 of the MOS transistor MQ is formed in an interlayer insulating film 27 made of, for example, a silicon oxide film. The storage node contact 24 is formed of, for example, a laminated film of a tungsten film 41 and a titanium nitride film 40. Here, the titanium nitride film 40 functions as a barrier metal layer. Further, on the upper surface of the interlayer insulating film 27, a storage node 25 electrically connected to the storage node contact 24 is formed. The storage node 25 includes a metal film 67 such as Ru (ruthenium) and a metal oxide such as SRO (SrRuO ₃ ) formed in a self-aligned manner on the surface of the metal film 67 and having a common metal element with the metal film 67. Consists of 28.
Then, the BST is set so as to cover the storage node 25.
A high dielectric film 29 such as O is formed. This high dielectric film 29 becomes a capacitor insulating film. Further, a metal oxide 30 such as SRO is formed so as to cover the high dielectric film 29. This metal oxide 30 becomes a plate electrode. Thus, the information storage capacitor is composed of the storage node 25, the high dielectric film 29 and the metal oxide 30.

Here, both the storage node 25 and the high dielectric film 29 use an oxide. By doing so, it is possible to maximize the performance of the high dielectric film. For example, if the storage node is an SRO film and the capacitor insulating film is a BSTO film, both have a conductive perovskite crystal structure, and the performance of the BSTO film can be maximized. In the source / drain region 26 of the MOS transistor MQ, the storage node contact 2
4 is electrically connected to the bit line contact 22. In the peripheral circuit region, a MOS transistor 31 is formed. Further, a wiring 33 made of a laminated film of tungsten and titanium nitride is formed on the interlayer insulating film 27. This wiring 33 is, for example, a MOS
The source / drain region 32 of the transistor 31 is electrically connected. A covering insulating film 34 such as a silicon nitride film is formed on the upper surface of the wiring 33. Then, an upper wiring 37 is formed via a contact 36 formed in the second interlayer insulating film 35. Similarly, as shown, an upper layer wiring is formed as necessary.

FIG. 13 is a circuit diagram of the COB type DRAM of FIG.
It shows a cross section (only the memory cell region) at the position -B ′. On the interlayer insulating film 27, a bit line 23 made of a laminated film of tungsten and titanium nitride is formed. The bit line 23 is connected to the source / drain diffusion layer 2 of the information transfer MOS transistor through the bit line contact 22.
6 is electrically connected to the storage node contact 24 not connected. This bit line 23
A coating insulating film 34 such as a silicon nitride film is formed on the upper surface of the substrate. The bit line 23 and the bit line contact 2
2 may be formed simultaneously. Next, a method for manufacturing the COB DRAM according to the first embodiment will be described with reference to the drawings (FIGS. 14 to 21). Hereinafter, unless otherwise specified, AA ′ in FIG.
This will be described with reference to a cross-sectional view of FIG. First, as shown in FIG.
An element isolation region 39 is formed in a semiconductor substrate 38. Although the element isolation region 39 uses the STI structure in the present embodiment, the LOCOS structure may be used. Then, a MOS transistor MQ (memory cell region) and a MOS transistor 31 (peripheral circuit region) are formed on the semiconductor substrate 38. The gate electrodes of the MOS transistor MQ and the MOS transistor 31 include a gate insulating film 42, a conductive layer 43 having a polycide structure, and an insulating film 44 formed so as to cover the conductive layer 43. Then, an interlayer insulating film 27 such as a silicon oxide film is formed on the entire surface.

Next, the interlayer insulating film 27 in the memory cell region
Inside, a storage node contact 24 made of a laminated film of, for example, a tungsten film 41 and a titanium nitride film 40 is formed. Here, the titanium nitride film 40 functions as a barrier metal layer. At the same time, a wiring 33 composed of a laminated film of a titanium nitride film 40 and a tungsten film 41 is formed in the interlayer insulating film 27 in the peripheral circuit region. This wiring 33
The MOS transistor 31 is electrically connected to one of the source / drain regions. Here, the wiring 33 also serves as the substrate contact 68. And this wiring 3
A coating insulating film 34 such as a silicon nitride film is formed on the upper surface of the substrate 3. Here, FIG. 15 is a cross-sectional view taken along line BB ′ of FIG. As shown in FIG. 15, at the same time when the substrate contact 68 and the wiring 33 are formed in the peripheral circuit region,
In the memory cell region, a bit line contact 22 and a bit line 23 are formed. Further, at the same time as the covering insulating film 34 is formed in the peripheral circuit region, the covering insulating film 34 is also formed in the memory cell region. Bit line 23 is electrically connected via bit line contact 22 to one of source / drain regions 26 of MOS transistor MQ to which storage node contact 24 is not connected. The bit line 23 and the bit line contact 22 may be formed at the same time.

Next, as shown in FIG. 16, after a metal film, for example, a Ru film 45 is formed on the entire surface, the Ru film 45 is left only in a portion where a capacitor is to be formed by using a lithography method and an etching technique. At this time, the Ru film 45 is formed so as to be electrically connected to the upper surface of the storage node contact 24. Next, as shown in FIG.
A film containing strontium, for example, a strontium oxide film 46 is formed on the entire surface by using a method. At this time, for example, Sr (DPM) ₂ (strontium bis
(Dipivaloylmethanate): Sr [(CH ₃ ) ₃ C-COCHCO- (C (CH ₃ )
₃ )] ₂ ) is dissolved in THF (tetra hydrofuran) solution,
When CVD is performed in an oxidizing atmosphere at about 300 to 500 ° C. using a gas that has been gasified by a vaporizer, a strontium oxide film is deposited. Alternatively, Sr (D
PM) ₂ may be vaporized by a sublimation method.
Here, the strontium-containing film may be a strontium carbonate film. Further, a strontium film may be used. However, the strontium oxide film and the strontium carbonate film are easier to deposit by the CVD method than the strontium film. In addition, as a method of depositing a coating, CV
Although the method D is described as an example, a sputtering method or a sol-gel method may be used.

Next, as shown in FIG. 18, by annealing in an oxidizing atmosphere such as oxygen or ozone,
A reaction is caused between the strontium oxide film 46 and the Ru film 45, and an SRO film 47 as a metal oxide is formed on the surface of the Ru film 45 in a self-aligned manner. The SRO film 47 thus formed has the same metal element as the Ru film 45. Next, as shown in FIG.
Or by wet etching in dilute acid,
The unreacted strontium oxide film 46 is removed. The remaining Ru film 45 and SRO film 47 become storage nodes 25 of the capacitor. Next, as shown in FIG. 20, the BSTO film 4 which is a high dielectric film is formed by using the CVD method.
8 is formed on the entire surface. Further, an SRO film 49 made of a metal oxide is formed on the entire surface by using the CVD method. This BST
The O film 48 becomes a capacitor insulating film, and the SRO film 49 becomes a plate electrode. Next, as shown in FIG. 21, the SRO film 49 as a plate electrode is processed into a desired shape by using a lithography method and an etching technique. Thereby, a capacitor is formed. In this capacitor, the storage node 25 is composed of a Ru film 45 as a metal film and an SRO film 47 as a metal oxide, the capacitor insulating film is a BSTO film 48 as a high dielectric film, and the plate electrode is a metal oxide. Is the SRO film 49. Here, a BSTO film 48 serving as a capacitor insulating film, an SRO film 49 serving as a plate electrode, and an SRO film
The film 47 has a perovskite crystal structure. Thereby, the BSTO film 48, which is a high dielectric film, can exhibit its performance to the maximum.

Thereafter, the COB type DRAM shown in FIG. 12 is formed by forming a multilayer wiring structure by using a known technique. By the way, as the miniaturization of the semiconductor device progresses, the storage node contact 24 and the Ru film 4 forming the storage node in the process shown in FIG.
The possibility of misalignment with 5 increases. According to the conventional technique (see FIGS. 1 to 6), when the SRO film 4 serving as a storage node is processed with a shift, the BST serving as a capacitor insulating film is formed with the titanium nitride film 3 exposed.
The O film 5 is formed. Then, the BSTO film 5
And the titanium nitride film 3 are in direct contact with each other, which causes deterioration of the capacitor leakage characteristics. On the other hand, according to the first embodiment of the present invention, after processing the Ru film 45, the strontium oxide film 46 is formed on the entire surface (see FIG. 17). Therefore, even when the Ru film 45 is processed to be shifted and the storage node contact 24 is exposed, the upper surface of the storage node contact 24 comes into contact with the strontium oxide film 46.
Then, the strontium oxide film 46 and the storage node contact 2 are formed by the annealing process already shown in FIG.
A reaction occurs with the metal film constituting 4 to form an insulating film.

That is, as shown in FIG. 22, if the storage node contact 24 is constituted by the tungsten film 41, the tungsten film 41 and the strontium oxide film 46 react to form an insulating film such as a SrWO ₄ film. Will be done. Thereby, it is possible to prevent the storage node contact 24 from directly contacting the BSTO film 48 as the capacitor insulating film, and to prevent deterioration of the capacitor leakage characteristics. As described above, according to the first embodiment of the present invention, the following effects can be obtained. First, storage node 2
The processing of No. 5 is substantially performed in the process of the Ru film 45 as the metal film, and the SRO film 47 as the metal oxide is formed in a self-aligned manner by the reaction between the Ru film 45 and the strontium oxide film 46 ( See FIG. 16). Therefore, the processing of the storage node 25 becomes easy, for example, by etching the Ru film 45 in a mixed gas of oxygen and chlorine.
As described above, even if a metal oxide such as an SRO film is used as a storage node, the processing can be prevented from becoming difficult, and fine processing can be performed. As a result, a highly reliable and high-density semiconductor device can be formed.

A Ru film as a metal film is formed between the tungsten film 41 forming the storage node contact 24 and the SRO film 47 forming the storage node 25. Therefore, the tungsten film 41 and the SRO
Since there is no direct contact with the film 47, there is no need to form a thin barrier metal layer at the interface. This allows
It is possible to prevent an increase in the number of manufacturing steps. Also,
The storage node 25 is mainly composed of a Ru film 45 which is a metal film, and an SRO film 47 which is a metal oxide is formed at a portion in contact with the BSTO film 48 which is a high dielectric film.
Are formed. An SRO film 49 made of a metal oxide is used as the plate electrode. Thus, by sandwiching the high dielectric film between the metal oxides, the performance of the high dielectric film can be maximized. Further, since the storage node 25 is mainly made of a metal film, the resistivity can be made lower than in the case where the storage node 25 is made of only a metal oxide. Thus, the speed of the semiconductor device can be increased. Further, as described above, even when misalignment occurs in the processing of the Ru film 45 constituting the storage node 25, it is possible to prevent the deterioration of the leak characteristic of the capacitor current, and to provide a highly reliable semiconductor device. It is possible to do.

The CVD step (see FIG. 17) of forming the strontium oxide film 46 using the CVD method is performed in 30 steps.
This is performed in an oxidizing atmosphere at a relatively low temperature of about 0 to 500 ° C. For this reason, it is possible to reduce a high-temperature heat process which is a problem in optimizing a transistor and adopting a silicide structure. (Modification 1 of First Embodiment) Modification 1 of the first embodiment of the present invention will be described with reference to FIG. In the first modification, a metal film, for example, a Ru film 52 is formed on the storage node contact 24. By doing so, as shown in FIG. 23, when the Ru film 45 constituting the storage node is misaligned during processing and the Ru film 52 is exposed, the Ru film 52 comes into contact with the strontium oxide film 46. (See FIG. 18). Then, by the annealing step already shown in FIG. 18, a reaction occurs between the Ru film 52 and the strontium oxide film 46, and the SRO film 53 which is a metal oxide is formed. For this reason, it is possible to prevent the tungsten film 41 and the BSTO film 48 constituting the storage node 24 from coming into direct contact. Further, the SRO film 53 can be used as a part of the storage node.

(Modification 2 of First Embodiment) A modification 2 of the first embodiment of the present invention will be described with reference to FIG. In the second modification, a Ru film 54 that is a metal film is used as the storage node contact 24.
With this arrangement, when the Ru film 45 constituting the storage node is misaligned during the processing and the Ru film 54 is exposed as shown in FIG. 24, the Ru film 54 comes into contact with the strontium oxide film 46. (See FIG. 18).
Then, by the annealing process already shown in FIG.
A reaction occurs between the film 54 and the strontium oxide film 46, and an SRO film 53, which is a metal oxide, is formed. For this reason, even if misalignment occurs, the SRO film 53 can be used as a part of the storage node, and the problem unlike the related art does not occur. (Second Embodiment) A second embodiment of the present invention will be described with reference to the drawings (FIGS. 25 to 30). Here, only the capacitor portion of the semiconductor device will be described with reference to the drawings. That is, in the case of a COB type DRAM, the present embodiment is applied to the portion of the capacitor MC in FIG. First, as shown in FIG. 25, the storage node contact 24 is formed in the interlayer insulating film 27.

Next, as shown in FIG.
Is used to form a metal film, for example, a Ru film 55 on the entire surface.
Next, as shown in FIG.
Using Ru film 55 as storage node using E method
Process into the shape of Next, as shown in FIG.
Strontium oxide film 5 as a film by CVD
6 is formed. At this time, the source gas is, for example, Sr
(DPM) ₂(Strontium bis (dipivaloylmethanat
e): Sr [(CH_Three)_ThreeC-COCHCO- (C (CH_Three)_Three)]_Two) In THF (tetr
a hydrofuran) solution and gasified by a vaporizer
In an oxidizing atmosphere of about 500 to 700 ° C.
Perform VD. Then, the strontium oxide film becomes the same as the deposition.
Sometimes, a Ru film 55 which is a metal film and a strontium oxide film
A reaction occurs at the interface with the metal oxide 56, and the metal oxide SRO
The film 57 is formed in a self-aligned manner. Formed in this way
The SRO film 57 has the same metal element as the Ru film 55.
Have Here, S is used as a source gas for CVD.
r (DPM)₂Can be used by sublimation
Good. Also, using a strontium carbonate film as the coating
No problem. Further, a strontium film may be used. However
Strontium oxide and charcoal rather than strontium
Strontium oxide film is easier to deposit by CVD method
It is. In addition, a CVD method is taken as an example of a film deposition method.
However, a sputtering method or a sol-gel method may be used.

Next, as shown in FIG. 29, the unreacted strontium oxide film 56 is removed by washing with water or wet etching in dilute acid. The remaining Ru film 55 and SRO film 57 serve as storage nodes of the capacitor. Next, as shown in FIG.
A BSTO film 58, which is a high dielectric film, is formed on the entire surface by using a method. Further, an SRO film 59 made of a metal oxide is formed on the entire surface by using the CVD method. This BSTO film 58 becomes a capacitor insulating film, and the SRO film 59 becomes a plate electrode. Next, although not shown, the SRO film 59 as a plate electrode is processed into a desired shape by using a lithography method and an etching technique. Thereby, a capacitor is formed. This capacitor is connected to storage node 2
5 is a Ru film 55 which is a metal film and SRO which is a metal oxide
The capacitor insulating film is a BSTO film 58 which is a high dielectric film, and the plate electrode is an SRO film 59 which is a metal oxide. Here, the BSTO film 58 as a capacitor insulating film and the SRO film 5 as a plate electrode
9 and the SRO film 57 constituting the storage node
Both have a perovskite-like crystal structure.
Thereby, the BSTO film 58, which is a high dielectric film, can exhibit its performance to the maximum.

As described above, according to the second embodiment of the present invention, the following effects can be obtained. First, the processing of the storage node is performed by using a Ru film 55 as a metal film.
And the reaction between the Ru film 55 and the strontium oxide film 56 is performed.
The film 57 is formed in a self-aligned manner (see FIG. 28). Therefore, the processing of the storage node 25 becomes easy, for example, by etching the Ru film 55 in a mixed gas of oxygen and chlorine. As described above, even if a metal oxide such as an SRO film is used as a storage node, the processing can be prevented from becoming difficult, and fine processing can be performed. As a result, a highly reliable and high-density semiconductor device can be formed. Further, a CVD step of forming a strontium oxide film 56 using a CVD method (see FIG. 28)
Is performed in a relatively high temperature oxidizing atmosphere of about 500 to 700 ° C. Therefore, the SRO film 57 can be formed simultaneously with the deposition of the strontium oxide film 56,
The number of steps can be reduced as compared with the first embodiment.
Further, a metal film Ru is provided between the storage node contact 24 and the SRO film 57 constituting the storage node.
A film 55 is formed. Therefore, even if a tungsten film, which is a low-resistance metal film, is used as the storage node contact, the storage node contact 24 and the SR
There is no direct contact with the O film 57. Therefore, there is no need to form a thin barrier metal layer at the interface. This makes it possible to prevent an increase in the number of manufacturing steps.

The storage node is mainly composed of a Ru film 55 which is a metal film, and a high dielectric film B
An SRO film 57 made of a metal oxide is formed in a portion in contact with the STO film 58. As the plate electrode, an SRO film 59, which is a metal oxide, is employed.
Thus, by sandwiching the high dielectric film between the metal oxides, the performance of the high dielectric film can be maximized. Further, since the storage node 25 is mainly made of a metal film, the resistivity can be made lower than in the case where the storage node 25 is made of only a metal oxide. Thus, the speed of the semiconductor device can be increased. Further, as described in the first embodiment, in processing the Ru film 55 forming the storage node,
Even if misalignment occurs, deterioration of the capacitor leak characteristics can be prevented, and a highly reliable semiconductor device can be provided. (Modification of Second Embodiment) A modification of the second embodiment of the present invention will be described with reference to FIG. In this modification, in the step of forming the strontium oxide film 56 shown in FIG. 28, the deposited film thickness of the strontium oxide film 56 is reduced and optimized. Thus, a reaction occurring between the Ru film 55 and the strontium oxide film 56 during the deposition of the strontium oxide film 56 proceeds to the surface of the strontium oxide film 56. This makes it possible to omit the step of removing the unreacted strontium oxide film 56 as shown in FIG.

In this case, a configuration as shown in FIG. 31 is obtained. That is, Ru on the upper surface of the interlayer insulating film 27 is used.
The strontium oxide film 56 remains in a portion where the film 55 or the SRO film 57 is not formed. By doing so, the number of steps can be further reduced as compared with the second embodiment. Third Embodiment A third embodiment of the present invention will be described with reference to the drawings (FIGS. 32 to 39). Here, only the capacitor portion of the semiconductor device will be described with reference to the drawings. That is, in the case of a COB type DRAM, the present embodiment is applied to the portion of the capacitor MC in FIG. First, as shown in FIG. 32, the storage node contact 24 is formed in the interlayer insulating film 27. Next, as shown in FIG. 33, an interlayer insulating film 60 made of, for example, a silicon oxide film is formed by a CVD method. Further, the contact hole 6 is formed using lithography and RIE.
Form one. This contact hole 61 is formed such that the upper surface of storage node contact 24 is exposed. This contact hole 61 is a region where a capacitor is formed later. Next, as shown in FIG.
A metal film, for example, a Ru film 62 is formed on the entire surface by using the VD method. As a result, the Ru film 62 comes into contact with the storage node contact 24.

Next, as shown in FIG. 35, a portion of the Ru film 62 above the upper surface of the interlayer insulating film 60 is removed by using a planarization technique, for example, a CMP method. Next, as shown in FIG. 36, a strontium oxide film 63, which is a film containing strontium, is deposited using, for example, a CVD method. At this time, for example, Sr (D
PM) ₂ (strontium bis (dipivaloylmethanate): S
r [(CH ₃ ) ₃ C-COCHCO- (C (CH ₃ ) ₃ )] ₂ ) is converted to THF (tetrahyd
A strontium oxide film 63 is deposited by performing CVD in an oxidizing atmosphere at about 300 to 500 ° C. using a substance dissolved in a solution and gasified by a vaporizer. Alternatively, Sr (DPM) ₂ vaporized by a sublimation method may be used as a source gas. Here, the strontium-containing film may be a strontium carbonate film. Further, a strontium film may be used. However, the strontium oxide film and the strontium carbonate film are easier to deposit by the CVD method than the strontium film.
Further, the CVD method has been described as an example of the method of depositing the coating, but a sputtering method or a sol-gel method may be used.

Next, as shown in FIG. 37, by annealing in an oxidizing atmosphere such as oxygen or ozone,
A reaction is caused between the strontium oxide film 63 and the Ru film 62 to form an SRO film 64 as a metal oxide in a self-aligned manner. The SRO film 64 thus formed
Has the same metal element as the Ru film 62.
Here, the CVD process of the strontium oxide film 63 (FIG. 3)
6) is performed in an oxidizing atmosphere at about 500 to 700 ° C., a strontium oxide film 63 is deposited, and at the same time, a reaction occurs at the interface between the Ru film 62 which is a metal film and the strontium oxide film 63, and the metal oxide Is formed in a self-aligned manner. In this case, the annealing step shown in FIG. 37 can be omitted. Next, FIG.
As shown in (1), unreacted strontium oxide film 63 is removed by washing with water or wet etching in dilute acid. Ru film 62 and SRO film 6 remaining here
4 becomes the storage node of the capacitor. Next, as shown in FIG. 39, a BSTO film 65 as a high dielectric film is formed on the entire surface by using the CVD method. Further, an SRO film 66 of a metal oxide is formed on the entire surface by using the CVD method. This BSTO film 65 becomes a capacitor insulating film,
The SRO film 66 becomes a plate electrode.

Next, although not shown, a lithography method and an etching technique are used to form a plate electrode SR.
The O film 66 is processed into a desired shape. Thereby, a capacitor is formed. This capacitor has a Ru film 62 whose storage node is a metal film and an SRO metal oxide.
The capacitor insulating film is a BSTO film 65 which is a high dielectric film, and the plate electrode is an SRO film 66 which is a metal oxide. Here, a BSTO film 65 which is a capacitor insulating film and an SRO film 6 which is a plate electrode
6 and the SRO film 64 forming the storage node both have a perovskite-like crystal structure. Thereby, the BSTO film 65, which is a high dielectric film, can exhibit its performance to the maximum. As described above, according to the third embodiment of the present invention, the following effects can be obtained. First, according to the third embodiment, after depositing an interlayer insulating film 60, this is etched by RIE or the like to form a contact hole 61, thereby determining the region of the storage node (FIG. 3).
3). Then, Ru is formed in the contact hole 61.
By forming the film 62 (see FIGS. 34 and 35),
The storage node is substantially processed, and an SRO film 64 as a metal oxide is formed in a self-aligned manner by a reaction between the Ru film 62 and the strontium oxide film 63 (see FIG. 37). According to this, the storage node can be processed by the etching technique of the interlayer insulating film 60 and the CMP technique of the Ru film 62 which is a metal film.
As described above, even if a metal oxide such as an SRO film is used as a storage node, the processing can be prevented from becoming difficult, and fine processing can be performed. As a result, a highly reliable and high-density semiconductor device can be formed.

A Ru film 62 as a metal film is formed between the storage node contact 24 and the SRO film 64 forming the storage node. Therefore, even if a tungsten film, which is a low-resistance metal film, is used as the storage node contact 24, the storage node contact 24 does not directly contact the SRO film 64. Therefore, it is not necessary to form a thin barrier metal layer at the interface. This makes it possible to prevent an increase in the number of manufacturing steps. Here, in order to prevent the contact between the tungsten film forming the storage node contact and the SRO film forming the storage node, it is conceivable that the storage node is a laminated film of the SRO film and the titanium nitride film (functioning as a barrier metal). Can be However, if the storage node is simply a stacked film, the titanium nitride film and the BSTO film 65 come into contact with each other, which deteriorates the leakage characteristics of the capacitor current. On the other hand, according to the third embodiment of the present invention, such a problem can be solved. The storage node is mainly composed of a Ru film 62, which is a metal film, and an SRO film 64, which is a metal oxide, is formed at a portion in contact with the BSTO film 65, which is a high dielectric film. An SRO film 66 made of a metal oxide is used as the plate electrode. Thus, by sandwiching the high dielectric film between the metal oxides, the performance of the high dielectric film can be maximized. Further, since the storage node is mainly composed of a metal film, the resistivity can be made lower than in the case where the storage node is composed of only a metal oxide. Thus, the speed of the semiconductor device can be increased.

Further, a CVD step (see FIG. 36) of forming a strontium oxide film 63 using a CVD method
If performed in a relatively low temperature oxidizing atmosphere of about 500 ° C.,
It is possible to reduce a high-temperature heat process which is a problem in optimizing a transistor and adopting a silicide structure.
On the other hand, if the CVD process is performed in a relatively high temperature oxidizing atmosphere of about 500 to 700 ° C., the SRO film 64 can be formed simultaneously with the deposition of the strontium oxide film 63, and the number of processes can be reduced. It becomes possible. In each of the above embodiments, a planar capacitor is used as the capacitor shape.
Although the inner moat type and the outer moat type have been described, the present invention can be applied to other structures such as a crown type and a fin type. Further, the present invention is not limited to a DRAM, but can be applied to a general semiconductor device having a capacitor structure such as an FRAM. The combination of the metal film forming the storage node and the film deposited on the metal film to form the metal oxide is different from the combination of the Ru (ruthenium) film and the strontium oxide film as described above. In addition, any combination of a metal and a film forming a conductive metal oxide (or a conductive perovskite-like structure substance) may be used.

[0030]

As described above, the present invention enables miniaturization while using a conductive metal oxide for a capacitor storage electrode. Further, the speed of the semiconductor device can be increased.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a manufacturing process of a conventional capacitor electrode.

FIG. 2 is a sectional view showing a manufacturing process of a conventional capacitor electrode.

FIG. 3 is a cross-sectional view showing a manufacturing process of a conventional capacitor electrode.

FIG. 4 is a sectional view of a manufacturing process of a conventional capacitor electrode.

FIG. 5 is a sectional view showing a manufacturing process of a conventional capacitor electrode.

FIG. 6 is a sectional view showing a manufacturing process of a conventional capacitor electrode.

FIG. 7 is a sectional view showing a manufacturing process of a conventional capacitor electrode.

FIG. 8 is a cross-sectional view showing a manufacturing process of a conventional capacitor electrode.

FIG. 9 is a sectional view of a manufacturing process of a conventional capacitor electrode.

FIG. 10 is a sectional view showing a manufacturing process of a conventional capacitor electrode.

FIG. 11 is a top layout view of the semiconductor device according to the first embodiment of the present invention;

FIG. 12 is a sectional view of the semiconductor device according to the first embodiment of the present invention;

FIG. 13 is a sectional view of the semiconductor device according to the first embodiment of the present invention;

FIG. 14 is a sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 15 is a sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 16 is a sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 17 is a sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 18 is a sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 19 is a sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 20 is a sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 21 is a sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 22 is a sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 23 is a sectional view of a semiconductor device according to a modification of the first embodiment of the present invention.

FIG. 24 is a sectional view of a semiconductor device according to a modification of the first embodiment of the present invention.

FIG. 25 is a sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 26 is a sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention;

FIG. 27 is a sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention;

FIG. 28 is a sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention;

FIG. 29 is a sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention;

FIG. 30 is a sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention;

FIG. 31 is a sectional view of a semiconductor device according to a modification of the second embodiment of the present invention;

FIG. 32 is a sectional view showing the manufacturing process of the semiconductor device according to the third embodiment of the present invention;

FIG. 33 is a sectional view showing the manufacturing process of the semiconductor device according to the third embodiment of the present invention;

FIG. 34 is a sectional view showing the manufacturing process of the semiconductor device according to the third embodiment of the present invention;

FIG. 35 is a sectional view showing the manufacturing process of the semiconductor device according to the third embodiment of the present invention;

FIG. 36 is a sectional view showing the manufacturing process of the semiconductor device according to the third embodiment of the present invention;

FIG. 37 is a sectional view showing the manufacturing process of the semiconductor device according to the third embodiment of the present invention;

FIG. 38 is a sectional view showing the manufacturing process of the semiconductor device according to the third embodiment of the present invention.

FIG. 39 is a sectional view showing the manufacturing process of the semiconductor device according to the third embodiment of the present invention;

[Explanation of symbols]

1. Semiconductor substrate 2. Silicon oxide film 3. Titanium nitride film 4. SRO film 5. BSTO film 6. SRO film 7. Tungsten film 8. Silicon oxide film 9. Contact hole 10. ... SRO film 11 ... BSTO film 12 ... SRO film 13 ... Top of SRO film 10 MC ... Capacitor MQ ... MOS transistor 21 ... Word line 22 ... Bit line contact 23 ... Bit line 24 ... Storage Node contact 25 Storage node 26 Source / drain diffusion layer 27 Interlayer insulating film 28 Metal oxide 29 High dielectric film 30 Metal oxide 31 MOS transistor 32 Source / Drain region 33 Wiring 34 Coating insulating film 35 Second interlayer insulating film 36 Contact 37 Upper wiring 38 ... Semiconductor substrate 39 ... Element isolation region 40 ... Titanium nitride film 41 ... Tungsten film 42 ... Gate insulating film 43 ... Conducting layer 44 ... Insulating film 45 ... Ru film 46 ... Strontium oxide film 47 ... SRO film 48 BSTO film 49 SRO film 50 Capacitor 51 SrWO ₃ 52 Ru film SRO film 54 Ru film 55 Ru film 56 Strontium oxide film 57 SRO film 58 ··· BSTO film 59 ··· SRO film 60 ···· Interlayer insulating film 61 ···· Contact hole 62 ···· Ru film 63 ····· Strontium oxide film 64 ····· SRO film 65 ····· BSTO film 66 ···· SRO film 67 ..Metal film

Claims (14)

[Claims] A first capacitor electrode having a stacked structure including a plurality of conductive films containing a common metal element; a capacitor insulating film formed on a surface of the first capacitor electrode; A second capacitor electrode formed so as to face the first capacitor electrode with the second capacitor electrode interposed therebetween. 2. The semiconductor device according to claim 1, wherein the first capacitor electrode has a stacked structure including a conductive oxide. 3. The semiconductor device according to claim 1, wherein the first capacitor electrode is a stacked film including a metal film and a conductive oxide. 4. The semiconductor device according to claim 1, wherein said capacitor insulating film is a high dielectric film. 5. The semiconductor device according to claim 3, wherein the metal film is a Ru (ruthenium) film, and the conductive oxide is an SRO (SrRuO ₃ ) film. 6. The semiconductor device according to claim 2, wherein the metal film is a Ru (ruthenium) film, the conductive oxide is an SRO (SrRuO ₃ ) film, and the capacitor insulating film is a BSTO film. 4. The semiconductor device according to 3. 7. The conductive oxide having a perovskite-like structure.
13. The semiconductor device according to claim 1. 8. A step of forming a film containing a metal, a step of forming a film on the surface of the film containing a metal, and reacting the film containing the metal with the film by heat treatment to form a conductive oxide. Forming, forming a capacitor insulating film on the surface of the conductive oxide, and forming a capacitor electrode at a position facing the conductive oxide with the capacitor insulating film interposed therebetween. A method of manufacturing a semiconductor device. 9. A step of forming a film containing a metal, a step of forming a film on the surface of the film containing the metal, and simultaneously reacting the film containing the metal with the film to form a conductive oxide. Forming a capacitor insulating film on the surface of the conductive oxide; and forming a capacitor electrode at a position facing the conductive oxide with the capacitor insulating film interposed therebetween. Semiconductor device manufacturing method. 10. The method of manufacturing a semiconductor device according to claim 8, further comprising a step of removing an unreacted one of the insulating films. 11. The semiconductor device according to claim 8, wherein the film containing the metal and the conductive oxide have a common metal element.
11. The method for manufacturing a semiconductor device according to any one of claims 10 to 10. 12. The method according to claim 8, wherein the conductive oxide and the capacitor insulating film both have a perovskite structure. 13. The method according to claim 8, wherein the capacitor insulating film is a high dielectric film. 14. The method according to claim 8, wherein the metal is Ru (ruthenium), and the conductive oxide is an SRO (SrRuO ₃ ) film.