KR20020050923A - Method for forming metal lines in manufacturing process of semiconductor device - Google Patents

Method for forming metal lines in manufacturing process of semiconductor device Download PDF

Info

Publication number
KR20020050923A
KR20020050923A KR1020000080228A KR20000080228A KR20020050923A KR 20020050923 A KR20020050923 A KR 20020050923A KR 1020000080228 A KR1020000080228 A KR 1020000080228A KR 20000080228 A KR20000080228 A KR 20000080228A KR 20020050923 A KR20020050923 A KR 20020050923A
Authority
KR
South Korea
Prior art keywords
barrier
copper layer
copper
forming
manufacturing process
Prior art date
Application number
KR1020000080228A
Other languages
Korean (ko)
Inventor
권성수
김봉천
Original Assignee
박종섭
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 박종섭, 주식회사 하이닉스반도체 filed Critical 박종섭
Priority to KR1020000080228A priority Critical patent/KR20020050923A/en
Publication of KR20020050923A publication Critical patent/KR20020050923A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric

Abstract

PURPOSE: A formation method of an interconnection is provided to form a copper layer having an equal thickness by removing a barrier through a chemical processing. CONSTITUTION: After forming a trench(9) in an oxide(8) and a silicon substrate(7), a barrier(10) and a copper layer(11) are sequentially formed to fill into the trench(9). At this time, the barrier(10) forming material is adequately made of a TiN so as to prevent a diffusion phenomenon between the copper layer(11) used as an interconnection and the oxide(8). Then, the copper layer(11) is etched to expose the barrier(10) using a CMP(Chemical Mechanical Polishing). Then, the exposed barrier(10) is removed by dipping a wafer formed with the detailed structure to a NH4OH solution. At this time, the TiN composing the barrier(10) is chemically reacted with the NH4OH solution and removed, thereby preventing a dishing and a corrosion phenomena on the copper layer(11) so as to get the flat surface of the copper layer(11).

Description

반도체 소자 제조 공정의 배선 형성 방법{Method for forming metal lines in manufacturing process of semiconductor device}Method for forming metal lines in manufacturing process of semiconductor device

본 발명은 반도체 소자 제조 공정에 관한 것으로서, 보다 상세하게는 상감 방식으로 구리 배선을 형성할 때 배리어(barrier)를 식각액으로 제거함으로써 폴리싱에 의한 침식 및 디싱의 발생을 방지한 반도체 소자 제조 공정의 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing process. More particularly, when forming copper wiring in an inlaid manner, a barrier is removed with an etchant to prevent erosion and dishing caused by polishing. It relates to a forming method.

종래의 구리 상감 공정 방법에서는 우선, 도 1에 도시된 바와 같이 실리콘 기판(1) 상부에 산화막(2)이 증착되며, 구리 배선이 필요한 영역은 식각에 의하여 트렌치(trench)(3)로 식각된 후 그 상부에 확산 방지를 위한 배리어(4)가 증착되고, 배리어(4) 상부에 배선 형성을 위한 구리 막질(5)이 증착된다.In the conventional copper inlay process method, first, as shown in FIG. 1, an oxide film 2 is deposited on a silicon substrate 1, and an area requiring copper wiring is etched into a trench 3 by etching. After that, a barrier 4 for diffusion prevention is deposited on top of it, and a copper film 5 for wiring formation is deposited on top of the barrier 4.

그 후 배선을 형성하기 위하여 도 2와 같이 화학적 물리적 폴리싱에 의해 트렌치 영역(3)을 제외한 영역의 구리 막질(5)이 제거된다.Thereafter, as shown in FIG. 2, the copper film 5 in the region excluding the trench region 3 is removed by chemical and physical polishing to form a wiring.

이 후, 도 3에 도시된 바와 같이 화학적 물리적 폴리싱에 의해 배리어(4)가 제거된다. 이 때, 실제 공정에서 증착이나 폴리싱의 불균일성과 패턴 의존성에 기인하여 구리와 배리어가 완전히 제거되지 못하고 남는 현상을 방지하기 위해, 도 4와 같이 오버 폴리싱 (over-polishing)이 수행된다.Thereafter, the barrier 4 is removed by chemical physical polishing as shown in FIG. At this time, over-polishing is performed as shown in FIG. 4 in order to prevent the copper and the barrier from being completely removed due to the non-uniformity and pattern dependency of deposition or polishing in the actual process.

그러나, 이러한 오버 폴리싱은 구리 막질(5)의 면적이 넓은 곳에서는 디싱 현상이 발생되며, 하부 막질의 패턴이 조밀하지 않은 곳에서는 침식 현상에 의하여 구리의 두께가 변화되는 문제점이 있다.However, this over polishing has a problem in that dishing occurs in a large area of the copper film 5, and a thickness of copper is changed by erosion in a place where the pattern of the lower film quality is not dense.

따라서, 본 발명은 상술한 바와 같은 종래 반도체 메모리 장치의 구리 상감 공정 방법의 문제점을 해결하기 위해 이루어진 것으로, 본 발명의 목적은 화학적 부식을 통해 배리어를 제거하여 침식과 디싱의 발생을 방지함에 있다.Accordingly, the present invention has been made to solve the problems of the copper inlay processing method of the conventional semiconductor memory device as described above, the object of the present invention is to prevent the occurrence of erosion and dishing by removing the barrier through chemical corrosion.

도 1 내지 도 4는 반도체 소자 제조 공정 중 구리 상감 공정을 나타내는 단면도1 to 4 are cross-sectional views illustrating copper inlay processes in a semiconductor device manufacturing process.

도 5 내지 도 7은 본 발명에 따른 반도체 소자 제조 공정의 배선 형성 방법의 바람직한 실시예를 나타내는 단면도5 to 7 are cross-sectional views showing a preferred embodiment of a wiring forming method of a semiconductor device manufacturing process according to the present invention.

상기 목적을 달성하기 위해, 본 발명의 반도체 메모리 장치의 구리 상감 공정 방법에서는 배리어를 형성 물질로 TiN이 사용되며, 배리어 제거 단계에서 TiN 배리어가 NH4OH용액과의 화학 반응에 의해 제거되도록 한다.In order to achieve the above object, in the copper inlay process method of the semiconductor memory device of the present invention, TiN is used as a barrier forming material, and the TiN barrier is removed by chemical reaction with NH 4 OH solution in the barrier removing step.

이하, 첨부된 도면을 참조하여 본 발명의 실시예를 상세히 설명하면 다음과 같다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

본 발명은 반도체 소자 제조 공정 중 배선을 형성하는 방법에 대한 것이며, 본 발명은 구리 배선을 트렌치에 상감하여 제조하는 공정을 실시예로 갖는다.The present invention relates to a method of forming a wiring in a semiconductor device manufacturing process, and the present invention has a process of manufacturing a copper wiring inlaid in a trench.

구체적으로, 도 5와 같이 실리콘 기판(7)의 산화막(8) 상에 트렌치(9)가 형성되고, 트렌치(9) 상부에 순차적으로 배리어(10)와 구리 막질(11)이 증착된다.Specifically, as shown in FIG. 5, a trench 9 is formed on the oxide film 8 of the silicon substrate 7, and the barrier 10 and the copper film 11 are sequentially deposited on the trench 9.

이 때, 배리어(10) 형성 물질은 배선으로 이용되는 구리와 산화막(8) 간의 확산현상을 방지하기 위한 것으로서, 바람직하게는 TiN 재질로 구성될 수 있다.At this time, the barrier 10 forming material is to prevent the diffusion phenomenon between the copper and the oxide film 8 used as the wiring, preferably made of a TiN material.

그리고, 구리 막질(11)은 배선을 형성하기 위한 것이다.The copper film 11 is for forming wiring.

다음 단계로서, 도 6에서와 같이 구리 막질(11)이 화학적 물리적 폴리싱에 의해 제거되고, 화학적 물리적 폴리싱은 배리어(10)가 노출될 때까지 진행된다.As a next step, the copper film 11 is removed by chemical physical polishing as in FIG. 6, and the chemical physical polishing proceeds until the barrier 10 is exposed.

이 후, 도 7과 같이 웨이퍼를 NH4OH 용액에 담그어 배리어(10)를 형성하는 TiN을 NH4OH와 반응시켜서 노출된 배리어(10)을 제거한다.Subsequently, the exposed barrier 10 is removed by immersing the wafer in the NH 4 OH solution as shown in FIG. 7 to form TiN, which forms the barrier 10, with NH 4 OH.

상술한 본 발명에 따른 배선 형성 방법의 실시예에 의하여, 도 7에 나타난 바와 같이 디싱이나 침식 등이 발생하지 않아 두께가 균일한 구리 배선이 형성될 수 있다.According to the embodiment of the wiring forming method according to the present invention described above, as shown in FIG. 7, dishing or erosion does not occur, and thus copper wiring having a uniform thickness may be formed.

이상 설명한 바와 같은 본 발명의 반도체 메모리 장치의 구리 상감 공정 방법은 화학 반응을 통해 배리어를 제거하므로 오버 폴리싱에 의해 구리 형성층에 디싱 및 침식 현상이 발생하지 않아 두께가 고른 구리 형성층을 얻을 수 있다.Since the copper damascene process method of the semiconductor memory device of the present invention as described above removes the barrier through a chemical reaction, dishing and erosion does not occur in the copper forming layer due to overpolishing, and thus a copper forming layer having an even thickness can be obtained.

한편, 본 발명은 상술한 실시예로만 한정되는 것이 아니라 본 발명의 요지를벗어나지 않는 범위내에서 수정 및 변형하여 실시할 수 있고, 이러한 수정 및 변경 등은 이하의 특허 청구의 범위에 속하는 것으로 보아야 할 것이다.On the other hand, the present invention is not limited only to the above-described embodiments, it can be carried out by modifying and modifying within the scope not departing from the gist of the present invention, such modifications and changes should be regarded as belonging to the following claims. will be.

Claims (2)

산화막 상에 트렌치를 형성한 후 구리 배선을 형성하는 반도체 소자 제조 공정의 배선 형성 방법에 있어서,In the wiring formation method of the semiconductor element manufacturing process of forming a copper wiring after forming a trench on an oxide film, 상기 트렌치와 상기 산화막 상에 배리어를 증착하는 배리어 형성 단계;A barrier forming step of depositing a barrier on the trench and the oxide film; 상기 배리어 위에 구리 막질을 증착하는 구리 증착 단계;A copper deposition step of depositing a copper film on the barrier; 상기 산화막 상의 상기 배리어가 노출되도록 상기 구리 막질을 폴리싱으로 제거하는 폴리싱 단계; 및Polishing to remove the copper film material by polishing so that the barrier on the oxide film is exposed; And 상기 산화막 상의 배리어를 식각액으로 제거하는 배리어 제거 단계;를 구비함을 특징으로 하는 반도체 소자 제조 공정의 배선 형성 방법.And a barrier removing step of removing the barrier on the oxide layer with an etching solution. 제 1 항에 있어서,The method of claim 1, 상기 배리어는 TiN 재질이고, 상기 식각액은 NH4OH 용액임을 특징으로 하는 반도체 소자 제조 공정의 배선 형성 방법.The barrier is a TiN material, the etching solution is a wire forming method of the semiconductor device manufacturing process, characterized in that the NH 4 OH solution.
KR1020000080228A 2000-12-22 2000-12-22 Method for forming metal lines in manufacturing process of semiconductor device KR20020050923A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020000080228A KR20020050923A (en) 2000-12-22 2000-12-22 Method for forming metal lines in manufacturing process of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020000080228A KR20020050923A (en) 2000-12-22 2000-12-22 Method for forming metal lines in manufacturing process of semiconductor device

Publications (1)

Publication Number Publication Date
KR20020050923A true KR20020050923A (en) 2002-06-28

Family

ID=27684578

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020000080228A KR20020050923A (en) 2000-12-22 2000-12-22 Method for forming metal lines in manufacturing process of semiconductor device

Country Status (1)

Country Link
KR (1) KR20020050923A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9865581B2 (en) 2014-11-13 2018-01-09 Samsung Electronics Co., Ltd. Method of fabricating multi-substrate semiconductor devices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9865581B2 (en) 2014-11-13 2018-01-09 Samsung Electronics Co., Ltd. Method of fabricating multi-substrate semiconductor devices

Similar Documents

Publication Publication Date Title
JP5268215B2 (en) Copper connection seed layer processing method and processing apparatus
KR100396883B1 (en) Slurry for chemical mechanical polishing and manufacturing method of copper metal interconnection layer using the same
US8211800B2 (en) Ru cap metal post cleaning method and cleaning chemical
US6645863B2 (en) Method of manufacturing semiconductor device and semiconductor device
US7071112B2 (en) BARC shaping for improved fabrication of dual damascene integrated circuit features
US6670272B2 (en) Method for reducing dishing in chemical mechanical polishing
KR20020050923A (en) Method for forming metal lines in manufacturing process of semiconductor device
CN109887880B (en) Semiconductor connection structure and manufacturing method thereof
KR20020010811A (en) Method for forming metal interconnection
KR0172042B1 (en) Method of manufacturing tungsten plug of semiconductor device
KR100315039B1 (en) Method for forming metal interconnection line of semiconductor device
KR100507868B1 (en) Wiring Formation Method of Semiconductor Device
KR100431086B1 (en) Method of forming a copper wiring in a semiconductor device
KR100476037B1 (en) Method for forming Cu wiring of semiconductor device
KR100814259B1 (en) Method of manufacturing semiconductor device
KR100347533B1 (en) Method of forming a metal wiring in a semiconductor device
KR100732737B1 (en) Method for forming isolation layer of semiconductor device
KR100737701B1 (en) Method of manufacturing wire in a semiconductor device
KR100284139B1 (en) Tungsten plug formation method of semiconductor device
KR100321156B1 (en) Method for forming metal interconnection line of semiconductor device
KR100567913B1 (en) Method of forming a metal wiring in a semiconductor device
KR100528449B1 (en) Method for forming damascene type metal wire in semiconductor device using chemical mechanical planarization and spin etch process
KR20050032435A (en) Method of forming plug of semiconductor device
KR100312647B1 (en) Planarization method of semiconductor device
KR100557916B1 (en) Metal film CMP method

Legal Events

Date Code Title Description
N231 Notification of change of applicant
WITN Withdrawal due to no request for examination