KR100347533B1 - Method of forming a metal wiring in a semiconductor device - Google Patents

Method of forming a metal wiring in a semiconductor device Download PDF

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KR100347533B1
KR100347533B1 KR1019990061795A KR19990061795A KR100347533B1 KR 100347533 B1 KR100347533 B1 KR 100347533B1 KR 1019990061795 A KR1019990061795 A KR 1019990061795A KR 19990061795 A KR19990061795 A KR 19990061795A KR 100347533 B1 KR100347533 B1 KR 100347533B1
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insulating film
thin film
forming
copper
copper thin
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KR1019990061795A
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Korean (ko)
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KR20010063718A (en
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김형준
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 구리 박막을 형성한 후 셀 영역과 구리 패드 영역 사이에 존재하는 단차에 의한 디싱 현상을 감소시키기 위해 구리 박막 상부에 연마 정지막으로 절연막을 형성하고, 셀 영역 및 구리 패드 영역의 단차가 없어질 때까지 1차 연마 공정을 실시한 후 절연막, 구리 박막 및 장벽 금속층의 연마 선택비가 1:1:1인 슬러리를 이용하여 2차 연마를 실시함으로써 구리 배선을 형성하는 반도체 소자의 금속 배선 형성 방법이 제시된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring of a semiconductor device, and after forming a copper thin film, an insulating film is formed on the copper thin film by a polishing stop layer to reduce dishing phenomenon due to a step difference between the cell region and the copper pad region. After performing the primary polishing process until the step between the cell region and the copper pad region is eliminated, the secondary polishing is performed using a slurry having a polishing selectivity of 1: 1: 1 of the insulating film, the copper thin film and the barrier metal layer. A method of forming metal wirings of a semiconductor element for forming wirings is provided.

Description

반도체 소자의 금속 배선 형성 방법{Method of forming a metal wiring in a semiconductor device}Method of forming a metal wiring in a semiconductor device

본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 특히 구리 박막을 형성한 후 연마 속도가 매우 느린 박막을 추가 증착하여 CMP 공정을 실시함으로써 과도 연마를 실시하지 않고도 평탄도를 향상시킬 수 있고, 디싱 현상도 줄일 수 있는 반도체 소자의 금속 배선 형성 방법에 관한 것이다.The present invention relates to a method for forming a metal wiring of a semiconductor device, and in particular, by forming a copper thin film and further depositing a thin film having a very low polishing rate to perform a CMP process, thereby improving flatness without performing excessive polishing. The present invention relates to a metal wiring forming method of a semiconductor device that can reduce dishing phenomenon.

구리를 이용한 반도체 소자의 금속 배선 형성 방법을 개략적으로 설명하면 다음과 같다. 소정의 구조가 형성된 반도체 기판 상부에 층간 절연막을 형성하고, 층간 절연막의 소정 영역을 식각하여 반도체 기판의 소정 영역을 노출시킨다. 전체 구조 상부에 Ta, TaN등으로 장벽 금속층을 형성하고 구리 박막을 형성한다. CMP 공정을 이용한 평탄화 공정을 통해 층간 절연막 상부에 있는 모든 금속 박막을 제거한다.A method of forming metal wirings of a semiconductor device using copper will be described as follows. An interlayer insulating film is formed on the semiconductor substrate having a predetermined structure, and a predetermined region of the interlayer insulating film is etched to expose a predetermined region of the semiconductor substrate. A barrier metal layer is formed of Ta, TaN, etc. on the entire structure, and a copper thin film is formed. A planarization process using a CMP process removes all metal thin films on the interlayer insulating film.

상기와 같은 구리를 이용한 반도체 소자의 금속 배선 형성 공정에서 CMP 공정은 2단계로 나누어 실시한다. 먼저 연마 속도가 빠른 슬러리를 이용하여 구리 박막의 80% 이상을 제거하고, 구리 박막, 장벽 금속층 및 층간 절연막의 연마비가 1:1:1인 슬러리를 사용하여 남아있는 구리 박막과 장벽 금속층을 동일한 연마 속도로 제거한다.In the metal wiring forming process of the semiconductor device using copper as described above, the CMP process is performed in two stages. First, more than 80% of the copper thin film is removed using a slurry having a high polishing rate, and the remaining copper thin film and the barrier metal layer are identically polished using a slurry having a polishing ratio of 1: 1: 1 of the copper thin film, the barrier metal layer, and the interlayer insulating film. Remove at speed.

그런데, 전기 도금(electroplating)에 의해 증착된 구리 박막의 패턴 프로파일은 밀도가 높은 셀 지역에서는 평탄하지만 테스트 패턴 지역의 수백㎛ 크기의 구리 패드에는 셀 지역에 비해 어느 정도 단차가 존재하게 된다. 2단계 구리 박막 및 장벽 금속층의 동시 연마 공정에서 연마비가 1:1:1인 슬러리를 사용하기 위해서는 1단계 구리 연마 공정에서 완전 평탄화가 이루어져야 한다. 그러나 셀 지역과 테스트 패턴 지역에 존재하는 단차는 1단계 공정을 통해 제거되기 어렵기 때문에 1단계공정에서 단차가 완벽하게 제거되지 않는다면 2단계 공정에서 구리와 장벽 금속층의 제거만으로 디싱을 줄일 수 없게 된다. 이 경우 디싱을 줄이기 위해서는 층간 절연막을 일정 부분 추가 연마해야 하기 때문에 추가 연마량을 고려한 층간 절연막의 증착과 CMP 공정을 실시한 후 평탄도가 저하되는 문제점이 발생한다. 현재 통상적으로 사용되는 층간 절연막의 추가 연마량은 평균 2000Å 정도로서 2단계에서 사용되는 연마비가 1:1:1인 슬러리의 연마 속도가 분당 500Å이라는 점을 감안한다면 장벽 금속층이 제거된 후 추가적으로 약 4분 정도 연마를 해야 한다. 4분 추가 연마는 막대한 추가 공정 비용에 해당되어 반도체 소자의 제조 공정에서 CMP 공정 자체만으로도 큰 부담으로 작용하게 된다.By the way, the pattern profile of the copper thin film deposited by electroplating is flat in a high density cell area, but there are some steps in the copper pad of several hundred micrometers in the test pattern area compared to the cell area. In order to use a slurry having a polishing ratio of 1: 1: 1 in a simultaneous polishing process of a two-step copper thin film and a barrier metal layer, complete flattening must be performed in a one-step copper polishing process. However, the level difference in the cell area and the test pattern area is difficult to remove through the first step process. If the step is not completely removed in the first step process, the removal of the copper and barrier metal layers in the second step process cannot reduce the dishing. . In this case, since the interlayer insulating film needs to be additionally polished to reduce dishing, flatness may be reduced after the deposition of the interlayer insulating film and the CMP process in consideration of the additional polishing amount. The average amount of additional polishing of the interlayer insulating film currently used is about 2000 kPa, and the polishing rate of the slurry having a polishing ratio of 1: 1: 1 used in the second stage is 500 kPa / min, which is about 4 minutes after the barrier metal layer is removed. You have to polish it. The additional 4 minutes of polishing is a huge additional process cost, and thus the CMP process itself is a huge burden in the semiconductor device manufacturing process.

따라서, 본 발명은 구리 박막을 형성한 후 연마 속도가 매우 느린 박막을 추가 증착하여 CMP 공정을 실시함으로써 과도 연마를 실시하지 않고도 평탄도를 향상시킬 수 있고, 디싱 현상도 줄일 수 있는 반도체 소자의 금속 배선 형성 방법을 제공하는데 그 목적이 있다.Therefore, the present invention can improve the flatness without performing excessive polishing by performing a CMP process by additionally depositing a thin film having a very low polishing rate after forming a copper thin film, and can reduce the dishing phenomenon. It is an object of the present invention to provide a wiring forming method.

상술한 목적을 달성하기 위한 본 발명은 반도체 기판 상부에 형성된 층간 절연막의 소정 영역을 식각하여 상기 반도체 기판의 소정 영역을 노출시킨 후 전체 구조 상부에 장벽 금속층 및 구리 박막을 형성하되, 패턴 밀도가 높은 셀 영역과 구리 패드 영역 사이에 단차가 존재하는 반도체 소자의 금속 배선 형성 방법에 있어서, 전체 구조 상부에 절연막을 형성하는 단계와, 상기 셀 영역과 구리 패드 영역 사이에 단차가 제거될 때까지 상기 절연막 및 상기 구리 박막을 1차 화학적기계적 연마하는 단계와, 상기 잔류하는 절연막, 구리 박막 및 장벽 금속층이 제거되어 층간 절연막을 노출시킬 때까지 2차 화학적기계적 연마 공정을 실시하는 단계를 포함하여 이루어진 것을 특징으로 한다.The present invention for achieving the above object is to expose a predetermined region of the semiconductor substrate by etching a predetermined region of the interlayer insulating film formed on the semiconductor substrate, and to form a barrier metal layer and a copper thin film on the entire structure, the pattern density is high A method of forming a metal wiring of a semiconductor device in which a step is present between a cell region and a copper pad region, the method comprising: forming an insulating film over an entire structure, and forming the insulating film until the step is removed between the cell region and the copper pad region. And chemically polishing the copper thin film and performing a second chemical mechanical polishing process until the remaining insulating film, the copper thin film, and the barrier metal layer are removed to expose the interlayer insulating film. It is done.

도 1(a) 내지 도 1(c)는 본 발명에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도.1 (a) to 1 (c) are cross-sectional views of devices sequentially shown in order to explain a method for forming metal wirings of a semiconductor device according to the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

11 : 반도체 기판 12 : 층간 절연막11 semiconductor substrate 12 interlayer insulating film

13 : 장벽 금속층 14 : 구리 박막13 barrier metal layer 14 copper thin film

15 : 절연막15: insulating film

첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.The present invention will be described in detail with reference to the accompanying drawings.

도 1(a) 내지 도 1(c)는 본 발명에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도이다.1 (a) to 1 (c) are cross-sectional views of devices sequentially shown in order to explain a method for forming metal wirings of a semiconductor device according to the present invention.

도 1(a)를 참조하면, 소정의 구조가 형성된 반도체 기판(11) 상부에 층간 절연막(12)을 형성한다. 층간 절연막(12)의 소정 부분을 식각하여 반도체 기판(11)의 소정 영역을 노출시킨다. 전체 구조 상부에 Ta, TaN등과 같은 장벽 금속층(13)을 형성한 후 구리 박막(14)을 형성한다. 이에 의해 패턴 밀도가 높은 셀 영역과 테스트 패턴 영역의 구리 패드 영역 사이에 단차가 존재하게 된다. 구리 박막(14)은 전기 도금법에 의해 증착한다. 전체 구조 상부에 연마 정지막으로 사용되는 절연막(15)을 형성한다. 절연막(15)은 이후 2차 연마 공정에서 사용되는 슬러리에 의해 장벽 금속층(13) 및 구리 박막(14)과 연마 선택비가 동일한 물질로 형성한다.Referring to FIG. 1A, an interlayer insulating layer 12 is formed on a semiconductor substrate 11 on which a predetermined structure is formed. A predetermined portion of the interlayer insulating layer 12 is etched to expose a predetermined region of the semiconductor substrate 11. After forming a barrier metal layer 13 such as Ta, TaN, etc. on the entire structure, a copper thin film 14 is formed. As a result, a step is present between the cell region having a high pattern density and the copper pad region of the test pattern region. The copper thin film 14 is deposited by electroplating. An insulating film 15 used as a polishing stop film is formed over the entire structure. The insulating film 15 is then formed of a material having the same polishing selectivity as the barrier metal layer 13 and the copper thin film 14 by the slurry used in the secondary polishing process.

도 1(b)는 제 1 슬러리를 이용한 1차 CMP 공정을 실시하여 셀 영역과 패드 영역의 단차가 없어질 때까지 연마 공정을 실시한 상태의 단면도이다. 패턴 밀도가 높은 셀 영역의 절연막(15)은 구리 패드 영역보다 빨리 연마되기 때문에절연막(15)이 제거되어 구리 박막(15)이 노출되면 셀 영역의 구리 박막(15)은 매우 빠른 속도로 제거된다. 이때 패드 영역에는 아직 절연막(15)이 잔류하는 상태이며, 셀 영역과 패드 영역간의 단차가 없어질 때까지 연마 공정을 실시한다.FIG. 1B is a cross-sectional view of a polishing process performed by performing a first CMP process using a first slurry until there is no step difference between the cell region and the pad region. Since the insulating film 15 of the cell region having a high pattern density is polished faster than the copper pad region, when the insulating film 15 is removed and the copper thin film 15 is exposed, the copper thin film 15 of the cell region is removed at a very high speed. . At this time, the insulating film 15 still remains in the pad region, and the polishing process is performed until there is no step difference between the cell region and the pad region.

도 1(c)는 제 2 슬러리를 이용한 2차 CMP 공정을 실시하여 층간 절연막(12)을 노출시켜 구리 배선을 형성한 상태의 단면도이다. 제 2 슬러리는 절연막(15), 구리 박막(14) 및 장벽 금속층(13)의 연마 선택비가 1:1:1인 슬러리이다.FIG. 1C is a cross-sectional view of a copper wiring formed by exposing the interlayer insulating film 12 by performing a second CMP process using a second slurry. The second slurry is a slurry in which the polishing selectivity of the insulating film 15, the copper thin film 14, and the barrier metal layer 13 is 1: 1: 1.

상술한 바와 같이 본 발명에 의하면 2단계 연마 공정을 실시하기 전에 평탄화가 이루어졌고 2단계 연마 공정에서 연마 대상막들의 연마 속도가 동일하여 디싱을 감소시키기 위한 추가적인 과도 연마를 실시하지 않아도 되기 때문에 통상적인 구리의 CMP 공정에서 발생하는 층간 절연막의 추가적인 연마 없이 디싱을 크게 줄일 수 있고, 비용 절감과 공정 마진을 동시에 확보할 수 있다.As described above, according to the present invention, since the planarization is performed before the two-step polishing process and the polishing rate of the films to be polished is the same in the two-step polishing process, no additional excessive polishing is required to reduce dishing. Dicing can be greatly reduced without additional polishing of the interlayer insulating film generated in the CMP process of copper, and cost reduction and process margin can be secured simultaneously.

Claims (3)

반도체 기판 상부에 형성된 층간 절연막의 소정 영역을 식각하여 상기 반도체 기판의 소정 영역을 노출시킨 후 전체 구조 상부에 장벽 금속층 및 구리 박막을 형성하되, 패턴 밀도가 높은 셀 영역과 구리 패드 영역 사이에 단차가 존재하는 반도체 소자의 금속 배선 형성 방법에 있어서,A predetermined region of the interlayer insulating layer formed on the semiconductor substrate is etched to expose the predetermined region of the semiconductor substrate, and a barrier metal layer and a copper thin film are formed on the entire structure, and a step difference is formed between the cell region and the copper pad region having a high pattern density. In the metal wiring formation method of a semiconductor element which exists, 전체 구조 상부에 절연막을 형성하는 단계와,Forming an insulating film on the entire structure; 상기 셀 영역과 구리 패드 영역 사이에 단차가 제거될 때까지 상기 절연막 및 상기 구리 박막을 1차 화학적기계적 연마하는 단계와,Primary chemical mechanical polishing of the insulating film and the copper thin film until the step is removed between the cell region and the copper pad region; 상기 잔류하는 절연막, 구리 박막 및 장벽 금속층이 제거되어 층간 절연막을 노출시킬 때까지 2차 화학적기계적 연마 공정을 실시하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.And performing a second chemical mechanical polishing process until the remaining insulating film, the copper thin film, and the barrier metal layer are removed to expose the interlayer insulating film. 제 1 항에 있어서, 상기 2차 화학적기계적 연마 공정은 상기 절연막, 구리 박막 및 장벽 금속층의 연마 선택비가 1:1:1인 슬러리를 이용하여 실시하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.The method of claim 1, wherein the secondary chemical mechanical polishing process is performed using a slurry having a polishing selectivity of the insulating film, the copper thin film, and the barrier metal layer in a ratio of 1: 1: 1. 삭제delete
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