KR100528449B1 - Method for forming damascene type metal wire in semiconductor device using chemical mechanical planarization and spin etch process - Google Patents
Method for forming damascene type metal wire in semiconductor device using chemical mechanical planarization and spin etch process Download PDFInfo
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- KR100528449B1 KR100528449B1 KR10-1999-0023308A KR19990023308A KR100528449B1 KR 100528449 B1 KR100528449 B1 KR 100528449B1 KR 19990023308 A KR19990023308 A KR 19990023308A KR 100528449 B1 KR100528449 B1 KR 100528449B1
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 104
- 239000002184 metal Substances 0.000 title claims abstract description 104
- 238000000034 method Methods 0.000 title claims abstract description 46
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 239000000126 substance Substances 0.000 title claims abstract description 8
- 230000004888 barrier function Effects 0.000 claims abstract description 40
- 239000011229 interlayer Substances 0.000 claims abstract description 31
- 238000005498 polishing Methods 0.000 claims abstract description 19
- 239000002002 slurry Substances 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 8
- 239000010410 layer Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 2
- 230000003628 erosive effect Effects 0.000 abstract description 11
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 238000005516 engineering process Methods 0.000 abstract description 4
- 150000002739 metals Chemical class 0.000 description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract
본 발명은 반도체 제조 기술에 관한 것으로, 특히 반도체 소자 제조 공정 중 금속배선 형성 공정에 관한 것이며, 더 자세히는 상감형(damascene type) 금속배선 형성 공정에 관한 것이다. 본 발명은 베리어 금속/배선 금속으로 상감형 금속배선을 형성할 때, 금속 디싱 및 층간절연막 침식을 완화시킬 수 있는 반도체 소자의 금속배선 형성방법을 제공하는데 그 목적이 있다. 본 발명은 상감형 금속배선 형성시 베리어 금속과 배선 금속의 연마 선택비 차에 의해 발생하는 화학·기계적 평탄화(CMP) 공정시의 금속 디싱 및 층간절연막 침식 현상을 완화시키기 위하여, 금속의 평탄화와 베리어 금속의 평탄화에 각각 다른 프로세스 즉, CMP와 스핀 에치를 적용하는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a metal wiring forming process in a semiconductor device manufacturing process, and more particularly, to a damascene type metal wiring forming process. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a metal wiring of a semiconductor device capable of alleviating metal dishing and erosion of an interlayer insulating film when forming a damascene metal wiring with a barrier metal / wiring metal. In order to alleviate metal dishing and interlayer insulating film erosion during chemical and mechanical planarization (CMP) process caused by the difference in polishing selectivity between barrier metal and wiring metal when forming inlaid metal wiring, the planarization and barrier of metal It is a technique to apply different processes to the planarization of metal, that is, CMP and spin etch.
Description
본 발명은 반도체 제조 기술에 관한 것으로, 특히 반도체 소자 제조 공정 중 금속배선 형성 공정에 관한 것이며, 더 자세히는 상감형(damascene type) 금속배선 형성 공정에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a metal wiring forming process in a semiconductor device manufacturing process, and more particularly, to a damascene type metal wiring forming process.
반도체 소자의 고집적화에 따라 디자인 룰(design rule)의 축소가 가속되고 있으며, 이에 따라 금속배선의 피치(pitch)가 줄어들고 있어 통상적인 금속배선 공정을 적용할 경우에는 고단차비를 가지는 금속배선의 형성시 금속배선의 CD(critical dimension) 균일도(uniformity), 라인 식각 프로파일(line etch profile) 및 포토레지스트의 식각 선택비 등에서 만족할만한 결과를 얻기 힘들게 되었다. 이를 개선하기 위해서는 하드 마스크(hard mask) 등을 사용하여야 하며, 이에 따른 제조비용의 증가와 소자 개발 일정의 지연이라는 문제점이 도출된다.As the integration of semiconductor devices increases, the reduction of design rules is accelerating. As a result, the pitch of metal wiring is reduced. Therefore, when a metal wiring having a high step ratio is formed when a conventional metal wiring process is applied. Satisfactory results have not been obtained in the CD (critical dimension) uniformity of the metallization, the line etch profile and the etching selectivity of the photoresist. In order to improve this, a hard mask should be used, which leads to an increase in manufacturing cost and delay in device development schedule.
한편, 상감형 금속배선 공정은 상기의 문제점을 해결할 수 있는 기술로 차세대 초고집적 소자에 적용이 유망하다.On the other hand, the damascene metal wiring process is a technology that can solve the above problems is likely to be applied to the next generation ultra-high integration device.
상감형 금속배선 공정은 통상 층간절연막에 라인용 트렌치 및 콘택홀을 형성하고, 베리어 금속(Ti, TiN, Ta, TaN, WNx 등)과 배선 금속(Al, W, Cu 등)을 증착한 후 화학·기계적 평탄화(chemical mechanical planarization, CMP) 기술을 이용하여 층간절연막 상부에 있는 베리어 금속 및 배선 금속을 제거하는 과정을 거치고 있다.Inlaid metal wiring processes typically form line trenches and contact holes in an interlayer insulating film, and deposit barrier metals (Ti, TiN, Ta, TaN, WN x, etc.) and wiring metals (Al, W, Cu, etc.). Chemical and mechanical planarization (CMP) technology is used to remove the barrier metal and wiring metal on top of the interlayer insulating film.
CMP에 사용되는 슬러리(slurry)는 배선 금속과 베리어 금속에 대한 연마비가 동일한 것이 바람직하다. 그러나, 현 반도체 공정에 사용되는 배선 금속 및 베리어 금속에 같은 연마 특성을 나타내는 슬러리는 거의 없는 실정이다. 상용화된 슬러리의 경우, 베리어 금속에 대한 배선 금속의 연마선택비가 보통 3 이상이며, 연마선택비가 클수록 베리어 금속 연마 과정 중에 배선 금속의 디싱(dishing)과 층간절연막 침식(erosion) 현상이 심화된다. 즉, 금속 CMP 공정시 하부 층간절연막이 연마정지막으로 작용하기 때문에 층간절연막이 노출되는 순간부터 연마 속도는 현저히 떨어지게 된다. 이 과정에서 라인용 트렌치 부분에서는 계속 연마가 진행되어 디싱이 발생하게 되고, 금속배선 패턴이 밀집한 영역에서는 이러한 디싱에 의해 층간절연막의 단위 면적당 연마 압력이 증가하기 때문에 금속배선 패턴이 밀집하지 않은 영역에 비해 층간절연막의 연마가 빠르게 진행되는 층간절연막 침식 현상이 발생하게 된다.It is preferable that the slurry used for CMP has the same polishing ratio for the wiring metal and the barrier metal. However, there is almost no slurry exhibiting the same polishing characteristics in the wiring metal and the barrier metal used in the current semiconductor process. In the case of a commercially available slurry, the selection ratio of the wiring metal to the barrier metal is usually 3 or more, and the larger the selection ratio, the deeper dish dishing and erosion of the interlayer insulating film during the barrier metal polishing process. That is, since the lower interlayer insulating film acts as a polishing stop film during the metal CMP process, the polishing rate is remarkably decreased from the instant the interlayer insulating film is exposed. In this process, the trench for the line is continuously polished to cause dishing. In the region where the metal wiring pattern is concentrated, the polishing pressure per unit area of the interlayer insulating film is increased by such dishing, so that the metal wiring pattern is not concentrated. On the other hand, the interlayer insulating film erosion phenomenon occurs that the polishing of the interlayer insulating film proceeds rapidly.
CMP 공정시 이러한 금속 디싱과 층간절연막 침식 현상은 패턴 밀도에 크게 의존하기 때문에 CMP 공정후 웨이퍼 전체의 연마 균일도가 국부적으로 크게 차이나 나게 되어 후속 공정에 영향을 주게 된다. Since the metal dishing and the interlayer insulating film erosion during the CMP process are highly dependent on the pattern density, the polishing uniformity of the entire wafer after the CMP process is locally different, which affects subsequent processes.
이와 같은 문제점을 완화시키기 위하여 베리어 금속용 슬러리가 개발 중에 있다. 금속 디싱 및 층간절연막 침식 현상을 완화하기 위한 베리어 금속용 슬러리는 배선 금속에 대한 베리어 금속의 연마선택비가 매우 커야하는데 아직 이와 같은 특성을 지닌 슬러리는 개발되지 않았다.In order to alleviate this problem, a slurry for barrier metal is under development. The slurry for barrier metals to mitigate metal dishing and interlayer dielectric erosion should have a very high polishing selectivity of barrier metals to wiring metals. However, the slurry having such characteristics has not been developed yet.
본 발명은 베리어 금속/배선 금속으로 상감형 금속배선을 형성할 때, 금속 디싱 및 층간절연막 침식을 완화시킬 수 있는 반도체 소자의 금속배선 형성방법을 제공하는데 그 목적이 있다. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a metal wiring of a semiconductor device capable of alleviating metal dishing and erosion of an interlayer insulating film when forming a damascene metal wiring with a barrier metal / wiring metal.
상기의 기술적 과제를 해결하기 위한 본 발명은, 반도체 소자의 상감형 금속배선 형성방법에 있어서, 소정의 하부층이 형성된 반도체 기판 상부에 층간절연막을 형성하는 제1 단계; 상기 층간절연막을 선택 식각하여 콘택홀 및 라인용 트렌치를 형성하는 제2 단계; 상기 제2 단계 수행 후, 전체구조 상부에 베리어 금속 및 배선 금속을 형성하여 상기 라인용 트렌치를 매립하는 제3 단계; 화학·기계적 평탄화 공정을 실시하여 상기 베리어 금속이 노출될 정도로 상기 배선 금속을 연마하는 제4 단계; 및 스핀 에치 공정을 실시하여 상기 층간절연막 상의 상기 베리어 금속을 제거하는 제5 단계를 포함하여 이루어진다.According to an aspect of the present invention, there is provided a method of forming a damascene metal wiring for a semiconductor device, the method comprising: forming an interlayer insulating film on a semiconductor substrate on which a predetermined lower layer is formed; Selectively etching the interlayer insulating layer to form contact holes and trenches for lines; A third step of filling the trench for line by forming a barrier metal and a wiring metal on the entire structure after performing the second step; Performing a chemical and mechanical planarization process to polish the wiring metal to the extent that the barrier metal is exposed; And a fifth step of removing the barrier metal on the interlayer insulating layer by performing a spin etch process.
본 발명은 상감형 금속배선 형성시 베리어 금속과 배선 금속의 연마 선택비 차에 의해 발생하는 CMP 공정시의 금속 디싱 및 층간절연막 침식 현상을 완화시키기 위하여, 금속의 평탄화와 베리어 금속의 평탄화에 각각 다른 프로세스 즉, CMP와 스핀 에치를 적용하는 기술이다.In order to alleviate metal dishing and interlayer dielectric erosion during the CMP process caused by the difference in polishing selectivity between the barrier metal and the wiring metal when the inlaid metal wiring is formed, the planarization of the metal and the planarization of the barrier metal are different. This is a technique for applying CMP and spin etch to processes.
이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.
첨부된 도면 도 1a 내지 도 1c는 본 발명의 일 실시예에 따른 상감형 금속배선 형성 공정을 도시한 것으로, 이하 이를 참조하여 설명한다.1A to 1C illustrate a process of forming inlaid metal wirings according to an embodiment of the present invention, which will be described below with reference to the drawings.
본 실시예에 따른 공정은 다음과 같이 진행한다. 우선, 도 1a에 도시된 바와 같이 소정의 하부층 공정을 마치고 평탄화된 층간절연막(10)을 형성한 상태에서 층간절연막(10)을 선택 식각하여 콘택홀(도시되지 않음) 및 라인용 트렌치를 형성하고, 전체구조 상에 베리어 금속(11)과 배선 금속(12)을 차례로 증착한다.The process according to this embodiment proceeds as follows. First, as shown in FIG. 1A, after the predetermined lower layer process is finished, the interlayer insulating film 10 is selectively etched while the planarized interlayer insulating film 10 is formed to form contact holes (not shown) and trenches for lines. The barrier metal 11 and the wiring metal 12 are sequentially deposited on the entire structure.
다음으로, 도 1b에 도시된 바와 같이 금속 CMP 공정을 실시하여 배선 금속(12)을 평탄화한다. 이때, CMP는 배선 금속(12) 대 베리어 금속(11)의 연마선택비가 8:1 이상인 슬러리를 사용하여 베리어 금속(11)이 연마정지막처럼 작용하도록 실시한다.Next, as shown in FIG. 1B, a metal CMP process is performed to planarize the wiring metal 12. At this time, CMP is performed so that the barrier metal 11 acts like a polishing stop film by using a slurry having a polishing selectivity of the wiring metal 12 to the barrier metal 11 of 8: 1 or more.
계속하여, 도 1c에 도시된 바와 같이 배선 금속(12)에 대한 베리어 금속(11)의 식각 선택비가 매우 큰 용액을 사용하여 스핀 에치 방식으로 실시하여 층간절연막(10) 상의 베리어 금속(11)을 제거한다. 이때 사용되는 용액은 층간졀연막에 대해서도 고선택비를 갖는 것이 바람직하다.Subsequently, as shown in FIG. 1C, the barrier metal 11 on the interlayer insulating film 10 is formed by spin-etching using a solution having a very high etching selectivity of the barrier metal 11 with respect to the wiring metal 12. Remove It is preferable that the solution used at this time has a high selectivity also with respect to an interlayer film.
이후, 웨이퍼 표면에 잔류하는 잔류물 및 결함 제거 등을 목적으로 CMP 장비에서 버핑(buffing)하거나, 세정을 실시한다.Thereafter, for the purpose of removing residues and defects remaining on the wafer surface, buffing or cleaning is performed in the CMP equipment.
금속 CMP에 사용되는 상용화된 슬러리는 베리어 금속(Ti, TiN, Ta, TaN, WNx 등)에 대해 배선 금속보다 낮은 연마속도를 나타낸다. 특히, 알루미늄과 구리의 CMP 공정시 베리어 금속에 대한 연마선택비는 8:1 정도로 베리어 금속의 연마속도가 매우 낮다. 비록 금속배선 형성 공정에서 증착되는 베리어 금속의 두께는 수백 Å에 불과하지만 대부분의 금속 디싱과 층간절연막 침식 현상은 베리어 금속 연마 과정 중에 발생한다. 따라서, CMP 공정을 배선 금속의 제거로 한정하게 된다면 베리어 금속과 배선 금속의 큰 연마 선택비 차이에 의한 금속 디싱 및 층간절연막 침식 현상을 일차적으로 크게 줄일 수 있게 된다.Commercially available slurries used in metal CMP exhibit lower polishing rates than barrier metals for barrier metals (Ti, TiN, Ta, TaN, WN x, etc.). In particular, the polishing rate for the barrier metal in the CMP process of aluminum and copper is about 8: 1, the polishing rate of the barrier metal is very low. Although the barrier metal deposited in the metallization process is only a few hundreds of microns in thickness, most of the metal dishing and interlayer dielectric erosion occur during barrier metal polishing. Therefore, if the CMP process is limited to the removal of the wiring metal, the metal dishing and the interlayer insulating film erosion due to the large difference in polishing selectivity between the barrier metal and the wiring metal can be largely reduced.
또한, 층간절연막 상의 베리어 금속을 제거하는데 기계적인 힘을 가하지 않고 화학 용액을 사용하는데, 이때, 배선 금속에 대한 베리어 금속의 높은 식각선택비를 갖는 화학 용액을 선정해야 라인용 트렌치 부분에서 배선 금속의 추가적인 디싱이 발생하지 않게 된다. 또한 층간절연막에 대해 고선택비를 갖는 용액을 사용해야만 베리어 금속 제거시 층간절연막의 손상을 방지할 수 있다. 특히 웨이퍼 전체의 균일도를 좋게 하기 위해서 에칭 공정을 스핀 에치 방식으로 진행한다. In addition, a chemical solution is used without applying mechanical force to remove the barrier metal on the interlayer insulating film. In this case, a chemical solution having a high etching selectivity of the barrier metal to the wiring metal must be selected. No further dishing will occur. In addition, only a solution having a high selectivity with respect to the interlayer insulating film can be used to prevent damage to the interlayer insulating film when removing the barrier metal. In particular, in order to improve the uniformity of the entire wafer, the etching process is performed by spin etching.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
전술한 본 발명은 금속의 평탄화와 베리어 금속의 평탄화에 각각 다른 프로세스 즉, CMP와 스핀 에치를 적용함으로써 상감형 금속배선 형성시 베리어 금속과 배선 금속의 연마 선택비 차에 의해 발생하는 CMP 공정시의 금속 디싱 및 층간절연막 침식 현상을 완화시키는 효과가 있으며, 이로 인하여 후속 공정에 대한 공정마진의 확보가 용이할 분 아니라 수율의 증가를 기대할 수 있다. The present invention described above is applied to the planarization of the metal and the planarization of the barrier metal, that is, in the CMP process caused by the difference in the polishing selectivity of the barrier metal and the wiring metal when the inlay metal wiring is formed by applying CMP and spin etch. It is effective to alleviate metal dishing and interlayer dielectric erosion, and thus it is not easy to secure process margins for subsequent processes, but it is expected to increase yield.
도 1a 내지 도 1c는 본 발명의 일 실시예에 따른 상감형 금속배선 형성 공정도.1A to 1C are diagrams illustrating a process of forming an inlay metal wiring according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
10 : 층간절연막10: interlayer insulating film
11 : 베리어 금속11: Barrier Metal
12 : 배선 금속12: wiring metal
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| KR10-1999-0023308A KR100528449B1 (en) | 1999-06-21 | 1999-06-21 | Method for forming damascene type metal wire in semiconductor device using chemical mechanical planarization and spin etch process |
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| KR10-1999-0023308A KR100528449B1 (en) | 1999-06-21 | 1999-06-21 | Method for forming damascene type metal wire in semiconductor device using chemical mechanical planarization and spin etch process |
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