KR20020027695A - 반도체소자의 층간절연막 형성 방법 - Google Patents
반도체소자의 층간절연막 형성 방법 Download PDFInfo
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- KR20020027695A KR20020027695A KR1020000058270A KR20000058270A KR20020027695A KR 20020027695 A KR20020027695 A KR 20020027695A KR 1020000058270 A KR1020000058270 A KR 1020000058270A KR 20000058270 A KR20000058270 A KR 20000058270A KR 20020027695 A KR20020027695 A KR 20020027695A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
Abstract
본 발명은 막질을 향상시키고 보이드 없이 갭필특성이 우수한 층간절연막의 형성 방법에 관한 것으로, 반도체기판상에 다수의 패턴을 형성하는 제 1 단계; 상기 다수의 패턴을 포함한 전면에 제 1 절연막을 형성하는 제 2 단계; 상기 제 1 절연막의 표면에 유기용매제를 이용한 표면처리를 실시하는 제 3 단계; 및 상기 표면처리된 제 1 절연막상에 상기 패턴 사이를 매립하는 제 2 절연막을 형성하는 제 4 단계를 포함하여 이루어진다.
Description
본 발명은 반도체소자의 제조 방법에 관한 것으로, 특히 하부막과의 접합성을 높이고 막질 및 균일도를 높여 갭필특성을 향상시키도록 한 층간절연막의 형성 방법에 관한 것이다.
최근에 반도체 소자의 고집적화에 따라 고단차의 좁은 간격의 패턴사이를 내부 공극없이 절연막으로 채우고, 상기 절연막의 매립에 따른 단차를 줄이는 평탄화기술은 반도체소자의 제조에 있어 중요한 기술 중 하나로 대두되고 있다.
일반적으로 고단차의 좁은 패턴(Pattern) 사이를 매립하기 위하여 화학적기상증착법(Chemical Vapor Deposition; CVD)을 이용한 BPSG(Boro Phosphorous Silicate Glass), 고밀도플라즈마 화학기상증착법(High Density Plasma Chemical Vapor Deposition; HDP CVD), SOG(Spin On Glass)를 사용한다.
상기 BPSG막을 사용하는 경우, 막 안정성, 갭필한계성 및 고온열처리에 의한 한계성이 있으며, 상기 SOG를 이용하는 경우, 미세패턴 매립 특성이 우수하나 고온공정에서 크랙(Crack)이 발생되고, 작은 패턴크기에서는 평탄도와 절연막이 이루는 각도가 우수하나 현재 사용되고 있는 DRAM의 셀블록(Cell block)과 같은 넓은 패턴에서는 전체 단차를 낮추지 못하는 단점이 있다.
도 1에 도시된 것처럼, 상압 화학기상증착법(Chemical Vapor Deposition; CVD)에 의한 절연막의 증착에 있어서는 소자의 고밀도화에 따라 좁은 영역에서의 갭필시 형성된 상부 절연막(14)과 하부 절연막(13)간의 접착력이 떨어지므로써 계면상태가 불안정하며 상부 절연막(13)의 표면은 상당히 거칠고 막 내부에는 보이드(Void)(15)가 존재하며 갭은 채워지지 않은 채로 남아있게 된다. 미설명 도면부호 11은 반도체기판, 12는 도전층패턴을 나타낸다.
이를 해결하기 위하여 최근에 고밀도 플라즈마(High Density Plasma; HDP) 방법을 이용한 산화막 증착법이 주로 적용되고 있으나, 상기 고밀도 플라즈마 증착법은 증착과 함께 스퍼터 식각(Sputter etch)이 수반되기 때문에 증착 초기에 증착하고자 하는 패턴의 모서리가 식각되는 현상이 발생될 수 있으며, 또한 고가의 장비인 점을 고려하면 실제 생산에 따른 비용이 증가하는 문제점이 있다.
본 발명은 상기 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 좁은 패턴 사이를 매립함에 따른 보이드의 발생을 방지하고 막질이 불균일해지는 현상을 방지하는데 적합한 층간절연막의 형성 방법을 제공함에 그 목적이 있다.
도 1은 종래기술에 따른 층간절연막의 형성 방법을 도시한 도면,
도 2a는 본 발명의 실시예에 따른 표면처리공정의 흐름도
도 2b는 본 발명의 실시예에 따른 층간절연막의 형성 방법을 도시한 도면,
도 3a 및 도 3b는 표면처리전후의 하부 제 1 절연막의 상태를 도시한 도면.
*도면의 주요 부분에 대한 부호의 설명
31 : 반도체기판 32 : 도전층패턴
33 : 제 1 절연막 34 : O3-산화막
상기의 목적을 달성하기 위한 본 발명의 층간절연막 형성 방법은 반도체기판상에 다수의 패턴을 형성하는 제 1 단계; 상기 다수의 패턴을 포함한 전면에 제 1 절연막을 형성하는 제 2 단계; 상기 제 1 절연막의 표면에 유기용매제를 이용한 표면처리를 실시하는 제 3 단계; 및 상기 표면처리된 제 1 절연막상에 상기 패턴 사이를 매립하는 제 2 절연막을 형성하는 제 4 단계를 포함하여 이루어짐을 특징으로 한다.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.
도 2a는 본 발명의 실시예에 따른 표면처리 공정의 흐름도이고, 도 2b는 도 2a를 이용한 층간절연막의 형성 방법을 도시한 도면이다.
도 2a 및 도 2b를 참조하여 설명하면, 반도체기판(31)상에 도전층을 형성한 후, 상기 도전층을 선택적으로 식각하여 다수의 도전층패턴(32)을 형성한다(21). 여기서, 상기 도전층패턴(32)은 게이트전극, 워드라인 또는 비트라인 등의 패턴이며, 상기 도전층패턴(32)간 간극은 소자의 고집적도에 따라 매우 조밀하다.
이어서, 상기 도전층패턴(32)을 포함한 전면에 제 1 절연막(33)을 형성한 후(22), 상기 제 1 절연막(33)상에 스핀도포법(Spin coating)을 이용하여 에탄올 또는 메탄올 중 어느 하나의 유기용매제(Organic solvent)를 도포하고, 상기 유기용매제를 포어(Pour) 및 스프레드(Spread)시킨다(23∼24). 이 때, 상기 스핀도포시 회전속도는 2000rpm∼2500rpm이고, 유기용매제의 스프레드는 8∼20초동안 실시한다.
이어서, 상기 스프레드된 유기용매제를 스핀건조(Spin drying)시켜 제거한 후(25), 상기 표면처리된 제 1 절연막(33) 상에 상압 화학기상증착법으로 제 2 절연막으로서 오존(O3)이 첨가된 O3-산화막(34)을 형성한다(26).
여기서, 상기 스핀건조는 0.5∼1기압의 저압 산소분위기에서 5초∼10초동안 실시하고, 또한 스핀건조시 회전속는 1500rpm∼2000rpm이며, 온도는 28℃∼30℃이다.
도 3a 및 도 3b는 표면처리전후의 하부 제 1 절연막의 표면성질 변화를 나타낸 도면으로서, 표면처리전(도 3a)에는 제 1 절연막(33) 표면이 공기중의 수분에 노출되어 친수성(A)을 가지기 때문에 소수성인 절연막과의 결합력이 약해진다. 또한 친수성(A)인 표면은 수분과의 결합이 용이하기 때문에 막질의 저하를 초래한다.
반면, 유기용매제인 에탄올 또는 메탄올에 의한 표면처리후(도 3b), 하부 제 1 절연막(33)이 소수성(R)으로 성질변화를 일으켜 제 2 절연막인 O3-산화막(34)과의 결합력이 강화되고 우수한 갭필특성을 나타내며, 보이드가 발생되지 않는다.
상술한 바와 같이, 본 발명의 실시예에서는 고비용을 요구하는 고밀도 플라즈마 증착법을 이용하지 않고 상압 화학기상증착법을 이용하면서 하부 절연막과의결합력이 강하고 갭필특성이 우수하며 보이드가 발생되지 않는 절연막을 형성한다.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.
상술한 본 발명의 층간절연막 형성 방법은 패턴간 매립시 하부 절연막형성후 유기용매제를 이용한 표면처리를 실시하므로써 막질을 향상시키며 좁은 패턴사이에 갭필이 우수하고 막내부의 보이드를 제거할 수 있는 효과가 있다.
또한, 동일 절연막을 증착하기 위하여 새로운 공정 조건을 설정할 필요 없이 상압 화학기상증착법으로 막질이 우수하고 갭필특성이 우수한 절연막을 형성할 수 있으므로 비용이 절감되는 효과가 있다.
Claims (9)
- 반도체소자의 절연막 형성 방법에 있어서,반도체기판상에 다수의 패턴을 형성하는 제 1 단계;상기 다수의 패턴을 포함한 전면에 제 1 절연막을 형성하는 제 2 단계; 및상기 제 1 절연막의 표면에 유기용매제를 이용한 표면처리를 실시하는 제 3 단계; 및상기 표면처리된 제 1 절연막상에 상기 패턴 사이를 매립하는 제 2 절연막을 형성하는 제 4 단계를 포함하여 이루어짐을 특징으로 하는 절연막의 형성 방법.
- 제 1 항에 있어서,상기 표면처리후, 상기 제 1 절연막은 친수성에서 소수성으로 개질되는 것을 특징으로 하는 절연막의 형성 방법.
- 제 1 항에 있어서,상기 제 2 단계는,상기 다수의 패턴상에 상기 유기용매제를 도포하는 단계; 및상기 유기용매제를 스핀건조시키는 단계를 포함하여 이루어짐을 특징으로 하는 절연막의 형성 방법.
- 제 3 항에 있어서,상기 유기용매제는 에탄올 또는 메탄올 중 어느 하나를 이용하는 것을 특징으로 하는 절연막의 형성 방법.
- 제 3 항에 있어서,상기 유기용매제 도포시, 스핀도포법을 이용하며 2000rpm∼2500rpm의 회전속도로 이루어지는 것을 특징으로 하는 절연막의 형성 방법.
- 제 3 항에 있어서,상기 유기용매제 도포후, 8초∼20초의 시간동안 스프레드시키는 것을 특징으로 하는 절연막의 형성 방법.
- 제 3 항에 있어서,상기 유기용매제의 스핀건조시, 5초∼10초, 0.5∼1기압의 저압산소분위기에서 이루어지는 것을 특징으로 하는 절연막의 형성 방법.
- 제 3 항에 있어서,상기 유기용매제의 스핀건조시 1500rpm∼2000rpm의 회전속도로 28℃∼30℃에서 이루어지는 것을 특징으로 하는 절연막의 형성 방법.
- 제 1 항에 있어서,상기 제 2 절연막 형성시, 상압 화학기상증착법을 이용하여 오존이 첨가된 산화막을 형성하는 것을 특징으로 하는 절연막의 형성 방법.
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Cited By (207)
Publication number | Priority date | Publication date | Assignee | Title |
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KR20030002625A (ko) * | 2001-06-29 | 2003-01-09 | 주식회사 하이닉스반도체 | 반도체 소자의 제조방법 |
KR20140143694A (ko) * | 2013-06-07 | 2014-12-17 | 에이에스엠 아이피 홀딩 비.브이. | 기판의 홈을 절연막으로 채우는 방법 |
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