KR20020006105A - 반도체 패키지 - Google Patents
반도체 패키지 Download PDFInfo
- Publication number
- KR20020006105A KR20020006105A KR1020000039577A KR20000039577A KR20020006105A KR 20020006105 A KR20020006105 A KR 20020006105A KR 1020000039577 A KR1020000039577 A KR 1020000039577A KR 20000039577 A KR20000039577 A KR 20000039577A KR 20020006105 A KR20020006105 A KR 20020006105A
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor chip
- circuit
- semiconductor package
- circuit component
- lead
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
Claims (11)
- 반도체 칩과;상기 반도체 칩이 장착되고, 일정 패턴의 회로배선이 형성되어 상기 회로배선 일단이 상기 반도체 칩과 와이어본딩되는 회로구성부재와;상기 회로구성부재의 둘레 가장자리부에서 회로배선 타단과 접착 연결되는 리드와;상기 리드에 지지되어 상기 반도체 칩의 상부에서 상기 반도체 칩이 발생시키는 전자파를 차단하는 전자파차단부재와;상기 반도체 칩, 회로구성부재, 그리고 전자파차단부재를 외부로부터 보호하는 몰드몸체를 포함하여 구성되는 반도체 패키지.
- 제1항에 있어서,상기 회로구성부재의 하면이 몰드몸체의 외부로 노출되는 것을 특징으로 하는 반도체 패키지.
- 제1항에 있어서,상기 전자파차단부재가 몰드몸체의 외부로 노출되는 것을 특징으로 하는 반도체 패키지.
- 제2항에 있어서,상기 회로구성부재의 하면에는 솔더볼이 구비됨과 함께 상기 솔더볼에 상기 회로구성부재의 회로배선 타단이 연결되는 것을 특징으로 하는 반도체 패키지
- 제1항 내지 제4항 중 어느 한 항에 있어서,상기 전자파차단부재는 메쉬형으로 이루어지는 것을 특징으로 하는 반도체 패키지.
- 제5항에 있어서,상기 회로구성부재와 상기 리드는 전도성 에폭시에 의해 연결되는 것을 특징으로 하는 반도체 패키지.
- 제6항에 있어서,상기 회로구성부재는 회로테이프임을 특징으로 하는 반도체 패키지.
- 제6항에 있어서,상기 회로구성부재는 회로기판임을 특징으로 하는 반도체 패키지.
- 제1항 내지 제3항 중 어느 한 항에 있어서,상기 회로구성부재의 저면에는 다른 전자파차단부재가 부착되는 것을 특징으로 하는 반도체 패키지.
- 반도체 칩을 회로구성부재에 장착하고 상기 반도체 칩과 상기 회로구성부재를 와이어본딩하는 단계와;리드프레임의 패들에 미세한 작은 구멍을 뚫어 메쉬형상의 전자파차단부재를 형성하고, 상기 전자파차단부재를 리드보다 높은 상측에 위치시키는 단계와;상기 리드프레임의 리드의 하면 또는, 상기 회로구성부재의 회로배선의 타단 상면에 접착제를 도포하는 단계와;상기 리드프레임과 상기 회로구성부재를 접착 연결함으로써 상기 반도체 칩의 상부에 전자파차단부재를 위치시키는 단계;상기 반도체 칩을 몰딩하여 몸체를 형성하는 단계를 포함하여 제조되는 반도체 패키지 제조방법.
- 제10항에 있어서,상기 회로구성부재의 회로배선 타단과 연결되도록 상기 회로구성부재의 하면에 솔더볼을 구비하는 단계를 더 포함하여 제조되는 것을 특징으로 하는 반도체 패키지 제조방법.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020000039577A KR100595317B1 (ko) | 2000-07-11 | 2000-07-11 | 반도체 패키지 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020000039577A KR100595317B1 (ko) | 2000-07-11 | 2000-07-11 | 반도체 패키지 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20020006105A true KR20020006105A (ko) | 2002-01-19 |
KR100595317B1 KR100595317B1 (ko) | 2006-07-03 |
Family
ID=19677360
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020000039577A KR100595317B1 (ko) | 2000-07-11 | 2000-07-11 | 반도체 패키지 |
Country Status (1)
Country | Link |
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KR (1) | KR100595317B1 (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2018152378A1 (en) * | 2017-02-15 | 2018-08-23 | Texas Instruments Incorporated | Semiconductor package with a wire bond mesh |
-
2000
- 2000-07-11 KR KR1020000039577A patent/KR100595317B1/ko active IP Right Grant
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2018152378A1 (en) * | 2017-02-15 | 2018-08-23 | Texas Instruments Incorporated | Semiconductor package with a wire bond mesh |
US10204842B2 (en) | 2017-02-15 | 2019-02-12 | Texas Instruments Incorporated | Semiconductor package with a wire bond mesh |
US11121049B2 (en) | 2017-02-15 | 2021-09-14 | Texas Instruments Incorporated | Semiconductor package with a wire bond mesh |
Also Published As
Publication number | Publication date |
---|---|
KR100595317B1 (ko) | 2006-07-03 |
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