KR200176109Y1 - Semiconductor package - Google Patents

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Publication number
KR200176109Y1
KR200176109Y1 KR2019990018833U KR19990018833U KR200176109Y1 KR 200176109 Y1 KR200176109 Y1 KR 200176109Y1 KR 2019990018833 U KR2019990018833 U KR 2019990018833U KR 19990018833 U KR19990018833 U KR 19990018833U KR 200176109 Y1 KR200176109 Y1 KR 200176109Y1
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South Korea
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conductive pattern
chip
resin layer
semiconductor package
semiconductor
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KR2019990018833U
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Korean (ko)
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김승모
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아남반도체주식회사
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Priority to KR2019990018833U priority Critical patent/KR200176109Y1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/0209—External configuration of printed circuit board adapted for heat dissipation, e.g. lay-out of conductors, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

본 고안은 반도체 패키지에 관한 것으로, 전원용 전도성패턴에 반도체 칩의 저면과 접촉되도록 한 중첩부를 형성하여, 칩에서 발생되는 열이 중첩부를 통하여 전도되도록 함으로써, 열 방출 경로를 단축하며 칩에서 발생되는 열을 효율적으로 방출할 수 있도록 구성한 반도체 패키지를 제공하고자 한 것이다.The present invention relates to a semiconductor package, by forming an overlapping portion in contact with the bottom surface of the semiconductor chip in the power supply conductive pattern, the heat generated from the chip is conducted through the overlapping portion, shortening the heat emission path and heat generated from the chip To provide a semiconductor package configured to efficiently discharge the.

Description

반도체 패키지{Semiconductor package}Semiconductor Package {Semiconductor package}

본 고안은 반도체 패키지에 관한 것으로, 더욱 상세하게는 칩에서 발생되는 열방출 경로를 단축하여 칩에서 발생되는 열을 효율적으로 방출할 수 있도록 구성한 반도체 패키지에 관한 것이다.The present invention relates to a semiconductor package, and more particularly, to a semiconductor package configured to shorten the heat dissipation path generated from the chip to efficiently discharge heat generated from the chip.

통상적으로 반도체 패키지의 구조는 웨이퍼에서 소잉된 각 반도체 칩이 리드 프레임상에 형성되어 있는 다이패드에 에폭시로 접착되어 있고, 이 접착된 반도체 칩의 본딩패드와 상기 리드 프레임의 리드간에 와이어가 연결되어 있으며, 상기 반도체 칩과 와이어등은 몰딩 컴파운드 수지로 몰딩되어 감싸여진 구조로 이루어져 있다.In general, the structure of a semiconductor package is epoxy bonded to a die pad on which each semiconductor chip sourced from a wafer is formed on a lead frame, and a wire is connected between the bonding pad of the bonded semiconductor chip and the lead of the lead frame. The semiconductor chip, the wire, and the like have a structure that is molded and wrapped with a molding compound resin.

또한, 상기와 같은 통상적인 구조의 반도체 패키지 뿐만아니라, 전자기기의 집약적 발달과 소형화 경향으로 인하여 고집적화, 소형화, 고기능화의 추세에 병행하여, 상기 다이패드의 저면이 외부로 노출되어진 구조의 EPP(Exposed pad package) 반도체 패키지, 볼 그리드 어레이 반도체 패키지, 인쇄회로기판을 이용한 반도체 패키지등 다양한 종류의 반도체 패키지가 경박단소화로 개발되어 왔고, 개발중에 있다.In addition to the semiconductor package of the conventional structure as described above, due to the intensive development and miniaturization tendency of electronic devices, in parallel to the trend of high integration, miniaturization, and high functionality, the bottom surface of the die pad is exposed to the outside. pad package) A variety of semiconductor packages, such as semiconductor packages, ball grid array semiconductor packages, and semiconductor packages using printed circuit boards, have been developed and are being developed in a light and small size.

특히, 상기 나열한 반도체 패키지중에 볼 그리드 어레이 반도체 패키지의 구조를 보면, 첨부한 도 2에 도시한 바와 같이 일정면적의 수지층(26)과 이 수지층(26) 상면에 식각 처리되어 부착되어 있는 전도성패턴(12),(14),(18)과 수지층(26)의 저면에 비아홀(34)로 연결되어 상기 전도성패턴과 접속되도록 한 랜드(36)로 구성된 인쇄회로기판(32)과, 이 인쇄회로기판(32)의 수지층(26) 상면 중앙부위에 접착수단으로 부착되는 반도체 칩(16)과, 상기 칩(16)의 본딩패드와 전도성 패턴간에 연결되는 와이어(28)와, 상기 전도성패턴, 칩, 와이어 등을 몰딩하고 있는 수지(20)와, 상기 수지층(26)의 저면에 형성되어 있는 랜드(36)에 반도체 칩(16)의 입출력 단자의 역할을 하도록 부착되는 인출단자(30)로 구성되어 있다.In particular, the structure of the ball grid array semiconductor package among the semiconductor packages listed above, as shown in the accompanying FIG. 2, has a conductive area which is etched and attached to the resin layer 26 having a predetermined area and the upper surface of the resin layer 26. A printed circuit board 32 composed of patterns 12, 14, 18 and lands 36 connected to the bottom surface of the resin layer 26 by via holes 34 so as to be connected to the conductive patterns; A semiconductor chip 16 attached to a central portion of the upper surface of the resin layer 26 of the printed circuit board 32 by an adhesive means, a wire 28 connected between the bonding pad of the chip 16 and the conductive pattern, and the conductive A drawing terminal attached to the resin 20 molding a pattern, a chip, a wire, or the like, and a land 36 formed on the bottom of the resin layer 26 to serve as an input / output terminal of the semiconductor chip 16. 30).

첨부한 도 1은 종래의 부재 즉, 인쇄회로기판상에 전도성패턴이 형성되어 있는 모양을 나타내는 평면도로서, 인쇄회로기판(32)의 수지층(26) 상면에서 칩(16)이 실장되는 영역에 접지용 전도성패턴(14)이 형성되어 있고, 그 바깥쪽으로 접촉되지 않으며 전원용 전도성패턴(12)이 형성되어 있으며, 또한 전원용 전도성패턴(12)의 외측으로 신호전달용 전도성패턴(18)이 형성되어 있다.1 is a plan view showing a shape in which a conductive pattern is formed on a conventional member, that is, a printed circuit board, and is located in a region where the chip 16 is mounted on the upper surface of the resin layer 26 of the printed circuit board 32. The grounding conductive pattern 14 is formed, and the conductive pattern 12 for the power source is formed without contact with the outside thereof, and the conductive pattern 18 for signal transmission is formed outside the conductive pattern 12 for the power source. have.

상기와 같이 형성되어 있는 인쇄회로기판의 접지용 전도성패턴(14) 위로 반도체 칩(16)이 실장되어 첨부한 도 2와 같은 구조의 반도체 패키지가 제조되는 바, 이 반도체 패키지(10)의 열방출경로를 살펴보면 다음과 같다.The semiconductor package having the structure as shown in FIG. 2 is manufactured by mounting the semiconductor chip 16 on the grounding conductive pattern 14 of the printed circuit board formed as described above, and heat dissipation of the semiconductor package 10 is performed. The path is as follows.

반도체 칩(16)에서 열이 발생하게 되면, 이 열을 칩과 닿아 있는 접지용 전도성패턴(14)으로 1차 전도되고, 그 다음으로 수지층(26), 전원용 전도성패턴(12), 다시 수지층(26)과 신호전달용 전도성패턴(18)의 순서로 전도되어 열방출이 이루어진다.When heat is generated in the semiconductor chip 16, the heat is first conducted to the grounding conductive pattern 14 which is in contact with the chip, and then the resin layer 26, the conductive pattern 12 for the power source, and again, The heat is generated by conducting in the order of the ground layer 26 and the conductive pattern 18 for signal transmission.

상기와 같은 경로를 거쳐 이루어지는 열방출은 그 경로의 수가 많아 열방출의 효과를 극대화시키지 못하는 단점이 있다.The heat dissipation made through the path as described above has a disadvantage in that the number of paths does not maximize the effect of heat dissipation.

본 고안은 상기와 같은 점을 감안하여 안출한 것으로써, 전원용 전도성패턴에 반도체 칩의 저면과 접촉되도록 한 중첩부를 형성하여, 칩에서 발생되는 열이 중첩부를 통하여 전도되도록 함으로써, 열 방출 경로를 단축하며 칩에서 발생되는 열을 효율적으로 방출할 수 있도록 구성한 반도체 패키지를 제공하는데 그 목적이 있다.The present invention devised in view of the above, by forming an overlapping portion in contact with the bottom surface of the semiconductor chip in the conductive pattern for the power supply, the heat generated from the chip is conducted through the overlapping portion, shortening the heat discharge path In addition, the object of the present invention is to provide a semiconductor package configured to efficiently discharge heat generated from a chip.

도 1 은 종래의 반도체 패키지의 부재를 나타내는 평면도,1 is a plan view showing a member of a conventional semiconductor package,

도 2 는 종래의 반도체 패키지를 단면도,2 is a cross-sectional view of a conventional semiconductor package,

도 3 은 본 고안에 따른 반도체 패키지의 부재를 나타내는 평면도,3 is a plan view showing a member of a semiconductor package according to the present invention,

도 4 는 본 고안에 따른 반도체 패키지를 나타내는 단면도.4 is a cross-sectional view showing a semiconductor package according to the present invention.

＜도면의 주요 부분에 대한 부호의 설명><Description of the code | symbol about the principal part of drawing>

10 : 반도체 패키지 12 : 전원용 전도성패턴10: semiconductor package 12: conductive pattern for power

14 : 접지용 전도성패턴 16 : 칩14: conductive pattern for grounding 16: chip

18 : 신호전달용 전도성패턴 20 : 수지18: conductive pattern for signal transmission 20: resin

22 : 중첩부 26 : 수지층22: overlapping portion 26: resin layer

28 : 와이어 30 : 인출단자28: wire 30: drawing terminal

32 : 인쇄회로기판32: printed circuit board

이하 본 고안을 첨부된 도면을 참조하여 설명하면 다음과 같다.Hereinafter, the present invention will be described with reference to the accompanying drawings.

본 고안은 일정면적의 수지층(26)과 이 수지층(26) 상면에 식각 처리되어 부착되어 있는 접지용, 전원용, 신호전달용 전도성패턴(12),(14),(18)과 수지층(26)의 저면에 비아홀(34)로 연결되어 상기 전도성패턴과 접속되도록 한 랜드(36)로 구성된 인쇄회로기판(32)과, 이 인쇄회로기판의 수지층(26) 상면 중앙부위에 접착수단으로 부착되는 반도체 칩(16)과, 상기 칩(16)의 본딩패드와 전도성 패턴간에 연결되는 와이어(28)와, 상기 전도성패턴, 칩, 와이어 등을 몰딩하고 있는 수지(20)와, 상기 수지층(26)의 저면에 형성되어 있는 랜드(36)에 반도체 칩(16)의 입출력 단자의 역할을 하도록 부착되는 인출단자(30)로 구성된 반도체 패키지에 있어서, 상기 전원용 전도성패턴(12)에 반도체 칩(16)의 저면과 접촉되어 있는 상기 접지용 전도성패턴(14)의 사이로 연장되는 동시에 상기 칩(16)의 저면과 접촉되도록 한 다수의 중첩부(22)를 일체로 형성하여서 이루어진 것을 특징으로 한다.The present invention has a resin layer 26 having a predetermined area, and conductive patterns 12, 14, and 18 for grounding, power supply, and signal transmission, which are etched on the upper surface of the resin layer 26, and the resin layer. A printed circuit board 32 composed of lands 36 connected to the bottom surface of the bottom surface 26 by via holes 34 and connected to the conductive pattern, and adhesive means attached to the upper surface of the resin layer 26 of the printed circuit board. A semiconductor chip 16 attached thereto, a wire 28 connected between a bonding pad of the chip 16 and a conductive pattern, a resin 20 molding the conductive pattern, a chip, a wire, and the like, and the number In the semiconductor package consisting of the extraction terminal 30 attached to the land 36 formed on the bottom of the ground layer 26 to serve as an input / output terminal of the semiconductor chip 16, the semiconductor is formed on the conductive pattern 12 for the power supply. Extends between the ground conductive patterns 14 in contact with the bottom of the chip 16 and simultaneously That made hayeoseo form an overlapping portion 22 such that a plurality of contact with the bottom surface of the chip 16 integrally features.

특히, 상기 접지용 전도성패턴(12)은 방사형으로 형성되고, 상기 전원용 전도성패턴(12)의 중첩부(22)는 상기 접지용 전도성패턴(12)의 방사형 사이 공간에 위치되어진다.In particular, the grounding conductive pattern 12 is radially formed, and the overlapping portion 22 of the power conductive pattern 12 is located in the radial interspace of the grounding conductive pattern 12.

본 고안을 실시예로서, 첨부도면을 참조로 더욱 상세하게 설명하면 다음과 같다.As an embodiment, the present invention will be described in more detail with reference to the accompanying drawings.

첨부한 도 3은 본 고안에 따른 반도체 패키지에 사용되는 부재 즉, 인쇄회로기판을 나타내는 개략도로서, 인쇄회로기판(32)의 수지층(26) 상면에서 칩(16)이 실장되는 영역에 접지용 전도성패턴(14)이 형성되는 바, 이 접지용 전도성패턴(14)은 중심점을 기준으로 여러 갈래의 띠편이 연장된 것과 같은 방사형으로 형성된다.FIG. 3 is a schematic view showing a member, that is, a printed circuit board, used in the semiconductor package according to the present invention, and is used for grounding in the region where the chip 16 is mounted on the upper surface of the resin layer 26 of the printed circuit board 32. As the conductive pattern 14 is formed, the grounding conductive pattern 14 is formed radially such that several strips of strips extend from the center point.

또한, 상기 접지용 전도성패턴(14)의 바깥쪽으로 전원용 전도성패턴(12)이 위치되어 형성되는데, 상기 전원용 전도성패턴(14)의 안쪽에는 상기 접지용 전도성패턴(12)의 방사형 사이의 공간으로 연장되는 다수의 중첩부(22)가 일체로 형성된다.In addition, a power conductive pattern 12 is positioned and formed outside the ground conductive pattern 14, and extends into a space between radials of the ground conductive pattern 12 inside the power conductive pattern 14. A plurality of overlapping portions 22 are formed integrally.

또한, 상기 전원용 전도성패턴(14)의 외측으로는 신호전달용 전도성패턴(18)이 형성되어 있다.In addition, a conductive pattern 18 for signal transmission is formed outside the conductive pattern 14 for power.

상기와 같은 구조의 인쇄회로기판을 이용하여 제조된 반도체 패키지는 첨부한 도 4에 도시한 바와 같으며, 이것의 구조와 열방출경로에 대하여 설명하면 다음과 같다.The semiconductor package manufactured using the printed circuit board having the above structure is as shown in FIG. 4, and the structure and heat dissipation path thereof are as follows.

본 고안의 반도체 패키지는 칩(16)의 저면에 인쇄회로기판(32)의 수지층(26) 상면에 형성된 상기 접지용 전도성패턴(14)과 전원용 전도성패턴(12)의 중첩부(22)가 접촉되며 위치되어 있고, 물론 전원용 전도성패턴(12)의 외측으로 신호전달용 전도성패턴(18)이 형성되어 있고, 각각의 전도성패턴(12),(14),(18)들의 본딩영역과 반도체 칩(16)의 본딩패드간에는 와이어(28)가 연결되어 있으며, 상기 칩(16)과 와이어(28)와 전도성패턴들이 수지(20)로 몰딩되어 이루어진 구조이다.In the semiconductor package of the present invention, the overlapping portion 22 of the ground conductive pattern 14 and the power conductive pattern 12 formed on the top surface of the resin layer 26 of the printed circuit board 32 is formed on the bottom surface of the chip 16. In contact with each other, the conductive patterns 18 for signal transmission are formed on the outside of the conductive patterns 12 for the power supply, and the bonding regions and semiconductor chips of the respective conductive patterns 12, 14, and 18 are formed. A wire 28 is connected between the bonding pads of the 16, and the chip 16, the wire 28, and the conductive patterns are molded by the resin 20.

따라서, 상기 반도체 칩(16)에서 발생되는 열의 방출경로는 반도체 칩으로부터 접지용 전도성패턴(14)으로 1차 전도되고, 그 다음으로 수지층(26), 전원용 전도성패턴(12), 다시 수지층(26)과 신호전달용 전도성패턴(18)의 순서로 전도되어 열방출이 이루어지기도 하지만, 반도체 칩(16)으로부터 상기 전원용 전도성패턴(12)의 중첩부(22)로 열이 일차로 전도되고, 그 다음으로 수지층(26)과 신호전달용 전도성패턴(18)의 순서로 열이 방출되어진다.Therefore, the heat emission path generated from the semiconductor chip 16 is first conducted from the semiconductor chip to the ground conductive pattern 14, and then the resin layer 26, the power conductive pattern 12, and then the resin layer. (26) and the conductive pattern for signal transmission (18) in order to heat dissipation, but heat is first conducted from the semiconductor chip 16 to the overlapping portion 22 of the conductive pattern 12 for the power source Then, heat is released in the order of the resin layer 26 and the conductive pattern 18 for signal transmission.

이에따라, 종래의 열방출경로중에 접지용 전도성패턴(14)과 수지층(26)이 배제되는 열방출 경로의 단축으로 인하여, 본 고안의 반도체 패키지의 열방출은 더욱 효율적으로 이루어지게 된다.Accordingly, due to the shortening of the heat dissipation path in which the grounding conductive pattern 14 and the resin layer 26 are excluded in the conventional heat dissipation path, the heat dissipation of the semiconductor package of the present invention is made more efficient.

이상 상술한 바와 같이, 본 고안에 따른 반도체 패키지에 의하면, 전원용 전도성패턴에 반도체 칩의 저면과 접촉되도록 한 중첩부를 형성하여, 칩에서 발생되는 열이 중첩부를 통하여 전도되도록 함으로써, 열 방출 경로를 단축하며 칩에서 발생되는 열을 효율적으로 방출시킬 수 있는 잇점이 있다.As described above, according to the semiconductor package according to the present invention, by forming an overlapping portion in contact with the bottom surface of the semiconductor chip in the power supply conductive pattern, the heat generated from the chip is conducted through the overlapping portion, thereby shortening the heat emission path It also has the advantage of efficiently dissipating heat generated from the chip.

Claims (2)

일정면적의 수지층(26)과 이 수지층(26) 상면에 식각 처리되어 부착되어 있는 접지용, 전원용, 신호전달용 전도성패턴(12),(14),(18)과 수지층(26)의 저면에 비아홀(34)로 연결되어 상기 전도성패턴과 접속되도록 한 랜드(36)로 구성된 인쇄회로기판(32)과, 이 인쇄회로기판의 수지층(26) 상면 중앙부위에 접착수단으로 부착되는 반도체 칩(16)과, 상기 칩(16)의 본딩패드와 전도성 패턴간에 연결되는 와이어(28)와, 상기 전도성패턴, 칩, 와이어 등을 몰딩하고 있는 수지(20)와, 상기 수지층(26)의 저면에 형성되어 있는 랜드(36)에 반도체 칩(16)의 입출력 단자의 역할을 하도록 부착되는 인출단자(30)로 구성된 반도체 패키지에 있어서,Grounding, power, and signal transmission conductive patterns 12, 14, 18 and resin layer 26, which are attached to the resin layer 26 and the upper surface of the resin layer 26 by etching. A printed circuit board 32 composed of lands 36 connected to the bottom surface of the printed circuit board by via holes 34 to be connected to the conductive pattern, and attached to a central portion of the upper surface of the resin layer 26 of the printed circuit board by adhesive means. The semiconductor chip 16, the wire 28 connected between the bonding pad of the chip 16 and the conductive pattern, the resin 20 molding the conductive pattern, the chip, the wire, and the like, and the resin layer 26. In the semiconductor package consisting of the extraction terminal 30 is attached to the land 36 formed on the bottom surface of the c) to serve as an input / output terminal of the semiconductor chip 16, 상기 전원용 전도성패턴(12)에 반도체 칩(16)의 저면과 접촉되어 있는 상기 접지용 전도성패턴(14)의 사이로 연장되는 동시에 상기 칩(16)의 저면과 접촉되도록 한 다수의 중첩부(22)를 일체로 형성하여서 이루어진 것을 특징으로 하는 반도체 패키지.A plurality of overlapping portions 22 extending between the grounding conductive patterns 14 in contact with the bottom surface of the semiconductor chip 16 in the power supply conductive pattern 12 and in contact with the bottom surface of the chip 16. Semiconductor package characterized in that formed by integrally. 제 1 항에 있어서, 상기 접지용 전도성패턴(12)은 방사형으로 형성되고, 상기 전원용 전도성패턴(12)의 중첩부(22)는 상기 접지용 전도성패턴(12)의 방사형 사이 공간에 위치되는 것을 특징으로 하는 반도체 패키지The method of claim 1, wherein the grounding conductive pattern 12 is formed radially, the overlapping portion 22 of the power conductive pattern 12 is located in the radial interspace of the grounding conductive pattern 12. Featured semiconductor package
KR2019990018833U 1999-09-06 1999-09-06 Semiconductor package KR200176109Y1 (en)

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