KR200168998Y1 - Lead frame of loc type - Google Patents

Lead frame of loc type Download PDF

Info

Publication number
KR200168998Y1
KR200168998Y1 KR2019940034592U KR19940034592U KR200168998Y1 KR 200168998 Y1 KR200168998 Y1 KR 200168998Y1 KR 2019940034592 U KR2019940034592 U KR 2019940034592U KR 19940034592 U KR19940034592 U KR 19940034592U KR 200168998 Y1 KR200168998 Y1 KR 200168998Y1
Authority
KR
South Korea
Prior art keywords
lead
lead frame
bonding wire
insulating film
leads
Prior art date
Application number
KR2019940034592U
Other languages
Korean (ko)
Other versions
KR960025504U (en
Inventor
엄재철
오진근
Original Assignee
김영환
현대전자산업주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김영환, 현대전자산업주식회사 filed Critical 김영환
Priority to KR2019940034592U priority Critical patent/KR200168998Y1/en
Publication of KR960025504U publication Critical patent/KR960025504U/en
Application granted granted Critical
Publication of KR200168998Y1 publication Critical patent/KR200168998Y1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49586—Insulating layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

본 고안은 고집적 메모리 제품용 LOC 타입의 리드 프레임에 관한 것으로, 리드 전체 상부에 절연막을 증착하고, 상기 절연막 중 칩상부의 패드와 본딩 와이어로 연결될 리드의 소정부위에 증착된 절연막을 선택적으로 제거하여, 패키지 공정시 리드 프레임의 리드와 칩 패드간을 연결하는 본딩 와이어가 그 하부에 위치한 파워라인용 리드와 몰딩 컴파운드가 덮여짐으로 인해 접촉되는 것을 방지하기 위한 것이며, 본딩 와이어가 하부 파워라인용 리드와의 접촉에 의한 단락 및 상호 간섭에 의한 제품특성의 저하를 방지함과 아울러, 초고집적 메모리 반도체 패키지에서 리드 프레임의 리드간의 간격이 더욱 좁아져도 전기적인 간섭이 작아지므로 메모리 고집적화에 기여할 수 있는 LOC 타입 리드 프레임이다.The present invention relates to a LOC type lead frame for a high density memory product, which deposits an insulating film over the entire lead, and selectively removes the insulating film deposited on a predetermined portion of the lead to be connected to the pad and the bonding wire on the chip. In order to prevent the bonding wire connecting the lead of the lead frame and the chip pad from the package process from being contacted due to the covering of the power line lead and the molding compound, the bonding wire is connected to the lower power line lead. LOC can contribute to high memory density by preventing electrical degradation due to short-circuit and mutual interference due to contact with, and even narrower lead-to-lead spacing in ultra-high density memory semiconductor packages. Type lead frame.

Description

엘오시(LOC) 타입 리드 프레임LOC type lead frame

제1도는 종래의 엘오시 타입 리드 프레임에 있어서 와이어 본딩이 된 상태의 평면도.1 is a plan view of a state in which wire bonding is performed in a conventional ELOS type lead frame.

제2a도는 본 고안의 엘오시 타입 리드 프레임에 있어서 와이어 본딩이 된 후, 리드 프레임의 리드 전체 상부에 절연막을 증착하고, 본딩 와이어와 연결될 리드의 해당부위의 절연막을 선택적으로 식각한 상태의 평면도.FIG. 2A is a plan view of a state in which an insulating film is deposited on the entire lead of the lead frame after the wire bonding in the ELOS type lead frame of the present invention, and the insulating film of the corresponding portion of the lead to be connected to the bonding wire is selectively etched.

제2b도는 상기 제2a도 상태의 상부에 몰딩 컴파운드로 덮은 후의 A -A 선에 따른 단면도.FIG. 2B is a cross-sectional view taken along line A-A after being covered with a molding compound in an upper portion of the FIG. 2A state.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1, 2, 3, 4 : 리드(Lead) 5 : 반도체 칩1, 2, 3, 4: Lead 5: Semiconductor chip

6 : 몰딩 컴파운드 7 : 절연막6: molding compound 7: insulating film

8 : 접지전압(Vss)용 리드 9 : 전원전압(Vcc)용 리드8: Lead for ground voltage (Vss) 9: Lead for power voltage (Vcc)

10 : 본딩 와이어(Bonding wire) a, b, c, d, e, f : 패드(Pad)10: Bonding wire a, b, c, d, e, f: Pad

a', b', c', d', e', f' : 리드프레임상에서 와이어 본딩이 이뤄지는 리드부a ', b', c ', d', e ', f': lead part where wire bonding is done on lead frame

본 고안은 고집적 메모리 제품용 엘오시(Lead on chip ; 이하 'LOC'라함) 타입 리드 프레임(Lead frame)에 관한 것으로, 특히 리드 프레임의 리드 전체 상부에 절연막을 증착하여 파워라인용 리드와 파워라인 리드 상부로 지나는 본딩 와이어간의 상호 간섭에 의한 특성저하를 방지하여 반도체 소자의 제조공정 수율 및 신뢰성을 향상시킬 수 있는 엘오시 타입 리드 프레임에 관한 것이다.The present invention relates to a lead frame of a lead on chip (LOC) type for a highly integrated memory product, and in particular, by depositing an insulating film over the entire lead of the lead frame, the lead for the power line and the power line The present invention relates to an EL type lead frame capable of improving a manufacturing process yield and reliability of a semiconductor device by preventing a deterioration of characteristics due to mutual interference between bonding wires passing through a lead.

고집적 반도체 메모리 제품에 있어서, 패키지 면적을 줄이고 파워 라인의 노이즈를 줄이기 위하여 리드가 칩의 상부에 위치하는 LOC 형태의 리드 프레임이 사용된다.In highly integrated semiconductor memory products, a lead frame in the form of a LOC is used in which the lead is located on top of the chip in order to reduce package area and reduce noise in power lines.

제1도는 종래의 LOC 타입 리드 프레임에 있어서, 와이어 본딩이 된 상태의 평면도이다.1 is a plan view of a wire bonding state in a conventional LOC type lead frame.

상기 제1도에 도시된 바와 같이, 고집적 메모리 제품에 사용되는 종래의 LOC 타입의 리드 프레임은 접지전압(Vss)용 리드(8)와 전원전압(Vcc)용 리드(9)는 칩(5)의 상부에서 일자형의 막대(Bar) 형태로 배치된다. 따라서 칩(5)상의 패드(a,b,c,d)에서 각 리드(1,2,3,4)로 와이어 본딩을 하기 위해서는 본딩 와이어(10)가 리드 프레임의 파워라인용 리드(8,9) 상부를 지나게 되며, 본딩 와이어(10)와 파워라인용 리드(8,9) 사이에는 빈 공간이 생기게 된다.As shown in FIG. 1, a conventional LOC type lead frame used in a high density memory product includes a lead 8 for ground voltage Vss and a lead 9 for power supply voltage Vcc. It is arranged in the form of a straight bar at the top of the. Therefore, in order to wire bond the pads a, b, c, and d on the chips 5 to the leads 1, 2, 3, and 4, the bonding wire 10 is connected to the lead 8 for the power line of the lead frame. 9) It passes through the upper portion, there is an empty space between the bonding wire 10 and the power line lead (8, 9).

상기와 같이 칩(5) 상부의 패드(a, b, c, d)와 리드 프레임의 리드(1, 2, 3, 4) 사이에 본딩 와이어(10)가 연결된 후에는, 전체 상부에 몰딩 컴파운드(제2b도6)를 덮게 되는데, 이 때 몰딩 컴파운드(6)가 본딩 와이어(10)를 눌러 본딩 와이어(10)와 본딩 와이어(10)의 하부에 위치한 파워라인용 리드(8, 9) 간에 접촉이 이뤄지게 되고, 이로 인해 단락(Short) 및 상호 간섭을 초래하게 되며, 특히, 전원전압용 리드(9) 상부를 지나는 본딩 와이어가 연결된 리드(3, 4)의 경우에는, 전압 레벨에 있어 그 변화가 심하게 발생하여 전체 반도체 칩의 특성을 저하시키게 되는 문제점이 있다.After the bonding wire 10 is connected between the pads a, b, c, d on the chip 5 and the leads 1, 2, 3, 4 of the lead frame as described above, the molding compound is formed on the entire upper part. (B) of FIG. 6, wherein the molding compound 6 presses the bonding wire 10 between the bonding wire 10 and the power line leads 8 and 9 positioned below the bonding wire 10. Contact is made, which results in short and mutual interference, in particular in the case of leads 3 and 4 with bonding wires passing over the lead 9 for the supply voltage. There is a problem that the change occurs badly to degrade the characteristics of the entire semiconductor chip.

따라서 본 고안은 상기의 문제점을 해결하기 위하여 리드 프레임의 리드 전체 상부에 절연막을 형성하여 리드 프레임의 파워라인용 리드와 본딩 와이어 간의 접촉에 의한 상호간섭을 배제하여 제품의 특성저하를 방지하는 LOC 타입 리드 프레임을 제공함에 그 목적이 있다.Therefore, in order to solve the above problems, the present invention forms an insulating film over the entire lead of the lead frame to prevent the deterioration of the characteristics of the product by eliminating the mutual interference caused by the contact between the power line lead and the bonding wire of the lead frame. The purpose is to provide a lead frame.

상기 목적을 달성하기 위한 본 고안의 LOC 타입 리드 프레임은, 반도체 칩의 상부에서 일자형의 막대형태로 배치되는 접지전압(VSS)용 리드(8)와 전원전압(VCC)용 리드(9) 및 다수의 리드(1, 2, 3, 4)를 구비하는 LOC타입 리드프레임에 있어서, 상기 리드프레임의 리드 전체 상부에 절연막(7)이 형성되되, 본딩 와이어 (10)에 의해 칩상의 패드(a, b, c, d, e, f)와 각각 연결되는 리드 프레임의 리드(a', b', c', d', e', f') 해당부위에 증착된 절연막이 선택적으로 제거되게 하여 상기리드 프레임의 파워라인용 리드(8, 9) 상부를 지나는 본딩 와이어(10)가 그 하부의 파워라인용 리드(8, 9)와 접촉되는 것을 방지한 것을 특징으로 한다.LOC type lead frame of the present invention for achieving the above object, the lead 8 for the ground voltage (VSS) and the lead 9 for the power supply voltage (VCC) and a plurality of arranged in the form of a straight rod on the top of the semiconductor chip In a LOC type lead frame having leads 1, 2, 3, and 4, an insulating film 7 is formed over the entire lead of the lead frame, and the pads (a, b, c, d, e, and f of the lead frame (a ', b', c ', d', e ', f') of the lead frame respectively connected to the insulating film deposited on the corresponding portion is selectively removed It is characterized in that the bonding wire 10 passing through the power line leads 8 and 9 of the lead frame is prevented from contacting the power line leads 8 and 9 thereunder.

이하, 첨부된 도면을 참조하여 본 고안에 따른 LOC 타입 리드프레임의 적합한 실시예에 대한 상세한 설명을 하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the LOC type lead frame according to the present invention.

제2a도는 본 고안의 엘오시 타입 리드 프레임에 있어서 와이어 본딩이 된 후, 리드 프레임의 리드 전체 상부에 절연막을 증착하고, 본딩 와이어와 연결될 리드의 해당부위의 절연막을 선택적으로 식각한 상태의 평면도이고, 제2b도는 상기 제2a도 상태의 상부에 몰딩 컴파운드로 덮은 후의 A -A 선에 따른 단면도이다.FIG. 2a is a plan view of a state in which an insulating film is deposited on the entire lead of the lead frame in the ELOS type lead frame of the present invention, and an insulating film of a corresponding portion of the lead to be connected to the bonding wire is selectively etched. 2B is a cross-sectional view taken along the line A-A after being covered with a molding compound in the upper portion of the state of FIG. 2A.

상기 도면을 함께 참조하면, 본 고안의 엘오시 타입 리드 프레임은 리드 프레임의 리드(1, 2, 3, 4, 8, 9) 전체 상부에 절연막(7)을 증착하고, 본딩 와이어(10)와 연결될 리드의 해당부위(a', b', c', d', e', f')에 증착된 절연막을 선택적으로 식각에 의해 제거한다.Referring to the drawings together, the ELOS type lead frame according to the present invention deposits an insulating film 7 over the entire leads 1, 2, 3, 4, 8, and 9 of the lead frame, and bonds the wire 10 to the lead frame. The insulating film deposited on the corresponding portions (a ', b', c ', d', e ', f') of the lead to be connected is selectively removed by etching.

따라서, 와이어 본딩이 이루어진 후 몰딩 컴파운드(6)가 상부에 덮여짐으로 인해 리드 프레임의 리드(1, 2, 3, 4)와 칩상의 패드(a, b, c, d)에 연결되는 본딩와이어(10)가 그 하부에 위치한 파워라인용 리드(8, 9)와 서로 접촉되어도, 리드 프레임 상부에 기 증착된 절연막(7)에 의해 상호 간섭되는 것이 방지된다.Therefore, the bonding wire connected to the leads 1, 2, 3, 4 of the lead frame and the pads a, b, c, d of the lead frame because the molding compound 6 is covered on the upper side after the wire bonding is made. Even if the 10 is in contact with the power line leads 8 and 9 located below it, the mutual interference is prevented by the insulating film 7 previously deposited on the lead frame.

한편, 상기 리드 상부에 형성되는 절연막(7)은 예컨데, 실리콘 산화막 (SiO2) 또는 실리콘 나이트 라이드(Si3N4) 등의 물질을 사용한다.On the other hand, the insulating film 7 formed on the lead is made of a material such as silicon oxide film (SiO 2 ) or silicon nitride (Si 3 N 4 ).

따라서, LOC 타입의 리드 프레임의 리드 상부 전체에 절연물(7)을 증착함으로써 본딩 와이어(10)와 그 하부에 위치한 파워라인용 리드(8, 9)간에 접촉이 이루어짐에 의한 단락 및 상호 간섭에 의한 제품특성의 저하를 방지할 수 있으며, 아울러 초고집적 메모리 반도체 패키지에서 리드 프레임의 리드간의 간격이 더욱 좁아져도 전기적인 간섭이 작아지므로 메모리 고집적화에 기여할 수 있는 효과가 있다.Therefore, the short circuit and mutual interference caused by the contact between the bonding wire 10 and the power line leads 8 and 9 positioned below by depositing the insulator 7 all over the lead of the LOC type lead frame. Product characteristics can be prevented from deteriorating, and in the ultra-high-density memory semiconductor package, even if the spacing between the leads of the lead frame is further narrowed, the electrical interference is reduced, thereby contributing to the high memory integration.

이상에서 설명한 바와같이, 본 고안의 LOC 타입의 리드 프레임은 리드 전체 상부에 절연막을 증착하고, 본딩 와이어로 연결될 리드프레임의 리드 해당 부위상에 증착된 절연막을 선택적으로 제거하여, 패키지 공정시 리드 프레임의 리드와 칩 패드간에 연결되는 본딩 와이어가 그 하부에 위치한 파워라인용 리드와 몰딩 컴파운드가 덮여짐으로 인해 접촉될 시, 리드 프레임 상부에 증착된 절연막에 의해 상기 접촉에 의한 단락 및 상호간섭을 방지할 수 있다.As described above, the LOC type lead frame according to the present invention deposits an insulating film over the entire lead, and selectively removes the insulating film deposited on the corresponding lead portion of the lead frame to be connected by the bonding wire, thereby leading to the lead frame during the package process. When the bonding wire connected between the lead of the chip and the chip pad is contacted due to the covering of the power line lead and the molding compound, the short circuit and the interference caused by the contact are prevented by the insulating film deposited on the lead frame. can do.

Claims (2)

(정정)반도체 칩의 상부에서 일자형의 막대형태로 배치되는 접지전압(Vss)용 리드(8)와 전원전압(Vcc)용 리드(9) 및 다수의 리드(1, 2, 3, 4)를 구비하는 LOC 타입 리드프레임에 있어서, 상기 리드프레임의 리드 전체 상부에 절연막(7)이 형성되되, 본딩 와이어(10)에 의해 칩상의 패드(a, b, c, d, e, f)와 각각 연결되는 리드 프레임의 리드(a', b', c', d', e', f') 해당부위에 증착된 절연막이 선택적으로 제거되게 하여 상기 리드 프레임의 파워라인용 리드(8, 9) 상부를 지나는 본딩 와이어(10)가 그 하부의 파워라인용 리드(8, 9)와 접촉되는 것을 방지한 것을 특징으로 하는 LOC 타입 리드프레임On the top of the semiconductor chip, a lead 8 for ground voltage Vss, a lead 9 for power supply voltage Vcc, and a plurality of leads 1, 2, 3, 4 arranged in the shape of a straight rod In the LOC type lead frame provided, an insulating film 7 is formed on the entire lead of the lead frame, and each of the pads a, b, c, d, e, and f on the chip is bonded by a bonding wire 10. Leads 8 and 9 for the lead line of the lead frame are selectively removed by selectively removing the insulating film deposited on the corresponding portions of the leads a ', b', c ', d', e 'and f' of the lead frame to be connected. LOC type lead frame, characterized in that the bonding wire 10 passing through the upper portion is prevented from contacting the leads 8, 9 for power lines thereunder 제1항에 있어서 상기 절연막은 실리콘 산화막(SiO2) 또는 실리콘 나이트 라이드(Si3N4)의 물질인 것을 특징으로 하는 엘오시 타입 리드 프레임.2. The EL type lead frame of claim 1, wherein the insulating layer is formed of a silicon oxide layer (SiO 2 ) or a silicon nitride (Si 3 N 4 ).
KR2019940034592U 1994-12-19 1994-12-19 Lead frame of loc type KR200168998Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019940034592U KR200168998Y1 (en) 1994-12-19 1994-12-19 Lead frame of loc type

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019940034592U KR200168998Y1 (en) 1994-12-19 1994-12-19 Lead frame of loc type

Publications (2)

Publication Number Publication Date
KR960025504U KR960025504U (en) 1996-07-22
KR200168998Y1 true KR200168998Y1 (en) 2000-02-01

Family

ID=19401817

Family Applications (1)

Application Number Title Priority Date Filing Date
KR2019940034592U KR200168998Y1 (en) 1994-12-19 1994-12-19 Lead frame of loc type

Country Status (1)

Country Link
KR (1) KR200168998Y1 (en)

Also Published As

Publication number Publication date
KR960025504U (en) 1996-07-22

Similar Documents

Publication Publication Date Title
US7572680B2 (en) Packaged integrated circuit with enhanced thermal dissipation
US8053278B2 (en) Multi-chip package type semiconductor device
JP3676646B2 (en) Semiconductor package and manufacturing method thereof
US5563443A (en) Packaged semiconductor device utilizing leadframe attached on a semiconductor chip
US5539257A (en) Resin molded type semiconductor device having a conductor film
EP0710982B1 (en) Personalized area leadframe coining or half etching for reduced mechanical stress at device edge
US6815807B2 (en) Method of fabricating a redundant pinout configuration for signal enhancement in an IC package
KR200168998Y1 (en) Lead frame of loc type
US5841188A (en) Tape carrier structure for a tape carrier package
US5075758A (en) Semiconductor device
US6259152B1 (en) Hybrid leadframe having conductive leads less deformable and semiconductor device using the same
US5187558A (en) Stress reduction structure for a resin sealed semiconductor device
JP2539763B2 (en) Semiconductor device mounting method
US20100244275A1 (en) Contact structure for an electronic circuit substrate and electronic circuit comprising said contact structure
JP2885786B1 (en) Semiconductor device manufacturing method and semiconductor device
JPS62154769A (en) Semiconductor device
KR200163131Y1 (en) structure of semiconductor
JPH0476927A (en) Semiconductor integrated circuit
KR0140458B1 (en) Leadframe for semiconductor package
KR940008060A (en) Semiconductor integrated circuit device
KR100324602B1 (en) A manufacturing method of a semiconductor device capable of one-time package processing
KR19990034731A (en) Lead-on chip lead frames and packages using them
KR960013778B1 (en) Semiconductor memory device
KR100475340B1 (en) Lead-on Chip Package
KR0137068B1 (en) Lead frame

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
REGI Registration of establishment
FPAY Annual fee payment

Payment date: 20051019

Year of fee payment: 7

LAPS Lapse due to unpaid annual fee